KR20020051669A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A fabrication method of semiconductor devices is provided to considerably reduce a leakage current between a junction region and an isolation layer by preventing a metal interconnection from protruding into the isolation layer and a contact with the metal interconnection and a semiconductor substrate. CONSTITUTION: A STI(Shallow Trench Isolation) layer(52) having a groove is formed at an edge portion of a semiconductor substrate(50). An insulating material made of an insulating buffer and a polysilicon layer is filled into the groove of the STI layer(52). A gate electrode(60) and sidewall spacers(62) are formed on the semiconductor substrate(50). Epitaxial layers(64) are formed on both sides of the gate electrode(60) so as to grow the semiconductor substrate(50) with a defined height. At this time, the epitaxial layers(64) prevents a direct contact of a metal interconnection(70) with the semiconductor substrate(50) and the STI layer(52), thereby reducing a leakage current. Then, junction regions(65) are formed by implanting doped dopants.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing leakage current generated at an interface between a junction region of a MOS transistor and an element isolation film.

In addition to the advancement of semiconductor technology, high speed and high integration of semiconductor devices is progressing. In connection with this, the necessity of refinement | miniaturization with respect to a pattern becomes increasingly high, and the dimension of a pattern is also required for high precision. This also applies to device isolation regions that occupy a wide area in semiconductor devices.

LOCOS oxide films are mostly used as device isolation films of current semiconductor devices. This LOCOS device isolation film is obtained by selectively localizing a substrate.

However, the LOCOS isolation layer has a disadvantage in that a bird-shaped bird's beak is generated at an edge portion thereof, thereby generating a leakage current while increasing the area of the isolation layer.

Accordingly, a device isolation film of a shallow trench isolation (STI) method having a small width and excellent device isolation characteristics has been proposed.

1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device having an STI device isolation film.

Referring to FIG. 1, a pad oxide film (not shown) and a silicon nitride film (not shown) are sequentially stacked on the semiconductor substrate 10, and the silicon nitride film is patterned to expose the device isolation region. Next, the semiconductor substrate 10 exposed by the silicon nitride film is etched by a predetermined depth to form a shallow trench t. Thereafter, a high density plasma insulating film is embedded in the shallow trench t by an etching process to form the STI device isolation film 12. Next, after removing the silicon nitride film and the pad oxide film on the surface of the semiconductor substrate 10, the surface of the semiconductor substrate 10 is cleaned.

Subsequently, the gate insulating film 14 and the conductive layer are deposited on the semiconductor substrate 10, and then the conductive layer is partially patterned to form the gate electrode 16. The insulating film spacers 18 are formed on both sidewalls of the gate electrode 16 in a known manner. Next, impurities are implanted into the semiconductor substrate 10 outside the gate electrode 16 to form the junction region 20. As a result, the MOS transistor is completed.

An etch stopper 22 is deposited on the semiconductor substrate 10 on which the MOS transistor is formed. At this time, the etch stopper 22 is provided to prevent misalignment during the subsequent contact hole forming process. As the etch stopper 22, a silicon nitride film or a silicon nitride oxide film is used. An interlayer insulating film 24 is deposited on the etch stopper 22. Thereafter, the interlayer insulating film 24 and the etch stopper 22 are etched so that the gate electrode 16 and the junction region 20 are exposed to form a contact hole h. At this time, as the design rule of the semiconductor device is drastically reduced, the line width of the junction region 20 is also reduced, so that the contact hole h is closest to the junction region 20 and the device isolation film 12 even if misalignment does not occur. It is formed to expose the seat portion. Such a contact method is called a non overlap contact method. Thereafter, the metal wiring 26 is formed in the contact hole h to be in contact with the exposed gate electrode 16 and the junction region 20.

However, the conventional method of manufacturing a semiconductor device has the following problems.

In general, when forming the STI device isolation film 12, in order to embed the high density plasma insulating film in the shallow trench (t), the high density plasma insulating film (not shown) remaining on the substrate 10 is etched, and the substrate ( 10) The surface is being cleaned. At this time, during the etching and cleaning process, the edge portion of the STI device isolation layer 12 has an etching speed faster than that of the center portion, so that the insulating film at the edge portion is easily lost. As a result, grooving (g) occurs in the corner portion of the STI device isolation film 12 as shown in FIG. 1.

In addition, the depth of a general junction region is shallower on the element isolation region than on the active side. Accordingly, the depth of the grooving g may be deeper than the depth of the junction region 20. In this case, the metal wirings 26 embedded in the grooving g come into contact with not only the junction region 20 but also the semiconductor substrate 10. As a result, when a voltage is applied to the metal wiring 26, an electric field is concentrated at a portion that meets the metal wiring 26, the junction region 20, and the semiconductor substrate 10 to generate a severe leakage current.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of minimizing leakage current generated near the interface between the junction region of the MOS transistor and the device isolation film.

1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device having a conventional STI device isolation film.

2A through 2E are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

50-Semiconductor Substrate 52-STI Device Separator

54-buffer insulating film 56-polysilicon film

58-gate insulating film 60-gate electrode

62-spacer 64-epitaxial growth layer

66-etch stopper 68-interlayer dielectric

70-Metal Wiring T-Shallow Trench

G-Grooving H-Contact Hole

In order to achieve the above object of the present invention, the configuration of one embodiment of the present invention is as follows.

First, an element isolation film having grooves at an edge is formed in a predetermined portion on a semiconductor substrate. Subsequently, an insulator is embedded in the groove of the device isolation film, and then a gate electrode is formed in a predetermined portion on the semiconductor substrate. Thereafter, the semiconductor substrates on both sides of the gate electrode are grown by a predetermined height, and then impurity is implanted into the grown semiconductor substrate to form a junction region.

Here, the step of embedding the insulator in the groove, the step of depositing a buffer insulating film on the semiconductor substrate, the step of depositing a polysilicon film to a thickness such that the groove is buried on the buffer insulating film, buffering the polysilicon film Anisotropic etching to expose the insulating film, removing the buffer insulating film remaining on the surface of the substrate, and oxidizing the polysilicon film embedded in the groove.

In addition, the configuration of another embodiment of the present invention is as follows.

First, an element isolation film having grooves at an edge is formed in a predetermined portion on the semiconductor substrate, and then a polysilicon film is embedded in the grooves of the element isolation film. Next, the polysilicon film embedded in the groove is oxidized. Next, after the gate electrode is formed in a predetermined portion on the semiconductor substrate, the semiconductor substrates on both sides of the gate electrode are grown by a predetermined height, and impurities are then injected into the grown semiconductor substrate to form a junction region.

The embedding of the polysilicon film in the groove may include depositing a buffer insulating film on a semiconductor substrate, depositing a polysilicon film to a thickness such that the groove is buried above the buffer insulating film, and forming the polysilicon film. Anisotropic etching to expose the buffer insulating film, and removing the buffer insulating film remaining on the surface of the substrate. At this time, the polysilicon film is preferably deposited to a thickness of 100 to 500 kPa.

In addition, it is preferable that the semiconductor substrates on both sides of the gate electrode are grown by a selective epitaxial growth method and grown to a thickness higher than the height from the substrate to the device isolation layer and lower than the height of the gate electrode. More preferably, the semiconductor substrates on both sides of the gate electrode are grown to a thickness of about 200 to 1000 mW.

According to the present invention, a polysilicon film is embedded at the edge of the STI device isolation film and then oxidized to form an STI device separation film without grooves. Subsequently, the junction region is raised from the substrate by a predetermined height to prevent the metal wiring from extending into the device isolation film while eliminating contact between the metal wiring and the semiconductor substrate.

As a result, leakage current is greatly reduced at the interface between the junction region and the device isolation film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2E are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the present invention.

First, referring to FIG. 2A, a shallow trench t is formed in a device isolation scheduled region of the semiconductor substrate 50 to a predetermined depth. The shallow trench T is formed by the following process. First, a pad oxide film (not shown) and a silicon nitride film (not shown) are sequentially deposited on the semiconductor substrate 50. A resist pattern (not shown) is formed to expose the silicon nitride film in the device isolation region, and then the silicon nitride film and the pad oxide film are removed using the resist pattern as a mask. Next, the resist pattern is also removed by a known method. Using the remaining silicon nitride film as a mask, the exposed semiconductor substrate 50 is etched to a predetermined depth to form a shallow trench T, and then the silicon nitride film and the pad oxide film are removed. Thereafter, the surface of the substrate 50 is cleaned. Then, an insulating film, for example, a high density plasma insulating film is deposited so that the shallow trench T is sufficiently buried on the semiconductor substrate 50 on which the shallow trench T is formed, and then embedded in the shallow trench T. By etching, the STI device isolation layer 52 is formed. Here, the STI device isolation layer 52 protrudes from the surface of the semiconductor substrate 50 by a predetermined height. Thereafter, the surface of the semiconductor substrate 50 is cleaned. At this time, in the etching process of embedding the high density plasma insulating film in the shallow trench T and the substrate cleaning process, the edge portion of the STI device isolation film 52 is etched to generate the groove G.

Thereafter, the buffer insulating film 54 and the polysilicon film 56 are sequentially deposited on the semiconductor substrate 50. Here, the buffer insulating film 54 is a thin thermal oxide film, and is formed to a thickness of about several tens to about 100 GPa. The polysilicon film 56 is deposited to a thickness such that the grooving G is sufficiently buried, for example, 100 to 500 mm thick. Here, the polysilicon film 56 may be a polysilicon film containing no impurities or a polysilicon film containing impurities.

As shown in FIG. 2B, the polysilicon film 56 is etched back until the buffer insulating film 54 is exposed, and is embedded in the groove G. As shown in FIG. Thereafter, the remaining buffer insulating film 54 is removed by a wet etching method.

Next, referring to FIG. 2C, the polysilicon film 56 embedded in the grooving G is oxidized. As a result, the polysilicon film 56 embedded in the groove G becomes a silicon oxide film, and an element isolation film 52 without the groove G is formed. Thereafter, the native oxide film (not shown) or the like on the surface of the substrate 50 that is incidentally generated during the oxidation process of the polysilicon film 56 is removed by washing.

Then, the gate insulating film 58 and the conductive layer are sequentially stacked on the semiconductor substrate 50. In this case, a doped polysilicon film, a transition metal film, a transition metal silicide film, a doped polysilicon film and a transition metal film, or a doped polysilicon film and a transition metal silicide film may be selectively used as the conductive layer. . Thereafter, the conductive layer is patterned to form the gate electrode 60. Subsequently, spacers 62 are formed on both sidewalls of the gate electrode 60 by a known anisotropic etching method.

Thereafter, as shown in FIG. 2D, the semiconductor substrate 50 on both sides of the gate electrode 60, that is, a predetermined region of the junction region, is grown by a predetermined height by selective epitaxial growth. In this case, the semiconductor substrate 50 is grown to be lower than the height of the STI device isolation layer 52 and lower than the height of the gate electrode 60, preferably about 200 to 1000 kV. Here, reference numeral 64 denotes an epitaxial growth layer.

Then, as shown in FIG. 2E, the epitaxial growth layer 64 is ion implanted with impurities of the opposite type to the substrate and then activated to form the junction region 65. Here, the junction region 65 includes the epitaxial growth layer 64 and up to a predetermined portion of the semiconductor substrate 50 thereunder. Thereafter, an etch stopper 66 is deposited over the semiconductor substrate output. At this time, as the etch stopper 66, a silicon nitride film or a silicon nitride oxide film is used as in the prior art. Next, an interlayer insulating film 68 is deposited on the etch stopper 66. In this case, a silicon oxide film including a planarization film may be used as the interlayer insulating film 68.

Thereafter, the interlayer insulating film 68 and the etch stopper 66 are etched to expose the upper surface of the gate electrode 60 and the junction region 65 to form a contact hole H. When the contact hole H is formed in the non-overlap contact method, since the groove G is removed, the contact hole H does not extend into the STI device isolation layer 52. In addition, even when the edge portion of the STI device isolation layer 52 is partially etched during the etching stopper 66, the junction region 65 may be formed not only on the selective epitaxial layer 64 but also on the region of the semiconductor substrate 50 below. Since it is formed over, the area of the pure semiconductor substrate 50 is not exposed by the contact hole H. Thereafter, the metal wiring 70 is formed to contact the exposed gate electrode 60 and the junction region 65. As a result, the metal wiring 70 is in contact with each of the junction region 65 and the gate electrode 60, so that no leakage current is generated.

As described in detail above, according to the present invention, a polysilicon film is embedded at the edge of the STI device isolation film, and then oxidized to form an STI device isolation film without grooves. Subsequently, the junction region is raised from the substrate by a predetermined height to prevent the metal wiring from extending into the device isolation film while eliminating contact between the metal wiring and the semiconductor substrate.

As a result, leakage current is greatly reduced at the interface between the junction region and the device isolation film.

In addition, it can variously change and implement in the range which does not deviate from the summary of this invention.

Claims (10)

Forming a device isolation film having grooves at an edge in a predetermined portion on the semiconductor substrate; Embedding an insulator in the grooving of the device isolation film; Forming a gate electrode on the semiconductor substrate; Growing semiconductor substrates on both sides of the gate electrode by a predetermined height; And And implanting impurities into the grown semiconductor substrate to form a junction region. The method of claim 1, wherein embedding an insulator in the grooving comprises: Depositing a buffer insulating film on the semiconductor substrate; Depositing a polysilicon layer on the buffer insulating layer to a thickness such that the groove is buried; Anisotropically etching the polysilicon film to expose a buffer insulating film; Removing the buffer insulating film remaining on the substrate surface; And oxidizing the polysilicon film embedded in the grooving. 2. The method of claim 1, wherein the semiconductor substrates on both sides of the gate electrode are grown to a thickness higher than the height from the substrate to the device isolation layer and lower than the height of the gate electrode. Forming a device isolation film having grooves at an edge in a predetermined portion on the semiconductor substrate; Embedding a polysilicon film in the grooving of the device isolation film; Oxidizing the polysilicon film embedded in the grooving; Forming a gate electrode on the semiconductor substrate; Growing semiconductor substrates on both sides of the gate electrode by a predetermined height; And And implanting impurities into the grown semiconductor substrate to form a junction region. The method of claim 4, wherein the embedding of the polysilicon film in the grooving, Depositing a buffer insulating film on the semiconductor substrate; Depositing a polysilicon layer on the buffer insulating layer to a thickness such that the groove is buried; Anisotropically etching the polysilicon film to expose a buffer insulating film; And removing the buffer insulating film remaining on the surface of the substrate. 6. The method of claim 5, wherein the polysilicon film is deposited to a thickness of 100 to 500 kHz. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrates on both sides of the gate electrode are grown by a selective epitaxial growth method. 8. The method of claim 7, wherein the semiconductor substrates on both sides of the gate electrode are grown to a thickness higher than the height from the substrate to the device isolation layer and lower than the height of the gate electrode. The method of claim 8, wherein the semiconductor substrates on both sides of the gate electrode are grown by a thickness of about 200 to about 1000 microns. 5. The method of claim 4, further comprising: forming an etch stopper on top of the semiconductor substrate output after forming the junction region; Forming an interlayer insulating film on the etch stopper; Etching the interlayer insulating film and the etch stopper to expose the gate electrode and the junction region to form a contact hole; And forming a metal wiring in a contact hole to contact the exposed gate electrode and the junction region.