KR20020050514A - method for forming plug semiconductor device - Google Patents
method for forming plug semiconductor device Download PDFInfo
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- KR20020050514A KR20020050514A KR1020000079672A KR20000079672A KR20020050514A KR 20020050514 A KR20020050514 A KR 20020050514A KR 1020000079672 A KR1020000079672 A KR 1020000079672A KR 20000079672 A KR20000079672 A KR 20000079672A KR 20020050514 A KR20020050514 A KR 20020050514A
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- insulating film
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- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000000873 masking effect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 11
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 폴리 실리콘을 이용한 반도체 소자의 플러그(plug) 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a plug of a semiconductor device using polysilicon.
차세대 고집적 소자 형성시 중요한 기술 중의 하나는 0.2㎛이하의 홀을 형성하는 것이다.One of the important technologies in forming next-generation highly integrated devices is to form holes of 0.2 μm or less.
현재 사용되고 있는 포토 장비로는 재현성이 우수하지 않고, 설계상의 오버레이 마진(overlay margin)을 만족하기가 어렵다.Photo equipment currently in use is not excellent in reproducibility, it is difficult to meet the overlay margin (design overlay margin).
이를 극복하기 위해 사용되는 방법 중의 하나가 셀프 얼라인 콘택(SAC : Self Align Contact) 공정이다.One method used to overcome this is a Self Align Contact (SAC) process.
상기 SAC 공정은 실리콘 질화막과 실리콘 산화막과의 식각 선택비가 크다는 점을 이용하여 실리콘 질화막 베리어(barrier)가 있는 셀 콘택 공정에 적용하므로써, 오버레이 마진을 확보할 수 있고, 경사진 프로파일을 갖도록 식각하는 것에 의해 상부의 CD(Critical Dimension)을 0.2㎛이상으로 가져갈 수가 있다.The SAC process is applied to a cell contact process with a silicon nitride barrier using a large etching selectivity between the silicon nitride film and the silicon oxide film, thereby securing an overlay margin and etching to have an inclined profile. By this, the upper CD (Critical Dimension) can be taken to 0.2 µm or more.
그러나 상기 SAC 공정 역시, 0.15㎛이하로 홀 사이즈가 감소하게 되면 재현성이 떨어지게 되어 현재의 포토 장비로는 정확하게 홀을 디파인(define)할 수가 없다.However, in the SAC process, when the hole size is reduced to 0.15 μm or less, reproducibility is deteriorated, and current photo equipment cannot accurately define a hole.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 플러그 형성방법을 설명하면 다음과 같다.Hereinafter, a plug forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 반도체 소자의 플러그 형성방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a plug of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체 기판(11)을 필드 영역과 활성 영역으로 정의한 후, 상기 필드 영역에 필드 산화막(12)을 형성한다.As shown in FIG. 1A, after the semiconductor substrate 11 is defined as a field region and an active region, a field oxide film 12 is formed in the field region.
이때 상기 필드 산화막(12)은 국부 산화(LOCOS) 공정으로 형성하거나STI(Shallow Trench Isolation) 공정으로 형성하는 것이 가능한 데, 종래 기술에서는 STI를 이용하여 필드 산화막(12)을 형성하였다.At this time, the field oxide film 12 may be formed by a local oxidation (LOCOS) process or by a shallow trench isolation (STI) process. In the related art, the field oxide film 12 is formed using STI.
이어, 상기 필드 산화막(12)을 포함한 반도체 기판(11)의 전면에 게이트 절연막용 제 1 절연막(13)을 형성하고, 상기 제 1 절연막(13)상에 게이트 전극용 제 1 폴리 실리콘막(14)을 형성한다.Subsequently, a first insulating film 13 for a gate insulating film is formed on the entire surface of the semiconductor substrate 11 including the field oxide film 12, and a first polysilicon film 14 for a gate electrode is formed on the first insulating film 13. ).
이어, 상기 제 1 폴리 실리콘막(14)상에 게이트 캡 절연막용 제 2 절연막(15)을 형성한다. 이때 상기 제 2 절연막(15)의 물질은 실리콘 질화막이다.Subsequently, a second insulating film 15 for a gate cap insulating film is formed on the first polysilicon film 14. At this time, the material of the second insulating film 15 is a silicon nitride film.
이어, 상기 제 2 절연막(15)상에 감광막(도시되지 않음)을 도포한 후, 노광 및 현상 공정으로 감광막을 패터닝하여 게이트 라인이 형성될 영역을 정의한다.Subsequently, after the photoresist (not shown) is coated on the second insulating layer 15, the photoresist is patterned by an exposure and development process to define a region where a gate line is to be formed.
도 1b에 도시한 바와 같이, 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 제 2 절연막(15), 제 1 폴리 실리콘막(14), 제 1 절연막(13)을 선택적으로 제거하여 상기 필드 산화막(12) 및 반도체 기판(11)상에 선택적으로 형성되는 복수개의 게이트 전극(14a) 및 캡 절연막(15a)을 형성한다.As shown in FIG. 1B, the field oxide film is selectively removed by selectively removing the second insulating film 15, the first polysilicon film 14, and the first insulating film 13 by an etching process using the patterned photosensitive film as a mask. A plurality of gate electrodes 14a and a cap insulating film 15a, which are selectively formed on the 12 and the semiconductor substrate 11, are formed.
도 1c에 도시한 바와 같이, 상기 게이트 전극(14a)을 포함한 반도체 기판(11)의 전면에 제 3 절연막을 형성하고, 상기 제 3 절연막을 에치백하여 상기 게이트 전극(14a) 및 캡 절연막(15a)의 양측면에 제 3 절연막 측벽(16)을 형성한다.As shown in FIG. 1C, a third insulating film is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 14a, and the third insulating film is etched back to form the gate electrode 14a and the cap insulating film 15a. The third insulating film sidewall 16 is formed on both sides of the substrate.
도 1d에 도시한 바와 같이, 상기 게이트 전극(14a)을 포함한 반도체 기판(11)의 전면에 제 2 폴리 실리콘막(17)을 형성한 후, 상기 캡 절연막(15a)의 상부 표면을 앤드 포인트(end point)로 CMP(Chemical Mechanical Polishing) 공정을 실시하여 상기 제 2 폴리 실리콘막(17)을 평탄화한다.As shown in FIG. 1D, after the second polysilicon film 17 is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 14a, the upper surface of the cap insulating film 15a is formed at the end point (the end point). The second polysilicon layer 17 is planarized by performing a chemical mechanical polishing (CMP) process at an end point.
도 1e에 도시한 바와 같이, 상기 제 2 폴리 실리콘막(17)상에 감광막(18)을 도포한 후, 노광 및 현상공정을 이용하여 상기 활성 영역상에만 남도록 상기 감광막(18)을 패터닝한다. 즉, 셀 플러그가 형성되지 않을 부분의 제 2 폴리 실리콘막(17)을 제거하기 위하여 감광막(18)을 마스크로 이용한다.As shown in FIG. 1E, after the photoresist film 18 is applied onto the second polysilicon film 17, the photoresist film 18 is patterned so as to remain only on the active region using an exposure and development process. That is, the photosensitive film 18 is used as a mask to remove the second polysilicon film 17 in the portion where the cell plug is not to be formed.
이어, 상기 패터닝된 감광막(18)을 마스크로 이용하여 고밀도 플라즈마(High Density Plasma : HDP) 식각 장비를 이용하여 상기 제 2 폴리 실리콘막(17)을 식각하여 활성 영역에만 존재하는 폴리 실리콘 플러그(17a)를 형성한다.Subsequently, the second polysilicon layer 17 is etched using a high density plasma (HDP) etching apparatus using the patterned photoresist layer 18 as a mask, and the polysilicon plug 17a existing only in an active region is used. ).
여기서 미설명한 19는 상기 제 2 폴리 실리콘막(17)을 HDP 식각장비에 의해 식각할 때 필드 영역에 잔류하는 제 2 폴리 실리콘막(17)의 잔류물이다.19, which is not described herein, is a residue of the second polysilicon film 17 remaining in the field region when the second polysilicon film 17 is etched by the HDP etching equipment.
이후 공정은 도면에 도시되지 않았지만 감광막(18)을 제거하고, 상기 폴리 실리콘 플러그(17a)를 형성한 후에 제 1 층간 절연막을 형성한 후 비트 라인 콘택을 형성하고, 텅스텐(tungsten)을 형성하여 비트 라인을 형성한 후 포함한 전면에 제 2 층간 절연막을 형성하고, 상기 제 2 층간 절연막에 콘택홀을 형성한 후에 통상적인 캐패시터를 형성한다.Although not shown in the drawings, the photoresist film 18 is removed, the polysilicon plug 17a is formed, a first interlayer insulating film is formed, a bit line contact is formed, and tungsten is formed to form a bit. After forming the lines, a second interlayer insulating film is formed on the entire surface including the lines, and after forming contact holes in the second interlayer insulating film, a conventional capacitor is formed.
그러나 상기와 같은 종래의 반도체 소자의 플러그 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the plug forming method of the conventional semiconductor device as described above has the following problems.
즉, HDP 식각 장비만을 이용하여 폴리 실리콘막을 식각함으로서 폴리 실리콘막의 프로파일로 인해 공정 및 디자인(design)상에 마진을 감소시키며, 필드 영역에 폴리 실리콘막의 잔류물(residue)이 존재하여 소자의 신뢰성을 저하시킨다.In other words, by etching the polysilicon film using only HDP etching equipment, the profile of the polysilicon film reduces the margin in the process and design, and the residue of the polysilicon film exists in the field region to improve the reliability of the device. Lowers.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 공정 및 디자인상에 마진을 향상시킴과 동시에 폴리 실리콘막의 잔류물 발생을 방지하여 소자의 신뢰성을 향상시키도록 한 반도체 소자의 플러그 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The method for forming a plug of a semiconductor device improves the reliability of the device by improving the margins in the process and design, and at the same time preventing the residue of the polysilicon film. The purpose is to provide.
도 1a 내지 도 1e는 종래의 반도체 소자의 플러그 형성방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method of forming a plug of a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 플러그 형성방법을 나타낸 공정단면도2A through 2F are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 필드 산화막21 semiconductor substrate 22 field oxide film
23 : 제 1 절연막 24 : 제 1 폴리 실리콘막23: first insulating film 24: first polysilicon film
25 : 제 2 절연막 26 : 제 3 절연막 측벽25: second insulating film 26: third insulating film sidewall
27 : 제 2 폴리 실리콘막 28 : 감광막27: second polysilicon film 28: photosensitive film
29 : 제 2 폴리 실리콘막의 잔류물29: residue of the second polysilicon film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 플러그 형성방법은 필드 영역과 활성 영역으로 정의된 반도체 기판의 필드 영역에 필드 산화막을 형성하는 단계와, 상기 반도체 기판상에 제 1 절연막, 제 1 폴리 실리콘막, 제 2 절연막을 차례로 적층하여 형성하는 단계와, 상기 제 2 절연막, 제 1 폴리 실리콘막, 제 1 절연막을 선택적으로 식각하여 복수개의 게이트 전극 및 캡 절연막을 형성하는 단계와, 상기 게이트 전극 및 캡 절연막의 양측면에 제 3 절연막 측벽을 형성하는 단계와, 상기 게이트 전극을 포함한 반도체 기판의 전면에 제 2 폴리 실리콘막을 형성한 후 상기 캡 절연막이 노출될 때까지 평탄화하는 단계와, 상기 반도체 기판의 활성 영역에 상응하는 제 2 폴리 실리콘막을 마스킹하고 HDP 식각 장비로 1차 식각하고, 계속해서 ECR 식각 장비로 제 2 폴리 실리콘막을 2차 식각하여 원하는 부분에만 폴리 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.The method of forming a plug of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a field oxide film in a field region of a semiconductor substrate defined as a field region and an active region, a first insulating film on the semiconductor substrate, Stacking and forming a first polysilicon film and a second insulating film, and selectively etching the second insulating film, the first polysilicon film, and the first insulating film to form a plurality of gate electrodes and a cap insulating film; Forming sidewalls of a third insulating film on both sides of the gate electrode and the cap insulating film, forming a second polysilicon film on an entire surface of the semiconductor substrate including the gate electrode, and then planarizing until the cap insulating film is exposed; Masking the second polysilicon film corresponding to the active region of the semiconductor substrate and first etching with HDP etching equipment, and then And etching the second polysilicon layer with the ECR etching equipment to form a poly plug only on a desired portion.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 플러그 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a plug of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 플러그 형성방법을 나타낸 공정단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)을 필드 영역과 활성 영역으로 정의한 후, 상기 필드 영역에 필드 산화막(22)을 형성한다.As shown in FIG. 2A, after the semiconductor substrate 21 is defined as a field region and an active region, a field oxide film 22 is formed in the field region.
이때 상기 필드 산화막(22)은 국부 산화(LOCOS) 공정으로 형성하거나 STI(Shallow Trench Isolation) 공정으로 형성하는 것이 가능한 데, 본 발명에서는 STI를 이용하여 필드 산화막(22)을 형성하였다.In this case, the field oxide layer 22 may be formed by a local oxidation (LOCOS) process or a shallow trench isolation (STI) process. In the present invention, the field oxide layer 22 is formed using STI.
이어, 상기 필드 산화막(22)을 포함한 반도체 기판(21)의 전면에 게이트 절연막용 제 1 절연막(23)을 형성하고, 상기 제 1 절연막(23)상에 게이트 전극용 제 1 폴리 실리콘막(24)을 형성한다.Subsequently, a first insulating film 23 for a gate insulating film is formed on the entire surface of the semiconductor substrate 21 including the field oxide film 22, and a first polysilicon film 24 for a gate electrode is formed on the first insulating film 23. ).
이어, 상기 제 1 폴리 실리콘막(24)상에 캡 절연막용 제 2 절연막(25)을 형성한다. 이때 상기 제 2 절연막(25)의 물질은 실리콘 질화막이다.Next, a second insulating film 25 for cap insulating film is formed on the first polysilicon film 24. At this time, the material of the second insulating film 25 is a silicon nitride film.
이어, 상기 제 2 절연막(25)상에 감광막(도시되지 않음)을 도포한 후, 노광 및 현상 공정으로 감광막을 패터닝하여 게이트 라인이 형성될 영역을 정의한다.Subsequently, after the photoresist (not shown) is coated on the second insulating layer 25, the photoresist is patterned by an exposure and development process to define a region where a gate line is to be formed.
도 2b에 도시한 바와 같이, 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 제 2 절연막(25), 제 1 폴리 실리콘막(24), 제 1 절연막(23)을 선택적으로 제거하여 상기 필드 산화막(22) 및 반도체 기판(21)상에 선택적으로 형성되는 복수개의 게이트 전극(24a) 및 캡 절연막(25a)을 형성한다.As shown in FIG. 2B, the field oxide film is selectively removed by selectively removing the second insulating film 25, the first polysilicon film 24, and the first insulating film 23 by an etching process using the patterned photosensitive film as a mask. A plurality of gate electrodes 24a and a cap insulating film 25a which are selectively formed on the 22 and the semiconductor substrate 21 are formed.
도 2c에 도시한 바와 같이, 상기 게이트 전극(24a)을 포함한 반도체 기판(21)의 전면에 제 3 절연막을 형성하고, 상기 제 3 절연막을 에치백하여 상기게이트 전극(24a) 및 캡 절연막(25a)의 양측면에 제 3 절연막 측벽(26)을 형성한다.As shown in FIG. 2C, a third insulating film is formed on the entire surface of the semiconductor substrate 21 including the gate electrode 24a, and the third insulating film is etched back to form the gate electrode 24a and the cap insulating film 25a. The third insulating film sidewall 26 is formed on both sides of the < RTI ID = 0.0 >
도 2d에 도시한 바와 같이, 상기 게이트 전극(24a)을 포함한 반도체 기판(21)의 전면에 제 2 폴리 실리콘막(27)을 형성한 후, 상기 캡 절연막(25a)의 상부 표면을 앤드 포인트(end point)로 CMP(Chemical Mechanical Polishing) 공정을 실시하여 상기 제 2 폴리 실리콘막(27)을 평탄화시킨다.As shown in FIG. 2D, after the second polysilicon film 27 is formed on the entire surface of the semiconductor substrate 21 including the gate electrode 24a, the upper surface of the cap insulating film 25a is formed at an end point (ie A chemical mechanical polishing (CMP) process is performed at the end point to planarize the second polysilicon layer 27.
도 2e에 도시한 바와 같이, 상기 제 2 폴리 실리콘막(27)상에 감광막(28)을 도포한 후, 노광 및 현상공정을 이용하여 상기 활성 영역상에만 남도록 상기 감광막(28)을 패터닝한다. 즉, 셀 플러그가 형성되지 않을 부분의 제 2 폴리 실리콘막(27)을 제거하기 위하여 감광막(28)을 마스크로 이용한다.As shown in FIG. 2E, after the photosensitive film 28 is applied onto the second polysilicon film 27, the photosensitive film 28 is patterned so as to remain only on the active region by using an exposure and development process. That is, the photosensitive film 28 is used as a mask to remove the second polysilicon film 27 in the portion where the cell plug is not to be formed.
이어, 상기 패터닝된 감광막(28)을 마스크로 이용하여 고밀도 플라즈마(High Density Plasma : HDP) 식각 장비에서 HBr과 Cl2가스에 He-O2가스를 더 첨가하여 상기 제 2 폴리 실리콘막(27)을 1차로 식각한다.Subsequently, the second polysilicon layer 27 may be further added by adding He-O 2 gas to HBr and Cl 2 gas in a high density plasma (HDP) etching apparatus using the patterned photoresist layer 28 as a mask. Etch first.
여기서 상기 HDP 식각 장비의 경우 파워를 20~200W, 압력을 2~20mTorr, HBr : Cl2의 비를 10:1 ~ 50:1로 하여 약 150sccm을 사용하며, He-O2가스는 10sccm을 사용한다.In the case of the HDP etching equipment, the power is 20 to 200 W, the pressure is 2 to 20 mTorr, and the ratio of HBr to Cl 2 is 10: 1 to 50: 1 to use about 150 sccm, and the He-O 2 gas is used at 10 sccm. do.
또한, 상기 HDP 식각 장비는 EPD(End Point Detection)을 사용하여 1차 식각한다.In addition, the HDP etching equipment is primarily etched using End Point Detection (EPD).
한편, 미설명한 29는 상기 제 2 폴리 실리콘막(27)을 HDP 식각장비에 의해식각할 때 필드 영역에 잔류하는 제 2 폴리 실리콘막(27)의 잔류물이다.Meanwhile, reference numeral 29 is a residue of the second polysilicon film 27 remaining in the field region when the second polysilicon film 27 is etched by the HDP etching equipment.
도 2f에 도시한 바와 같이, 상기 HDP 식각 장비를 이용하여 상기 제 2 폴리 실리콘막(27)을 1차로 식각한 후, ECR(Electron Cyclotron Resonance) 식각 장비에서 HBr과 O2가스를 사용하여 2차 식각하여 제 2 폴리 실리콘막(27)의 잔류물(29)을 제거하여 활성 영역에만 폴리 실리콘 플러그(27a)를 형성한다.As shown in FIG. 2F, the second polysilicon layer 27 is first etched by using the HDP etching equipment, and then, the second polysilicon film 27 is secondary by using HBr and O 2 gas in an ECR (Electron Cyclotron Resonance) etching equipment. By etching, the residue 29 of the second polysilicon layer 27 is removed to form the polysilicon plug 27a only in the active region.
한편, 상기 ECR 식각 장비의 경우 파워를 20~200W, 압력을 2~20mTorr, HBr : O2비를 10:1 ~ 100:1 예를 들면, HBr 가스는 120sccm와 O2가스는 10sccm를 사용하여 추가 식각을 진행한다.In the case of the ECR etching equipment, the power is 20 to 200 W, the pressure is 2 to 20 mTorr, and the HBr to O 2 ratio is 10: 1 to 100: 1. For example, 120 sccm of HBr gas and 10 sccm of O 2 gas are used. Proceed with additional etching.
이후 공정은 도면에 도시되지 않았지만 상기 감광막(28)을 제거하고, 상기 폴리 실리콘 플러그(27a)를 형성한 후에 제 1 층간 절연막을 형성한 후 비트 라인 콘택을 형성하고, 텅스텐(tungsten)을 형성하여 비트 라인을 형성한 후 포함한 전면에 제 2 층간 절연막을 형성하고, 상기 제 2 층간 절연막에 콘택홀을 형성한 후에 통상적인 캐패시터를 형성한다.Although not shown in the drawings, the photoresist layer 28 is removed, the polysilicon plug 27a is formed, a first interlayer insulating layer is formed, a bit line contact is formed, and tungsten is formed. After forming the bit line, a second interlayer insulating film is formed on the entire surface including the bit line, and after forming a contact hole in the second interlayer insulating film, a conventional capacitor is formed.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 플러그 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a plug of a semiconductor device according to the present invention has the following effects.
즉, 셀 플러그용 폴리 실리콘막을 HDP 식각 장비와 ECR 식각 장비를 이용하여 1,2차로 식각함으로서 폴리 실리콘막의 잔류물 생성을 방지하여 소자의 신뢰성을 향상시킬 수 있고, 공정 및 디자인 마진을 향상시킬 수 있다.That is, by etching the polysilicon film for cell plugs in the 1st and 2nd order using the HDP etching equipment and the ECR etching equipment, it is possible to prevent the formation of residues of the polysilicon film, thereby improving the reliability of the device, and improving the process and design margin. have.
Claims (6)
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175171A (en) * | 1991-12-20 | 1993-07-13 | Nippon Steel Corp | Dry etching method |
| US5336365A (en) * | 1992-02-27 | 1994-08-09 | Nippon Steel Semiconductor Corporation | Polysilicon etching method |
| JPH07201834A (en) * | 1993-12-29 | 1995-08-04 | Sony Corp | Dry etching method |
| JPH09148312A (en) * | 1995-11-29 | 1997-06-06 | Sony Corp | Method of pattern etching |
| JPH1167724A (en) * | 1997-08-08 | 1999-03-09 | Hitachi Ltd | Slective etching method for polycrystalline silicon film and manufacture of semiconductor device using the same |
| US6096657A (en) * | 1998-03-31 | 2000-08-01 | Imec Vzw | Method for forming a spacer |
-
2000
- 2000-12-21 KR KR1020000079672A patent/KR20020050514A/en not_active Application Discontinuation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175171A (en) * | 1991-12-20 | 1993-07-13 | Nippon Steel Corp | Dry etching method |
| US5336365A (en) * | 1992-02-27 | 1994-08-09 | Nippon Steel Semiconductor Corporation | Polysilicon etching method |
| JPH07201834A (en) * | 1993-12-29 | 1995-08-04 | Sony Corp | Dry etching method |
| JPH09148312A (en) * | 1995-11-29 | 1997-06-06 | Sony Corp | Method of pattern etching |
| JPH1167724A (en) * | 1997-08-08 | 1999-03-09 | Hitachi Ltd | Slective etching method for polycrystalline silicon film and manufacture of semiconductor device using the same |
| US6096657A (en) * | 1998-03-31 | 2000-08-01 | Imec Vzw | Method for forming a spacer |
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