KR20020047876A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to exactly generate a precharge enable signal and a write enable signal even though a size of a device changes. CONSTITUTION: An inverter(I3) and an inverter(I4) delay a precharge enable signal(S1) and generate a signal(S21). A NAND gate(NA2) performs a NAND operation of a signal(S3) and a column selecting signal(y1). A NOR gate(NOR) performs a NOR operation of an output signal of the inverter(I3) and an output signal of the NAND gate(NA2) to generate a signal(S41). The signal(S21) is generated in response to the precharge enable signal(S1). The signal(S41) is generated by performing a NAND operation of the write enable signal(S3) and the column selecting signal(y1) in response to the precharge enable signal(S1). A control signal generating circuit generates the precharge enable signal(S1) and a write enable signal(S3) in response to a clock signal and a write enable signal.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device capable of being designed in various sizes by a compiler according to a request of an orderer.

The compiled macro static semiconductor memory device is designed as a device of various sizes according to a request of an orderer by a program of a compiler.

However, in the conventional compiled macro static semiconductor memory device, when the size of the device changes, the line load capacitance of the precharge enable signal and the write enable signal line also changes. However, compilers design semiconductor memory devices without considering the effects of these line load capacitances.

Therefore, in the conventional compiled macro static semiconductor memory device, the timing of these control signals must be generated accurately, and the problem that the timing of generation of these control signals is not accurate because the load capacitance of these signal lines varies with the size of the device. there was.

It is an object of the present invention to provide a semiconductor memory device in which a precharge enable signal and a write enable signal can be accurately generated even if the size of the device changes.

The semiconductor memory device of the present invention for achieving the above object is a memory cell array having a plurality of memory cells connected between each of a plurality of word lines and a plurality of bit line pairs, each of a plurality of precharge control signals Precharging the plurality of bit line pairs in response to the plurality of bit lines, and selecting a plurality of precharges and columns for transferring data from a predetermined number of data line pairs to the plurality of bit line pairs in response to each of the plurality of write control signals. Gate means, and generate each of the plurality of precharge control signals in response to a precharge enable signal, and generate each of the plurality of write control signals in response to the precharge enable signal and the write enable signal. It characterized in that it comprises a plurality of control means for.

1 is a block diagram showing the structure of a conventional semiconductor memory device.

FIG. 2 is a circuit diagram of an embodiment of the memory cell shown in FIG.

Figure 3 is a circuit diagram of an embodiment of a conventional precharge & column select gate and control circuit.

4 is an operation timing diagram for explaining the operation of the control circuit shown in FIG.

Figure 5 is a circuit diagram of an embodiment of the precharge & column select gate and control circuit of the present invention.

FIG. 6 is an operation timing diagram for explaining the operation of the control circuit shown in FIG.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the semiconductor memory device of the present invention.

1 is a block diagram showing the structure of a conventional semiconductor memory device, which includes a memory cell array 10, a row address decoder 12, a column address decoder 14, a write driver 16, and a control signal generation circuit 18. As shown in FIG. , Control circuits 20-1, 20-2, ..., 20-m, and precharge & column select gates 22-1, 22-2, ..., 22-m. have.

The memory cell array 10 has word lines WL1, WL2, ..., WLn and bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BLm, BLmB), respectively. It is composed of a plurality of memory cells (MC) connected between.

The function of each of the blocks shown in FIG. 1 will be described below.

The memory cell array 10 responds to a signal applied from each of the word lines WL1, WL2, ..., WLn, and the bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BLm, BLmB)) to transfer data. The row address decoder 12 decodes the row address Xi to generate signals for selecting word lines WL1, WL2,..., WLn. The column address decoder 14 decodes the column address Yj to generate column selection signals y1, y2, ..., ym. The write driver 16 drives the data Din and transmits the data to the data line pair DL and DLB. The control signal generation circuit 18 inputs the clock signal CLK and the write enable signal WE to generate the precharge enable signal S1 and the write enable signal S3. Each of the control circuits 20-1, 20-2, ..., 20-m generates signals S21, S22, ..., S2m in response to the precharge enable signal S1, Signals S41, S42, ..., S4m are generated in response to each of the combination of the write enable signal WE and the column select signals y1, y2, ..., ym. Each of the precharge & column select gates 22-1, 22-2,..., 22-m is in response to each of the signals S21, S22,..., S2m. , BL1B), (BL2, BL2B), ..., (BLm, BLmB)) and pre-charge the data line pair DL, DLB in response to each of the signals S41, S42, ..., S4m. Data is transmitted to bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BLm, BLmB). The block diagram shown in Fig. 1 shows only the data write path, and the data read path exists separately.

FIG. 2 is a circuit diagram showing the configuration of the embodiment of the memory cell shown in FIG. 1, and is comprised of a latch LA composed of NMOS transistors N1 and N2 and inverters I1 and I2.

The memory cell MC shown in FIG. 2 represents a cell connected between the word line WL1 and the bit line pair BL1 and BL1B.

The operation of the circuit shown in Fig. 2 is as follows.

When the word line WL1 is selected, the NMOS transistors N1 and N2 are turned on to transfer data between the bit line pairs BL1 and BL1B and the latch LA. The latch LA inverts and latches data transmitted through the NMOS transistors N1 and N2.

FIG. 3 is a circuit diagram of an embodiment of the precharge & column select gate and control circuit shown in FIG. 1, with PMOS transistors P1, P2, P3, NMOS transistors N3, N4, inverters I3, I4, I5. ) And a NAND gate (NA).

The operation of the circuit shown in Fig. 3 is as follows.

The PMOS transistors P1, P2, and P3 are precharge and equalization circuits, which precharge and equalize the bit line pairs BL1 and BL1B in response to the signal " low " level S21. The NMOS transistors N3 and N4 transfer data of the data line pair DL and DLB to the bit line pair BL1 and BL1B in response to the signal “S” of the “high” level.

The inverters I3 and I4 delay the precharge enable signal S1 to generate the signal S21. The NAND gate NA1 and the inverter I5 multiply the write enable signal S3 and the column select signal y1 to generate a signal S41.

However, the write operation may be performed correctly only when the signal S41 maintains the “high” level within the “high” level section of the signal S21 generated at this time.

FIG. 4 is an operation timing diagram for describing the operation of the control circuit shown in FIG. 3. The operation of the circuit shown in FIG. 3 will be described below with reference to FIG. 4.

The control signal generation circuit 18 generates the precharge enable signal S1 and the write enable signal S3 in response to the clock signal CLK and the not shown write enable signal WE. The signal S21 is generated in response to the precharge enable signal S1, and the signal S41 is generated in response to the write enable signal S3.

That is, each of the signals S21 and S41 is generated by delaying the precharge enable signal S1 and the write enable signal S3 for a predetermined time, respectively.

In the conventional compiled macro semiconductor memory device, the line load capacitance of the signal lines 30 and 32 for transmitting the precharge enable signal S21 and the write enable signal S41 as the size of the device changes. Can vary. Therefore, the timing of the signals S21 and S41 is shifted so that a correct write operation cannot be performed.

In the timing diagram of FIG. 4, it is possible by the control signal generation circuit 18 to control the signals S1 and S3 between the period d1 and the period d6. However, the timing of generation of the signals S1 and S3 may deviate from the period d1 to the period d6 so that the line load capacitance of the signal lines 30 and 32 changes.

Therefore, in this case, the timings of the generation of the signals S21 and S41 are also shifted, that is, the signal S41 is not generated within the "high" level section of the signal S21, so that the correct write operation cannot be performed. have.

Fig. 5 is a circuit diagram of an embodiment of the precharge & column select gate and control circuit of the present invention, wherein the configuration of the precharge & column select gate 22-1 is the same as that of the precharge and column select gate shown in Fig. 3; The control circuit 20'-1 is composed of inverters I3 and I4, a NAND gate NA2, and a NOR gate NOR.

The function of the circuit shown in Fig. 5 is as follows.

Inverters I3 and I4 delay signal S1 to generate signal S21, and NAND gate NA2 nonlogically multiplies signal S3 with column select signal y1. The NOR gate NOR non-logically combines the output signal of the inverter I3 with the output signal of the NAND gate NA2 to generate a signal S41.

That is, the signal S21 is generated in response to the precharge enable signal S1, and the signal S41 is non-logically multiplied by the write enable signal S3 and the column select signal y1 in response to the signal S1. A signal is generated as the signal S41.

FIG. 6 is an operation timing diagram for describing the operation of the control circuit shown in FIG. 5. The operation of the circuit shown in FIG. 5 will be described below with reference to FIG. 6.

The control signal generation circuit 18 generates the precharge enable signal S1 and the write enable signal S3 in response to the clock signal CLK and the not shown write enable signal WE. However, at this time, the generated write enable signal S3 is enabled in response to the rising edge of the clock signal CLK.

When the signal S21 is generated in response to the precharge enable signal S1 and the signal S4 is at the "high" level of the precharge enable signal S1, the signal S3 is at the "high" level. When the signal S4 transitions to the "high" level, and the signal S1 transitions to the "low" level, the signal S4 transitions to the "low" level.

That is, signals S2 and S4 are generated in response to the precharge enable signal S1. At this time, if the size of the PMOS transistor (not shown) constituting the inverter I3 is increased and the size of the PMOS transistor (not shown) constituting the NOR gate (NOR) is reduced, the timing of periods d2 and d3 is achieved. On the other hand, if the size of the NMOS transistor (not shown) constituting the inverter I3 is reduced and the size of the NMOS transistor (not shown) constituting the NOR gate NOR is increased, the timing of the periods d5 and d6 is achieved. Will have

The timing may be adjusted by adjusting the sizes of the transistors of the gates constituting the control circuit 20'-1.

The control circuits of the present invention control signals S1 and S3 output from the control signal generation circuit when generating signals S21, S22, S2m, S41, S42, S4m. Rather than being generated independently in response to each of these signals, these signals are generated in association with the control signal S1, so that even if there is a change in the line load capacitance of the signal lines 30 and 32, it can be generated accurately.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Therefore, in the semiconductor memory device of the present invention, even when the load capacitance of the precharge and write enable signal lines changes, the precharge and write operations can be accurately performed.

Claims (3)

A memory cell array having a plurality of memory cells coupled between each of a plurality of word lines and a plurality of bit line pairs; Precharging the plurality of bit line pairs in response to each of the plurality of precharge control signals, and transmitting data from a predetermined number of data line pairs to the plurality of bit line pairs in response to each of the plurality of write control signals. A plurality of precharge and column select gate means for; And A plurality of controls for generating each of the plurality of precharge control signals in response to a precharge enable signal and for generating each of the plurality of write control signals in response to the precharge enable signal and the write enable signal And a means for providing a semiconductor memory device. The method of claim 1, wherein each of the plurality of control means A delay circuit for delaying the precharge enable signal and generating a corresponding precharge control signal; A non-logical gate for non-logically multiplying the write enable signal and a column select signal for selecting the corresponding bit line pair; And And a non-logical gate for non-logically combining the signal obtained by inverting the precharge enable signal and the output signal of the non-logical gate to generate the corresponding write control signal. The method of claim 1, wherein each of the plurality of control means And enabling the write control signal to be enabled within an enable time of the precharge control signal.