KR20020044269A - Electro luminescent display panel - Google Patents

Abstract

PURPOSE: An electro-luminescent display panel is provided to compensate for the difference of luminance between pixels and form a gray level by using a timing control method. CONSTITUTION: The first switching element(41) is controlled by a signal applied to a gate line. The first switching element(41) is used for switching a data signal. The second switching element(43) is connected serially with the first switching element(41). A capacitor(45) is connected with an output terminal of the second switching element(43) and a supply voltage terminal(Vdd) in order to charge data voltage received through the first and the second switching elements(41,43). The third switching element(47) is connected with an output terminal of the first switching element(41) and one terminal of the capacitor(45). A bypass portion(51) is used for intercepting a discharge voltage of the capacitor(45) according to an erase signal. The fourth switching element(53) is connected between the supply voltage terminal(Vdd) and an electro-luminescent element(49).

Description

Electroluminescent display panel

The present invention relates to a display device, and more particularly, to a liquid crystal display device.

Due to the rapid development of the information and communication field, the importance of the display industry that displays desired information is increasing day by day. Until now, CRT (cathod ray tube) among information display devices can display various colors and the brightness of the screen is excellent. Because of its advantages, it has enjoyed steady popularity. However, the desire for large, portable and high resolution displays is urgently needed to develop flat panel displays instead of CRTs, which are bulky and bulky. These flat panel displays have a wide range of applications from computer monitors to displays used in aircraft and spacecraft.

Currently produced or developed flat panel displays include liquid crystal display (LCD), electroluminescent display (ELD), field emission display (FED), plasma display panel (PDP), etc. have. To be an ideal flat panel display, light weight, high brightness, high efficiency, high resolution, high speed response characteristics, low driving voltage, low power consumption, low cost (cost) and color display characteristics are required.

Among these, electroluminescent displays (ELDs) have excellent characteristics such as wide viewing angles, high-speed response, and high contrast, and are emerging as next-generation flat panel displays because they are thin, light, and have good color.

The electroluminescent display is largely divided into an inorganic light emitting device and an organic light emitting device according to the material used, wherein the organic light emitting device is a pair of electrons and holes when the charge is injected into the organic thin film layer formed between the electron injection electrode and the hole injection electrode After accomplishing this, it is an element that emits light while extinguishing. An inorganic light emitting element is an element that emits electrons, which are accelerated by a high electric field, to strike and excite the light emitter, and the excited light emitter falls to a ground state.

Hereinafter, an electroluminescent display panel according to the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a unit pixel of an electroluminescent display panel according to the prior art, and FIG. 2 is a timing diagram of a gate signal and a data signal for explaining a driving method.

As shown in FIG. 1, a conventional unit pixel employs a 2-TR structure. That is, the first transistor 11 for selectively switching the data voltage by the gate signal and the second transistor 15 for switching the power supply voltage to the electroluminescent element 13 by the output terminal voltage of the first transistor 11. ) And a capacitor 17 connected between the output terminal of the first transistor 11 and the input terminal of the second transistor 15.

Here, the first transistor 11 and the second transistor 15 are P-type thin film transistors driven by a low voltage.

In the conventional EL display panel having such a structure, when the first transistor 11 is driven by the gate signal of the gate line Gn, the data voltage loaded on the data line Dn is transferred through the first transistor 11. When the gate signal is charged and the gate signal is cut, the voltage charged in the capacitor 17 is discharged, and a current is transmitted to the electroluminescent element 13 through the second transistor 15 to discharge the electroluminescent element 13. ) Will emit light.

In this case, the degree of light emission is determined by the data voltage, and the intensity of light emission varies according to the height of the data voltage.

However, the conventional EL display panel has the following problems.

Since unit pixels having the structure shown in FIG. 1 are formed in the entire area of the panel, characteristics of the second transistor change according to the position of the pixel, causing a luminance difference between the pixels, and there is a limit in implementing gray levels. have.

The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide an electroluminescent display panel that can compensate for the luminance difference between pixels and implement gray levels through time control.

1 is a configuration diagram of a unit pixel of an electroluminescent display panel according to the related art.

2 is a waveform diagram of a gate voltage and a data voltage for explaining a conventional driving method.

3 is a configuration diagram of an electroluminescent display panel of the present invention.

4 is a unit pixel configuration diagram of an electroluminescent display panel of the present invention.

5 is a timing diagram illustrating a method of driving an electroluminescent display panel of the present invention.

6 is a configuration diagram of a unit frame composed of a plurality of subfields according to the present invention.

FIG. 7 illustrates six subfields constituting one frame when assuming digital data is 6 bits.

FIG. 8 is a timing diagram of an electroluminescent display panel using FIG. 7.

9 is another configuration diagram of a unit pixel according to the electroluminescent display panel of the present invention.

Explanation of symbols for main parts of the drawings

31 pixel array portion 33 gate driving circuit portion

35 source driving circuit portion 37 erase driving circuit portion

41,43: first and second switching elements 47,53: third and fourth switching elements

51: bypass section

The electroluminescent display panel of the present invention for achieving the above object is a pixel array unit comprising a plurality of pixels having a plurality of gate lines and data lines arranged intersectingly arranged, and an electroluminescent element formed at each intersection, the gate A gate driving circuit portion for applying a gate driving signal to a wiring, a data driving circuit portion for applying a data signal to the data wiring, and an erasing driving circuit portion for applying an erase signal for adjusting the emission time of each electroluminescent element of the pixel array portion; It is configured to include.

Here, each of the pixels is connected in series to switch the first and second switching elements for switching the data voltage, a capacitor connected between the output terminal and the power supply voltage terminal of the second switching element and the charge of the data voltage, A bypass unit connected in parallel at both ends, a third switching element connected between an output terminal of the first switching element and a power supply voltage terminal, and a current corresponding to a current flowing through the third switching element as an electroluminescent element And a fourth switching element for outputting and an electroluminescent element emitting light for a predetermined time in correspondence with the current flowing through the fourth switching element.

Hereinafter, an electroluminescent display panel of the present invention will be described with reference to the accompanying drawings.

3 is a configuration diagram of the electroluminescent display panel of the present invention and FIG. 4 is a unit pixel configuration diagram of the electroluminescent display panel.

First, as shown in FIG. 3, the electroluminescent display panel of the present invention is largely composed of a pixel array unit 31, a gate driving circuit unit 33, a source driving circuit unit 35, and an erase driving circuit unit 37.

Here, in the pixel array unit 31, a plurality of gate lines and data lines are arranged to cross each other, and a pixel region is defined at each crossing portion. The gate driving circuit unit 33 sequentially applies a driving signal to the gate wiring in the pixel array unit 31, and the erase driving circuit unit 37 applies an erase signal to each pixel in the pixel array unit 31. The source driving circuit unit 35 applies a data signal to the data line.

The pixel array unit 31 is composed of a plurality of pixels, and the structure of each pixel is as shown in FIG. 4.

As shown in FIG. 4, the unit pixel of the electroluminescent display panel of the present invention is controlled by a signal applied to a gate wiring to switch a data signal, and a first switching element 41 and the first switching element 41. ) Is connected in series with the second switching element 43, one terminal is connected to the output terminal of the second switching element 43 and the other terminal is connected to the power supply voltage terminal (Vdd) to the first, second switching element ( A capacitor 45 for charging the data voltage transferred through the first and second terminals 41 and 43, and an output terminal of the first switching element 41 and the other terminal of the capacitor 45, and one terminal of the capacitor 45. The discharge voltage of the capacitor 45 is prevented from being transferred to the electroluminescent element 49 in accordance with the third switching element 47 controlled by the voltage induced by the and the erase signal applied from the erase driving circuit unit 37. Passing by It consists seubu 51, the power supply voltage terminal (Vdd) and the electroluminescent fourth switching element 53 is controlled by the connection between the device 49 to the voltage induced in the one terminal of the capacitor.

Here, the switching elements are composed of a P conductive transistor driven by a low voltage, the bypass unit 51 is connected in parallel with the capacitor 45 between one terminal and the other terminal of the capacitor 45 By performing the function of bypassing the discharge voltage of the capacitor 45 to the electroluminescent element 49 by the erase signal applied from the erase driving circuit unit 37, and constitutes a P-conductive transistor do.

When the unit pixel configured as described above applies an activation signal to the gate wiring, the data voltage is charged to the capacitor 45 through the first and second switching elements 41 and 43, and then the third switching element 47. The current corresponding to the current flowing through) is transferred to the electroluminescent element 49 through the fourth switching element 53 so that the electroluminescent element emits light for a predetermined time.

Subsequently, even when the gate signals for controlling the first and second switching elements 41 and 43 are cut, the electroluminescent element continues to emit light while the data voltage stored in the capacitor 45 is discharged. When the erase signal is output to the bypass unit 51 configured at both ends of the capacitor 45, the discharge voltage of the capacitor 45 is bypassed through the bypass unit 51 so that the electroluminescent element 49 is It will no longer emit light.

Referring to the driving method of the electroluminescent display panel having a unit pixel having such a structure as follows.

As mentioned above, the present invention configures the bypass unit 51 at both ends of the capacitor 45, and controls the bypass unit 51 by the erase signal of the erase driving circuit unit 37 to display the electroluminescent element ( It is characterized by adjusting the light emission time of 49).

That is, as can be seen from the timing diagram shown in FIG. 5, before the gate signal is activated, the erase driving circuit unit 37 outputs the erase signal to the bypass unit 51 to completely discharge the voltage charged in the capacitor. At this time, the electroluminescent device emits light from the time when the gate signal is activated. If it is assumed that the time from the time when the electroluminescent device starts to emit light until the next erase signal is output, t1 is adjusted. By this, the light emission time of the electroluminescent element can be adjusted.

Hereinafter, the method of adjusting t1 will be described in more detail.

As a method for adjusting t1, one frame is divided into n subfields, and pixels are turned on / off for each subfield.

Here, a method of dividing one frame into n subfields uses the number of bits of the input digital data, as shown in FIG. 6. If the digital data is 6 bits, the method is divided into six subfields. If the number of bits is 8 bits, it is divided into eight subfields. As a result, each bit constituting one frame becomes data of one subfield.

For reference, if the digital data is 6 bits, gray levels from 0 to 63 may be implemented. If the digital data is 8 bits, gray levels from 0 to 255 may be implemented.

FIG. 7 illustrates six subfields constituting one frame when the digital data to be input is 6 bits. The time for which data corresponding to each subfield is displayed is defined as T1 to T6, respectively. 8 is a timing diagram accordingly.

In FIG. 7 and FIG. 8, T1 is a time at which data corresponding to subfield 1 emits light, T2 is a time at which data corresponding to subfield 2 emits light, T3 is subfield 3, T4 is subfield 4, and T5 is Subfields 5 and T6 are time periods at which data corresponding to the subfield 6 emits light.

Therefore, the gray level can be adjusted by dividing the input digital data into a plurality of subfields and adjusting the time that each subfield emits light. In other words, the T1 to T6 are determined according to the gray level.

FIG. 9 illustrates another embodiment of unit pixels of an electroluminescent display panel.

As shown in FIG. 9, it can be seen that the position of the capacitor has been changed in comparison with FIG. 4. That is, in FIG. 4, the capacitor 45 is connected between the power supply voltage terminal Vdd and the output terminal of the second switching element 43. In FIG. 9, the output terminal of the ground voltage terminal Vss and the second switching element 43 is shown. Connected in between.

As described above, the electroluminescent display panel of the present invention has the following effects.

By adding the bypass portion at both ends of the capacitor to charge the data voltage to adjust the emission time of the electroluminescent device through the bypass portion, the gray level can be achieved by adjusting the time and the luminance between each pixel can be compensated have.

Claims (7)

A pixel array unit comprising a plurality of pixels including a plurality of gate lines and data lines intersected and an electroluminescent element formed at each intersection; A gate driving circuit unit applying a gate driving signal to the gate wiring; A data driver circuit unit applying a data signal to the data line; And an erase driver circuit unit configured to apply an erase signal for adjusting an emission time of each electroluminescent element of the pixel array unit. The method of claim 1, wherein each pixel is First and second switching elements connected in series to switch data voltages; A capacitor connected between an output terminal of the second switching element and a power supply voltage terminal to charge a data voltage; A bypass unit connected in parallel between both ends of the capacitor; A third switching element connected between an output terminal of the first switching element and a power supply voltage terminal; A fourth switching device for selectively outputting a current corresponding to the current flowing through the third switching device to an electroluminescent device; And an electroluminescent element emitting light for a predetermined time in correspondence with the current flowing through the fourth switching element. The electroluminescent display panel of claim 2, wherein the bypass unit is controlled by an erase signal output from the erase driver circuit unit. The electroluminescent display panel according to claim 2, wherein each switching element comprises a P-type thin film transistor. The EL display panel of claim 2, wherein the erase signal applied to the bypass unit has a time difference. 6. The EL display panel of claim 5, wherein the temporal difference of the erase signal is determined by data of each bit constituting a unit frame of digital data. The electroluminescent display panel of claim 2, wherein the capacitor is configured between an output terminal of the second switching element and a ground voltage terminal.