KR20020034437A - Data output buffer control circuit - Google Patents

Abstract

PURPOSE: A data output buffer control circuit is provided, which improves a yield by stabilizing an operation of the circuit by controlling a time(tAC) from when a data hold time(tOH) and a clock signal(clock) are applied until effective data are output at random. CONSTITUTION: A control signal generation unit generates a number of control signals by decoding an output signal of a number of fuse box parts having fuses. A data output control signal generation unit controls a timing by controlling a delay of the data output control signal generated from a clock by a number of clock signals from the control signal generation unit. And a data output enable signal generation unit controls a timing by controlling a delay of the data output enable signal generated from a clock by a number of control signals generated from the control signal generation unit. The control signal generation unit comprises the first and the second fuse box part(50,60) outputting a 'high' or 'low' level signal by a connection state of the fuse, and a decoding circuit part outputting control signals by decoding the output signals of the first and the second fuse box part.

Description

Data output buffer control circuit {DATA OUTPUT BUFFER CONTROL CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer control circuit of a semiconductor memory device, and in particular, adjusts the time t _AC from the time point at which the data hold time t _OH and the clock signal are applied until the valid data is output. The present invention relates to a data output buffer control circuit which stabilizes the operation of a circuit.

FIG. 1A is a schematic diagram of a conventional data output control circuit, in which a data output buffer is output from a memory core unit 10 and data from the memory core unit 10 by an output control signal oc. A data output control unit 20 for transmitting to the unit 30, and outputs the data (dout) from the data output control unit 20 to the input / output pad 32 by the data output enable signal (oe) The data output buffer section 30 is shown.

FIG. 1B is a circuit diagram of a conventional data output buffer control circuit shown in FIG. 1A.

As shown in the drawing, the read data data read from the conventional data output buffer memory core unit 10 is connected to the node through the transfer gates P1 and N1 when the data output control signal oc has a high state. Nd1). The signal of the node Nd1 is transmitted to the node Nd2 by the inverter INV2, and the potential signal of the node Nd2 is present until the next data is transferred by the memory cells INV4 and INV2. Will be maintained. The data of the node Nd2 is inverted by the inverter INV3 and output to the node Nd3.

The output signal dout of the data output control unit 20 output to the node Nd3 is input to the data output buffer unit 30. At this time, when the output enable signal oe is 'high' and the node Nd3 is 'high', the pull-up transistor P2 operates to 'high' data to the input / output pad I / O PAD. When the output enable signal oe is 'high' and the node Nd3 is 'low', the pull-down transistor N2 operates to 'low' the input / output pad I / O PAD. 'Print data. When the output enable signal oe is 'low', both the pull-up and pull-down transistors P2 and N2 are turned off regardless of the potential level of the node Nd3, and thus the input / output pads I / O. PAD) has a high impedance (Hi-Z) state.

FIG. 1C illustrates an operation timing of the control signal and output data shown in FIGS. 1A and 1B.

The data output control signal oc generates a pulse signal after a predetermined time after the data transitions, and the data output enable signal oe is generated after a predetermined time after the first data output control signal oc occurs. Enabled to high.

The data output control signal oc and the data output enable signal oe are signals for determining the column address access time t _AA for outputting the first data in the DRAM of the semiconductor memory device. In addition, from the output of the second data, the timing of the data control signal is adjusted to satisfy the data hold time t _OH and the time t _AC from the time point at which the clock signal is applied until the valid data is output. Try to output the data from the cell on time.

However, when the data output control signal oc or the data output enable signal oe operates fast or slow due to a change in a process, the data hold time t _OH and a clock signal are applied. The circuit does not operate reliably because it does not satisfy the time t _AC until valid data is output.

The data output control signal oc and the data output enable signal oe are also used in general data output buffers, but the timing is already determined before the manufacturing process. Therefore, it cannot be changed after the manufacturing process, and if necessary, when the timing of the data output control signal oc and the data output enable signal oe is corrected, the wafer is manufactured again through a modification of a metal layer. There was a problem that should be committed to.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a data hold time t even if a data output control signal oc or a data enable signal oe operates fast or slow due to a process change or the like. _It is to provide a data output buffer control circuit which improves the yield by stabilizing the operation of the circuit by arbitrarily adjusting the time (t _AC ) from the time point at which _OH ) and the clock signal (clock) is applied until the valid data is output.

In order to achieve the above object, the data output buffer control circuit of the present invention,

Control signal generating means for decoding the output signals of the plurality of fuse box portions having respective fuses to generate a plurality of control signals;

A data output control signal generating means for adjusting timing by adjusting a delay of a data output control signal generated from a clock by a plurality of control signals generated by the control signal generating means;

And a data output enable signal generating means for adjusting timing by adjusting a delay of the data output enable signal generated from the clock by a plurality of control signals generated by the control signal generating means.

In the data output buffer control circuit of the present invention, the control signal generating means includes first and second fuse box parts for outputting a signal having a 'high' or 'low' level according to a connection state of the fuse, and the first And a decoding circuit unit for outputting the first to fourth control signals decoded by inputting the output signal of the second fuse box unit.

1A is a conceptual diagram of a conventional data output

Figure 1b is a conventional data output buffer control circuit diagram

FIG. 1C is an operation timing diagram of FIG. 1B

2 is a data output control circuit diagram according to the present invention;

2A is a circuit diagram of a data output control signal generator according to the present invention;

2B is a data output enable signal generation circuit diagram according to the present invention;

FIG. 2C is a control signal generation circuit diagram shown in FIGS. 2A and 2B.

3 is an operation timing diagram of a data output control circuit according to the present invention;

Explanation of symbols on the main parts of the drawings

10: memory core unit 20: data output control unit

30: data output buffer section 50: first fuse box section

60: second fuse box portion

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2 is a data output control circuit diagram according to the present invention, FIG. 2A is a data output control signal generation circuit diagram of the present invention, FIG. 2B is a data output enable signal generation circuit diagram according to the present invention, and FIG. 2C is FIGS. 2A and FIG. It is a control signal generation circuit diagram shown in 2b.

First, the control signal generating circuit shown in FIG. 2C includes first and second fuse box parts 50 and 60 that output signals of a 'high' or 'low' level by a connection state of a fuse; A NAND gate NAND2 for inputting output signals of the first and second fuse box units 50 and 60 to output an output signal out, and an output signal Nd5 of the first fuse box unit 50. And a NAND gate NAND3 for inputting an inverted signal of the output signal Nd6 of the second fuse box unit 60 to output the first control signal conA, and an output of the first fuse box unit 50. A NAND gate NAND4 for inputting an inverted signal of the signal Nd5 and an output signal Nd6 of the second fuse box unit 60 to output a second control signal conB, and the first fuse box unit ( A NAND gate N for outputting a third control signal conC by inputting an inverted signal of the output signal Nd5 of 50 and an inverted signal of the output signal Nd6 of the second fuse box unit 60. AND5).

The first and second fuse box parts 50 and 60 may include a PMOS transistor P3 for supplying a power supply voltage Vdd to the node Nd4 by an initialization signal using a pulse lamp during power-up, and the The NMOS transistor N3 and the fuse f1 connected in series between the node Nd4 and the ground voltage Vss and switched by the initialization signal, and between the node Nd4 and the node Nd5. It is composed of a connected inverter INV6 and a PMOS transistor P4 which supplies a power supply voltage Vdd to the node Nd4 by the potential of the node Nd5.

When the fuse f1 is connected, the initialization signal has a high level, so that the output of the first fuse box part 50 is connected through the NMOS transistor N3 connected to the fuse f1. It receives the 'low' level input to the inverter INV6 and outputs a 'high' level.

When the fuse f1 is blown, the initialization signal int has a 'low' level, and thus a potential signal having a 'high' level is input to the inverter INV6 through the PMOS transistor P3. Therefore, the inverter INV6 outputs the 'low' level and the latching PMOS transistor P4 maintains the input level, so that the first fuse box part 50 outputs the 'low' level.

In normal operation, the fuse is blown even when the initialization signal (initial) is at the 'high' level and the NMOS transistor N3 is operated, so the input of the inverter INV6 through the latch PMOS transistor P4 is 'high'. Keep your level. Thus, the output of the fuse box portion 50 has a 'low' level.

In FIG. 2B, when the fuse in the first fuse box part 50 is called a first fuse f1 for convenience and the fuse in the second fuse box part 60 is called a second fuse f2, The signal output according to whether the first and second fuses are connected is shown in the following table.

First fuse (f1) Second fuse (f2) Output signal ('low' state) Connected Connected default Connected Broken conA Broken Connected conB Broken Broken conC

As shown in the above table, when both the first fuse f1 and the second fuse f2 are not blown, only the output signal default is at the 'low' level, and all remaining signals output the 'high' level.

The four signals generated here are respectively input to the data output control signal oc generating circuit shown in Fig. 2A and used to adjust the timing at which the data output control signal oc is output from the clock.

Referring to FIG. 2A, the data output control signal oc generating circuit according to the present invention includes two inverters INV9 and INV10 connected in series between a terminal for inputting a clock signal and a node Nd7. Inverter INV11 which inverts the signal of node Nd7 by one control signal conA and outputs it to node Nd8, and inverts the signal of node Nd8 and outputs it as data output control signal oc. Is composed of an inverter INV12. In addition, two inverters INV13 and INV14 connected in series between the node Nd7 and the node Nd9 and the node Nd8 are inverted by inverting the signal of the node Nd9 by the second control signal conB. Signal from the node Nd10 by the inverter INV15 to be output to the node, two inverters INV16 and INV17 connected in series between the node Nd9 and the node Nd10, and the control signal default. Inverter INV18 inverted and outputted to node Nd8, two inverters INV19 and INV20 connected in series between node Nd10 and node Nd11, and the third control signal conC. An inverter INV15 for inverting the signal of the node Nd11 and outputting the inverted signal to the node Nd8.

Since only one of the four control signals generated in the circuit of FIG. 2B has a 'low' level, the data output control signal oc operates accordingly after two to eight inverters are delayed. However, the number of inverters or delay elements used here can be changed as much as possible. By changing the operation timing of the data output control signal oc as described above, the data hold time t _OH and the time t _AC from the time point at which the clock signal is applied to the valid data are output at the time of data output. It was adjusted to allow normal operation.

2B is a circuit diagram of a data output enable signal oe generation according to the present invention.

As shown, the data output enable signal (oe) generation circuit of the present invention includes a NAND gate (NAND6) for inputting a read command and a clock, an output terminal of the NAND gate (NAND6), and a node (Nd12). Two inverters INV22 and INV23 connected in series between each other and the node Nd12 by a lead enable bar signal REB generated by a burst length or a burst stop or the like. A flip-flop composed of NAND gates NAND7 and NAND8 latching a signal, an inverter INV24 for inverting the output signals of the flip-flop NAND7 and NAND8 and outputting it to the node Nd13, and the first control signal It consists of an inverter INV25 which inverts the signal of the node Nd13 by conA and outputs it as a data output enable signal oe. In addition, two inverters INV26 and INV27 connected in series between the node Nd13 and the node Nd14 and the terminal outputting the data output enable signal oe by the second control signal conB. And an inverter INV28 that inverts and outputs the signal of the node Nd14. In addition, two inverters INV29 and INV30 connected in series between the node Nd14 and the node Nd15 and the terminal outputting the data output enable signal oe by the third control signal conC. Inverter INV31 for inverting and outputting the signal of node Nd15. In addition, two inverters INV32 and INV33 connected in series between the node Nd15 and the node Nd16 and a terminal for outputting the data output enable signal oe by a fourth control signal conD are provided. It consists of an inverter INV34 which inverts and outputs the signal of the node Nd16.

The data output enable signal (oe) generating circuit is provided with one more fuse box unit shown in FIG. 2C to input four control signals conA to conD to adjust the timing of the data output enable signal oe. . This allows variation in the column address access time t _AA at the first data output. In addition, the timing with the data can be adjusted to prevent the invalid data from being output at the first data output.

As described above, according to the data output buffer control circuit of the present invention, even if the data output control signal oc or the data enable signal oe operates fast or slow due to a process change or the like, the data hold time t _OH And the time t _AC from the time point at which the clock signal is applied to the valid data to be output can be arbitrarily adjusted, so that the operation of the circuit can be stabilized and the yield can be improved.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (2)

In a semiconductor memory device, Control signal generating means for decoding the output signals of the plurality of fuse box portions having respective fuses to generate a plurality of control signals; A data output control signal generating means for adjusting timing by adjusting a delay of a data output control signal generated from a clock by a plurality of control signals generated by the control signal generating means; And a data output enable signal generating means for adjusting timing by adjusting a delay of a data output enable signal generated from a clock by a plurality of control signals generated by the control signal generating means. Buffer control circuit. The method of claim 1, wherein the control signal generating means, First and second fuse box parts configured to output signals of a 'high' or 'low' level by a connection state of the fuse; And a decoding circuit unit for outputting first to fourth control signals decoded by inputting output signals of the first and second fuse box units.