KR20020016337A - Method of forming a highly reliable and highly integrated ferroelectric capacitor - Google Patents

Abstract

PURPOSE: A method for fabricating a reliable high-integrated ferroelectric capacitor is provided to prevent a characteristic of a ferroelectric material layer from being deteriorated, by making a reaction barrier layer and a conductive pad completely surround the capacitor. CONSTITUTION: A contact plug(118) penetrates a predetermined portion of an insulation layer formed on a semiconductor substrate(100) having an active region, in contact with the active region. The ferroelectric capacitor is formed on the contact plug and on the insulation layer formed at both sides of the contact plug. The reaction barrier layer(132) is formed on the insulation layer and the capacitor. The reaction barrier layer is patterned to expose a part of an upper electrode. A conductive hydrogen barrier layer is formed on the reaction barrier layer and the exposed upper electrode. The reaction barrier layer and the conductive hydrogen barrier layer are patterned to surround at least the capacitor so that a hydrogen barrier layer conductive pad(136) in contact with the upper electrode is formed.

Description

METHOOD OF FORMING A HIGHLY RELIABLE AND HIGHLY INTEGRATED FERROELECTRIC CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a highly reliable ferroelectric capacitor and a method of manufacturing the same.

In modern data processing systems, random access must be available for quick access to information stored in memory cells. In the semiconductor industry, memory devices require fast operating speeds. Accordingly, research into ferroelectric random access memory (FRAM) has been actively conducted. As is well known, such FRAMs have non-volatile properties, which are possible because of having a ferroelectric material film between the capacitor electrodes. These ferroelectric films have two different stable polarization states, which are represented by the well-known characteristic hysteresis loop in the graph representing the polarization state with respect to the applied voltage.

As described above, FRAM can be written at a relatively low voltage (about 5V or less), nonvolatile characteristics such as flash memory (18-22V for flash memory), and excellent operating speed. (Several nsec, about 40 nsec or less) (several msec for flash memory), excellent immunity (about 10 ¹² or more) (about 10 ⁵ -10 ^{8 for} flash memory), and low power consumption (standby current of about 1 microarm) Less than a pair)

In FRAM, a pulse is applied to an upper electrode to read / write data, and a plate line through a via hole is required. However, due to the high integration, as the size of the via hole becomes smaller and the thickness of the insulating layer formed on the capacitor becomes thicker, the size of the upper electrode decreases, the via hole size decreases, and the via hole photo margin decreases, making the process difficult. .

In addition, the characteristics of the ferroelectric material are deteriorated due to the polarization (charging) by the cation due to dry etching in the capacitor electrode formation or contact hole / via hole formation process. Such deterioration of the characteristics of the ferroelectric material accumulates as the integration process for fabricating highly integrated devices proceeds. Therefore, it is necessary to recover the deterioration of characteristics. To this end, a heat treatment process is performed, which is performed while the capacitor upper electrode is exposed. That is, after forming the via hole exposing the upper electrode by patterning the interlayer insulating film, heat treatment is performed to prevent deterioration of characteristics due to etching. However, as is known, the ferroelectric material is an oxide having a structure in which a metal element and oxygen are bonded. Therefore, hydrogen generated in the interlayer insulating film process penetrates into the ferroelectric material film through the ferroelectric capacitor exposed by the via hole and combines with oxygen in the ferroelectric material film. Accordingly, the ferroelectric material film is deficient in oxygen and deteriorates the characteristics of the above-described ferroelectric material. Meanwhile, in order to prevent this, a reaction prevention film is formed, but even in this case, since the via hole must expose the upper electrode through the reaction prevention film as well as the interlayer insulating film, the material such as hydrogen still remains through the exposed upper electrode. Can penetrate

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a reliable hydrogen barrier film to form a reliable highly integrated ferroelectric capacitor.

Another object of the present invention is to provide a method of forming a ferroelectric capacitor capable of improving a photo alignment margin of a via hole.

1 to 11 are diagrams schematically showing a cross section of a semiconductor substrate according to a process sequence of a method of forming a ferroelectric capacitor according to a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 102 device isolation region

104, 106: Gate patterns 108a, 108b: Source / drain

110, 116, 138: interlayer insulating film 114: bit line

118: contact plug 120,122,126,126,128,130: capacitor

132: reaction prevention film 136: conductive pad

140: via hole 142: metal wiring

A feature of the present invention is to form a reaction prevention film after capacitor formation. After that, a part of the upper electrode is exposed, and heat treatment is performed to reinforce the anti-reaction film properties and to heal the damage caused by the formation of the via hole. Then, an oxidation-heat resistant conductive film is formed as a hydrogen barrier film to prevent hydrogen from penetrating into the subsequent interlayer insulating film. At this time, by forming the reaction prevention film and the hydrogen prevention film, a conductive pad in electrical contact with the upper electrode of the capacitor is formed. Due to the conductive pad, it is possible to prevent diffusion of hydrogen in a subsequent interlayer insulating film process and to improve photo margin of via hole formation for forming metal wirings.

More specifically, the method of forming a ferroelectric capacitor according to a preferred process configuration of the present invention for achieving the object of the present invention, the contact with the active region through a predetermined portion of the insulating film formed on a semiconductor substrate having an active region Forming a contact plug, forming a ferroelectric capacitor on the contact plug and the one insulating film on both sides thereof, forming a reaction prevention film on the one insulating film and the capacitor, and patterning the reaction prevention film. Exposing a portion of the upper electrode, forming a conductive hydrogen barrier layer on the reaction prevention layer and the exposed upper electrode, and patterning the reaction prevention layer and the conductive hydrogen barrier layer at least to surround the capacitor. Type a hydrogen barrier conductive pad in contact with the upper electrode It is achieved by including the step of.

In a preferred embodiment, after exposing a portion of the upper electrode, heat treatment is performed in an oxygen atmosphere to enhance the properties of the reaction prevention film and to cure damage caused by the exposure of the upper electrode. The oxygen atmosphere can compensate for the oxygen deficiency of the ferroelectric material film.

In another preferred embodiment, forming another insulating layer on a resultant product on which the conductive pad is formed, forming another via layer to expose the conductive pad by patterning the other insulating layer, and healing damage caused by the via hole patterning. And performing heat treatment in an oxygen atmosphere, and forming metal wirings on the other insulating layer to contact the exposed conductive pads. In this case, the conductive pad prevents penetration of hydrogen present in the other insulating layer and increases photo margin of via hole formation.

In the above-described method, the heat-resistant oxidic conductive material is formed of any one of iridium, ruthenium, iridium dioxide, ruthenium dioxide, and a combination thereof.

In the preferred embodiment, the forming of the capacitor may include sequentially forming an adhesion reinforcing film, an anti-oxidation film, a ferroelectric material film, and an upper electrode film on the contact plug and the one insulating film on both sides thereof, and electrically contacting the contact plug. Patterning the membrane formed in turn so as to contact. In this case, the adhesion reinforcing film is any one of titanium, cobalt and titanium nitride film, the antioxidant film is any one of iridium, ruthenium.

According to the preferred process configuration of the present invention described above, since the damage healing heat treatment process for the ferroelectric material film is performed twice, a more reliable ferroelectric material film can be formed. In addition, due to the second hydrogen barrier film conductive pad being formed, the grape alignment margin increases in the subsequent via hole process, making it particularly suitable for the process of forming a highly integrated ferroelectric capacitor. The hydrogen barrier film conductive pad also prevents the penetration of hydrogen in the interlayer insulating film through the upper electrode during the damage healing heat treatment. In addition, the first reaction prevention film is formed at the same time when the damage healing heat treatment, the film quality is improved.

The present invention also provides a ferroelectric capacitor structure suitable for achieving the above object of the present invention. The ferroelectric capacitor is a ferroelectric capacitor including a lower electrode, a ferroelectric material film and an upper electrode formed on one interlayer insulating film, and a spacer-type reaction extending from an edge of the upper electrode of the ferroelectric capacitor to a side portion and a part of the interlayer insulating film. And a conductive pad formed on the upper electrode surface exposed by the reaction prevention film and the reaction prevention film.

The ferroelectric capacitor may be electrically connected to the conductive pad through the conductive pad and another interlayer insulating layer formed on the interlayer insulating layer, and via holes through a predetermined portion of the other interlayer insulating layer to expose a portion of the conductive pad. A metal wiring formed in the insulating film and the via hole is further included.

The semiconductor device may further include another insulating layer under the capacitor lower electrode, and the capacitor lower electrode may be in electrical contact with a contact plug that penetrates a predetermined portion of the another insulating layer to electrically contact an active region of the semiconductor substrate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention relates to a ferroelectric capacitor and a method of forming the same, and detailed descriptions of device isolation regions, transistors, bit lines, and various insulating films formed by methods common to semiconductor manufacturing processes will be omitted.

1 is a cross-sectional view schematically showing a semiconductor substrate in which a transistor is already formed according to a preferred embodiment of the present invention, showing only a part of the semiconductor wafer. Looking at the process step, first, the semiconductor substrate 100 is prepared. The semiconductor substrate is a conventional silicon substrate. In a well known manner, an isolation region 102 is formed in a predetermined region of the semiconductor substrate 100. When the semiconductor substrate surrounded by the device isolation region 102 is called an active region, an electrical connection is formed in a subsequent process. Accordingly, the device isolation region 102 is formed of an insulating material, and a well-known method includes a local oxidation of silicon, a trench isolation method, and the like. The area (ie the active area) can be electrically isolated.

After the device isolation region 102 is formed, a transistor forming process is performed. A gate oxide film is formed for electrical insulation from the semiconductor substrate 100. Next, a gate electrode film is formed, and the gate oxide film and the gate electrode film are patterned to form a gate pattern composed of the gate electrode 106 and the gate oxide film 104. Although not shown, a capping film may be further formed on the gate electrode film as a protective film. After forming the gate pattern, an ion implantation process is performed to form source / drain regions 108a and 108b, which are impurity diffusion regions, in the active regions on both sides of the gate pattern. Next, although not shown, gate insulating film spacers are formed on both sides of the gate pattern. Here, the active region between the source / drain regions 108a and 108b, that is, the active region under the gate pattern, becomes a channel region (not shown). As a result, the gate patterns 102 and 104 including the source / drain regions 108a and 108b, the passivation layer and the spacer, and the channel region constitute a transistor.

Next, referring to FIG. 2, a first interlayer insulating film 110 is formed on the semiconductor substrate 100 on which the transistor is formed. The first interlayer insulating film 110 is typically formed of an oxide film by chemical vapor deposition (CVD). Next, a bit line forming process, which is a data line of the ferroelectric memory device, is performed. First, the first interlayer insulating layer 110 is patterned to expose a predetermined source / drain region 108a to form a contact hole for electrical connection with a bit line. A conductive material is deposited on the first interlayer insulating film 108 to fill the contact hole. Thereafter, the deposited conductive material is flattened and etched to form the bit line contact plug 112. Next, a conductive material is formed on the contact plug 112 and the first interlayer insulating layer 110, and is patterned to electrically connect the contact plug 112 to the predetermined source / drain region 108a through the contact plug 112. A line is formed. Although the drawing shows that the contact plug is formed, the bit line may be formed by immediately patterning the conductive material to fill the contact hole. Although not shown, an insulating film for protecting the bit line may be further formed.

Referring to FIG. 3, after the bit line 114 is formed, a second interlayer insulating film 116 is formed on the first interlayer insulating film 110 and the bit line 114. The second interlayer insulating film 116 is typically formed of an oxide film by a CVD method. The following is a process of forming a contact plug for electrical connection between a ferroelectric capacitor and a transistor formed in a subsequent process. First, contact holes are formed by patterning the second and first interlayer insulating films 116 and 110 to expose a predetermined source / drain 108b of the transistor. A conductive material, such as polysilicon, is deposited to completely fill the contact hole. Then, the planarization process is performed to complete the contact plug 118.

The subsequent process is a ferroelectric capacitor formation process. The adhesion reinforcing film 120, the conductive antioxidant film 122, and the lower electrode film 124 are sequentially formed. Thereafter, a ferroelectric material film 126 is formed on the lower electrode film 124 and undergoes a heat treatment process to exhibit ferroelectric properties. Thereafter, upper electrodes 128 and 130 are formed. Specifically, the adhesion reinforcing film 120 is used to enhance the adhesive property between the lower second interlayer insulating film 116 and the film deposited in a subsequent process, and also the ohmic contact with the top of the contact plug 118. Is deposited for. The adhesion reinforcing film 120 is formed of, for example, titanium, titanium nitride film, cobalt or the like. The conductive antioxidant film 122 is formed of iridium (Ir) using, for example, a sputtering method. It may also be formed of rhodium or ruthenium. The conductive antioxidant film 122 prevents the diffusion of oxygen through the upper surface of the adhesive reinforcing film 120 in a subsequent heat treatment process, thereby preventing oxidation to prevent deterioration of electrical characteristics of the adhesive reinforcing film 120.

Although the lower electrode film 124 is shown as a single layer in the drawing, it is preferable that the conductive oxide film and the metal electrode are sequentially stacked. Iridium dioxide, ruthenium dioxide, etc. are mentioned as an oxide film electrode, For example, platinum is preferable as a metal electrode. The platinum electrode provides a lattice structure that is advantageous for the crystallization of the ferroelectric material film formed on the upper surface thereof, thereby helping to form a more stable ferroelectric material film.

In the ferroelectric material film, precursors are first deposited in an amorphous form by a sol-gel method. For example, a PZT film is deposited. Then, a crystallization heat treatment is performed to cause the PZT film to exhibit ferroelectric material properties, thereby completing a ferroelectric material film 126 having unique properties.

The upper electrodes 128 and 130 are preferably formed of the oxide electrode 128 and the metal electrode 130 in the same manner as the lower electrode. For example, irinium, ruthenium, platinum electrodes, and the like may be used as the metal electrode 130, and oxide electrodes of these metal electrodes may be used as the oxide film electrodes. In addition, a single electrode of these electrodes may be used, and the order of the oxide electrode and the metal electrode may be changed.

Next, the film layers stacked for forming the capacitor are patterned to form a capacitor as shown in FIG. 5. Thereafter, heat treatment is performed to heal the damage caused by etching, for example, a charging phenomenon due to plasma etching.

Next, referring to FIG. 6, a reaction prevention layer 132 for preventing the capacitor, in particular, the dielectric material layer 126, from reacting with a foreign substance is formed on the second interlayer insulating layer 116 so as to completely surround the capacitor. do. The anti-reaction film prevents material movement between the capacitor and the external environment surrounding the ferroelectric material film to prevent the ferroelectric material film from reacting with the external foreign matter to prevent its properties from deteriorating.

In the next step, the reaction prevention layer 134 is patterned to expose a portion of the upper electrode 132 (reference numeral 134). Thereafter, the heat treatment is performed to strengthen the properties of the anti-reaction film while healing damage caused by the anti-reaction film patterning. The heat treatment is preferably carried out in an oxygen atmosphere. This is because the oxygen deficiency of the ferroelectric material film may be compensated for. The reason for exposing a part of the upper electrode is to form a conductive pad as described later.

Next, referring to FIG. 8, a hydrogen barrier layer 136 is formed on the exposed upper electrode 134 and the reaction barrier layer 130. The hydrogen barrier layer 136 is for preventing hydrogen in the subsequent interlayer dielectric layer from penetrating into the ferroelectric material film through the upper electrode or through the capacitor side portion in the heat treatment notarization. Therefore, according to the present invention, the reaction prevention film 132 and the hydrogen prevention film 136 serve as a film to protect the capacitor ferroelectric material film. In addition, as will be described later, the hydrogen barrier layer 136 improves the alignment margin of the photo process for the subsequent via hole forming process. The hydrogen barrier layer 136 is formed of a heat resistant, oxidation resistant conductive material, or conductive oxide. For example, heat resistant and oxidation resistant conductive materials include iridium, ruthenium, and the like, and conductive oxides include an iridium oxide film and a ruthenium oxide film. It is also possible to form a multilayer film using a combination of these.

Next, as shown in FIG. 9, the hydrogen barrier layer 136 and the reaction barrier layer 134 are patterned in sequence. As a result, a conductive pad 136 is formed in electrical contact with the upper electrode. At this time, the capacitor is separated in units of cells. The conductive pad 136 has a larger area than the size of the upper electrode, thereby significantly improving the photo alignment margin in the subsequent via hole forming process. As a result, the via hole misalignment caused by the reduction of the upper electrode area due to the high integration can be avoided.

Next, referring to FIG. 10, a third interlayer insulating film 138 is formed on the resultant product on which the conductive pad 136 is formed. The third interlayer insulating film 138 is formed of a CVD oxide film. Subsequently, the third interlayer insulating layer 138 is patterned to form a via hole 140 exposing the conductive pad 136 through a via hole forming process. Next, a heat treatment for healing the etching damage due to the via hole patterning is preferably performed in an oxygen atmosphere. At this time, according to the present invention, since the capacitor side portion is protected by the reaction prevention film 132 and the conductive pad 136 and the upper portion is protected by the conductive pad 136, it is possible to effectively prevent hydrogen infiltration.

Next, referring to FIG. 11, a conductive material for metal wiring is formed and patterned on the via hole 140 and the third interlayer insulating layer 138 to form a metal wiring 142.

Referring to FIG. 11, the ferroelectric capacitor according to the present invention includes a reaction prevention film 132 and a hydrogen prevention film conductive pad 136. The metal wire 142 and the upper electrode 130 are electrically connected through the conductive pad 136. Specifically, the reaction prevention film 132 extends from the upper edge of the capacitor and is formed in the form of a spacer to the side portion and a part of the interlayer insulating film, and exposes a portion of the upper electrode. A conductive pad 136 is formed on the reaction prevention layer while contacting the capacitor upper electrode exposed by the reaction prevention layer 132. As a result, according to the present invention, the capacitor has a protective film 132 and a conductive pad 136 on its side, and a protective pad and a conductive pad on its upper edge, and a conductive pad on its portion except the edge. Therefore, it is possible to effectively prevent deterioration of the characteristics of the capacitor ferroelectric material film. Also, as shown, the area of the conductive pad is relatively larger than that of the upper electrode. As a result, the photo alignment margin of the subsequent via hole process is increased to prevent misalignment of the via hole.

Although the present invention has been described with reference to preferred embodiments, the scope of the present invention is not limited thereto. Rather, various modifications and similar arrangements are included. Therefore, the true scope and spirit of the claims of the present invention should be interpreted broadly to encompass such modifications and similar arrangements.

As described above, according to the present invention, in order to protect the capacitor, the reaction prevention film and the conductive pad are formed to completely surround the capacitor.

In this case, the conductive pad is formed on the reaction prevention film so as to be in electrical contact with the upper electrode, thereby improving the photo alignment margin of via hole formation due to high integration.

In addition, the conductive pad prevents hydrogen in the interlayer insulating film from penetrating into the ferroelectric material film through the upper electrode, and at the capacitor side, the reaction prevention film and the conductive pad prevent the material from penetrating, thereby preventing deterioration of characteristics of the ferroelectric material film.

Claims (10)

In the method of forming a ferroelectric capacitor, Forming a contact plug penetrating a predetermined portion of an insulating film formed on a semiconductor substrate having an active region and contacting the active region; Forming a ferroelectric capacitor on the contact plug and the one insulating film on both sides thereof; Forming a reaction prevention film on the one insulating film and the capacitor; Patterning the reaction prevention layer to expose a portion of the upper electrode; Forming a conductive hydrogen barrier on the reaction barrier and the exposed upper electrode; And, And patterning the reaction prevention film and the conductive hydrogen prevention film so as to surround at least the capacitor, thereby forming a hydrogen barrier film conductive pad in contact with the upper electrode. The method of claim 1, After exposing a portion of the upper electrode, further enhancing the properties of the anti-reaction film, and performing heat treatment in an oxygen atmosphere to heal damage caused by the anti-reaction film patterning. How to form a capacitor. The method according to claim 1 or 2, Forming another insulating film on a resultant product on which the conductive pad is formed; Patterning the another insulating film to form a via hole exposing the conductive pad; Performing heat treatment in an oxygen atmosphere to heal damage caused by the via hole patterning; And, Forming metal wires on the other insulating layer to contact the exposed conductive pads; In this case, the conductive pad is a method of forming a ferroelectric capacitor of a semiconductor device, characterized in that to prevent the penetration of hydrogen present in the other insulating film. The method of claim 1, wherein the conductive pad is any one of iridium, ruthenium, iridium dioxide, ruthenium dioxide, and a combination thereof. The method of claim 1, Forming the capacitor, Sequentially forming an adhesion strengthening film, an anti-oxidation film, a ferroelectric material film, and an upper electrode film on the contact plug and the one insulating film on both sides thereof; And, And patterning the film quality formed in order so as to be in electrical contact with the contact plug. The method of claim 5, The adhesion reinforcing film is any one of titanium, cobalt and titanium nitride film, and the anti-oxidation film is any one of iridium, rhodium, ruthenium. The method of claim 1, The reaction prevention film is a method of forming a ferroelectric capacitor of a semiconductor device, characterized in that the titanium oxide film or aluminum oxide film. In ferroelectric capacitors, A ferroelectric capacitor formed on the interlayer insulating film, the ferroelectric capacitor comprising a lower electrode, a ferroelectric material film, and an upper electrode; A reaction prevention film extending from an edge of the upper electrode of the ferroelectric capacitor to a side portion and a part of the interlayer insulating film in a spacer form; And, And a conductive pad formed on the upper electrode surface exposed by the reaction prevention film and the reaction prevention film. The method of claim 8, Another interlayer insulating film formed on the conductive pad and the one interlayer insulating film; And, And a metal wiring formed in the other interlayer insulating film and the via hole to be electrically connected to the conductive pad through a via hole through a predetermined portion of the other interlayer insulating film and exposing a portion of the conductive pad. The method according to claim 9 or 10, The conductive pad is any one of iridium, ruthenium, iridium dioxide, ruthenium dioxide, and a combination thereof.