KR20020010403A - Method for fabricating 3-dimensional silicon wafer by using thin-film layer having different depth - Google Patents
Method for fabricating 3-dimensional silicon wafer by using thin-film layer having different depth Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 84
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 82
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 82
- 239000010703 silicon Substances 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000005530 etching Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 20
- 235000012431 wafers Nutrition 0.000 description 72
- 238000001459 lithography Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000011324 bead Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M potassium hydroxide Inorganic materials [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZJOWACHQXFQBCF-UHFFFAOYSA-M [OH-].O.O.O.P.[K+] Chemical compound [OH-].O.O.O.P.[K+] ZJOWACHQXFQBCF-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
본 발명은 상이한 깊이를 가진 박막층에 의한 3차원 실리콘 웨이퍼 제조 방법에 관한 것으로서, 보다 상세하게는 실리콘 웨이퍼의 박막층을 상이한 깊이를 가지도록 형성한 후 박막층을 순차적으로 제거하면서 노출된 실리콘 웨이퍼를 단계적으로 식각하여 3차원 실리콘 웨이퍼를 제조하는 방법에 관한 것이다.The present invention relates to a three-dimensional silicon wafer manufacturing method using a thin film layer having a different depth, and more particularly, after forming the thin film layer of the silicon wafer to have a different depth, and subsequently removing the thin film layer step by step to expose the exposed silicon wafer It relates to a method of manufacturing a three-dimensional silicon wafer by etching.
근래에 3차원 실리콘 웨이퍼는 광트랜시버(optical transceiver), 광소자, 반도체 센서, 액츄에이터(actuator), 미세소자, 패키징(packaging) 등에 많이 사용되고 있다.In recent years, three-dimensional silicon wafers are widely used in optical transceivers, optical devices, semiconductor sensors, actuators, microdevices, and packaging.
3차원 실리콘 웨이퍼의 일예로서 도1에 도시된 바와 같은 실리콘 광 벤치(silicon optical bench)가 있는 데, 여기에는 다양한 깊이의 3차원 구조의 U홈들(1,2,3,4,5)들이 형성되어 예컨대 가이드 핀(guide pin), 광파이버(optical fiber), 레이저 다이오우드(laser diode), 포토 다이오우드(photo diode), 모니터 포토 다이오우드(monitor photo diode), 광 도파로 등을 올려 놓을 수 있다. 예컨대 가이드 핀이 놓여지는 U홈(5)의 깊이는 400㎛으로, 레이저 다이오우드 및 포토 다이오우드가 놓여지는 U홈(2,3)의 깊이는 각각 20㎛, 40㎛으로 형성하여야 하기 때문에, 실리콘 웨이퍼에 서로 다른 깊이 또는 형상을 가진 3차원적 구조가 형성될 필요가 있다.As an example of a three-dimensional silicon wafer, there is a silicon optical bench as shown in Fig. 1, in which U-grooves 1, 2, 3, 4, and 5 of various depths are formed. For example, a guide pin, an optical fiber, a laser diode, a photo diode, a monitor photo diode, an optical waveguide, and the like can be mounted. For example, the depth of the U groove 5 on which the guide pin is placed is 400 mu m, and the depths of the U grooves 2, 3 on which the laser diode and the photo diode are placed should be 20 mu m and 40 mu m, respectively. It is necessary to form three-dimensional structures with different depths or shapes.
이를 위해 종래에는 도2에 도시된 바와 같은 공정 방법을 사용하여 3차원 구조의 실리콘 웨이퍼를 제조하였다.To this end, a silicon wafer having a three-dimensional structure is manufactured by using a process method as shown in FIG. 2.
즉, 먼저 깨끗이 세척된 실리콘 웨이퍼(20)을 준비하여(1a), 실리콘 웨이퍼(20)위에 예컨대 질화막이나 산화막과 같은 박막층(21)을 형성하고, 그 위에PR(Photo Regist)층(22)을 형성한다(1b). 그리고 실리콘 웨이퍼 위에 포토 마스크를 정렬(alignment)하고, PR층을 노광(exposure), 현상(development), 세척(cleaning)하는 일련의 석판인쇄공정(photolithography)을 거친 후에 박막층(21)을 선택적으로 식각하여 패턴을 전사한다(1c). 그리고 실리콘 웨이퍼를 습식식각하여 경사면을 가진 예컨대 깊이 400㎛의 U홈(5)을 형성하고(1d), 잔류 박막층(21)을 제거함으로써(1e), 첫째 종류의 U홈(5)을 형성한다.That is, first, the cleaned silicon wafer 20 is prepared (1a), and a thin film layer 21 such as a nitride film or an oxide film is formed on the silicon wafer 20, and a PR (Photo Regist) layer 22 is formed thereon. To form (1b). The thin film layer 21 is selectively etched after the photomask is aligned on the silicon wafer, and a series of photolithography processes are performed to expose, develop, and clean the PR layer. The pattern is transferred (1c). Then, the silicon wafer is wet-etched to form a U groove 5 having a slope, for example, 400 μm deep (1d), and the remaining thin film layer 21 is removed (1e) to form a first type of U groove 5. .
그 후에 다른 종류의 U홈 예컨대 깊이 40㎛의 U홈(3)을 형성하려면 전술한 바와 유사한 공정을 반복하여야 한다. 즉, 다시 깨끗이 세척된 실리콘 웨이퍼(20)을 준비하여(1e), 실리콘 웨이퍼(20)위에 예컨대 질화막이나 산화막과 같은 박막층(25)을 형성하고, 그 위에 PR(Photo Regist)층(26)을 형성한다(2b). 그리고 실리콘 웨이퍼 위에 포토 마스크를 정렬(alignment)하고, PR층을 노광(exposure), 현상(development), 세척(cleaning)하는 일련의 석판인쇄공정(photolithography)을 거친 후에 박막층(25)을 선택적으로 식각하여 패턴을 전사한다(2c). 그리고 실리콘 웨이퍼를 습식식각하여 깊이 40㎛의 U홈(3)을 형성하고(2d), 잔류 박막층(25)을 제거함으로써(2e), 둘째 종류의 U홈(5)을 형성하는 공정이 종료된다. 셋째 종류인 예컨대 깊이 20㎛의 U홈(2) 역시 동일한 공정을 반복하여 형성된다 (3b,3c,3d,3e).Thereafter, in order to form another kind of U groove, for example, the U groove 3 having a depth of 40 mu m, a similar process to that described above must be repeated. That is, the cleaned silicon wafer 20 is prepared again (1e), and a thin film layer 25 such as a nitride film or an oxide film is formed on the silicon wafer 20, and a PR (Photo Regist) layer 26 is formed thereon. To form (2b). The thin film layer 25 is selectively etched after the photomask is aligned on the silicon wafer, and the PR layer is exposed, developed, and cleaned through a series of photolithography processes. The pattern is transferred (2c). Then, the process of forming the second type of U groove 5 is completed by wet etching the silicon wafer to form the U groove 3 having a depth of 40 μm (2d), and removing the remaining thin film layer 25 (2e). . The third type, for example, the U groove 2 having a depth of 20 mu m is also formed by repeating the same process (3b, 3c, 3d, 3e).
즉 종래의 3차원 실리콘 웨이퍼를 제조하는 방법을 사용하여 도1에 도시된 바와 같은 5가지 서로 다른 유형별 종류의 3차원 형상의 U홈들(1,2,3,4,5)을 만들려면, 각 유형별 종류의 3차원 형상에 따라 전술한 바와 같은 박막층 형성, 석판인쇄공정, 실리콘 웨이퍼의 습식식각, 잔류 박막층 제거 공정을 각각 5회 반복하여야하기 때문에 많은 단계의 제조공정을 거쳐야 하는 문제점이 있다.That is, by using a conventional method of manufacturing a three-dimensional silicon wafer, to make five different types of three-dimensional U-shaped grooves (1, 2, 3, 4, 5) as shown in FIG. According to the three-dimensional shape of each type, the thin film layer forming process, lithography process, wet etching of the silicon wafer, and the remaining thin film layer removing process have to be repeated five times.
또한 실리콘 웨이퍼상에 제조할 각 U홈들(1,2,3,4,5)의 깊이는 통상 수백㎛에서 수십㎛까지 다양한 깊이를 가져 U홈의 깊이 차가 크기 때문에, PR층을 스핀 코팅(spin coating)할 때 U홈의 경계 부분에서 PR층이 함몰되거나 돌출되는 에지 비드(edge bead) 현상이 나타나 PR층이 불균일하게 코팅되는 문제점이 있다.In addition, since the depths of the U grooves 1, 2, 3, 4, and 5 to be manufactured on the silicon wafer have various depths from several hundreds of micrometers to several tens of micrometers, the depth of the U grooves is large, so the spin coating of the PR layer At the time of coating, an edge bead phenomenon occurs in which the PR layer is recessed or protrudes at the boundary of the U-groove, so that the PR layer is unevenly coated.
이와 같은 PR층의 불균일 코팅으로 인한 요철은 석판인쇄공정에서 포토 마스크를 실리콘 웨이퍼상에 정렬할 때 정렬 오차를 크게 하며, 또한 포토 마스크와 실리콘 웨이퍼사이에 접촉정렬을 나쁘게 하고, 노광시에 회절의 발생을 야기하기 때문에, 실리콘 웨이퍼상에 정확히 패턴을 전사하기 어려운 문제점이 있다. 한편 PR층은 에지 비드가 발생하는 영역 또는 U홈내의 일부 영역에서는 두껍게 코팅되는 반면 타 영역에서는 얇게 코팅되기 때문에, 현상공정에서 현상시간을 조절하기 어려운 문제점이 있다.The irregularities caused by the non-uniform coating of the PR layer increase the alignment error when the photo mask is aligned on the silicon wafer in the lithography process, and also worsen the contact alignment between the photo mask and the silicon wafer, There is a problem that it is difficult to transfer the pattern accurately on the silicon wafer because it causes the occurrence. On the other hand, since the PR layer is thickly coated in the region where the edge bead occurs or in some regions in the U-groove, but thinly coated in the other region, it is difficult to control the development time in the developing process.
본 발명의 목적은 이와 같은 종래의 문제점을 해결하기 위한 것으로서, 상이한 높이를 가진 박막층을 이용하여 복잡한 3차원 실리콘 웨이퍼 형상을 제조하는 공정을 단순화시키는 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional problem, and to provide a method for simplifying a process of manufacturing a complex three-dimensional silicon wafer shape using thin layers having different heights.
본 발명의 다른 목적은 3차원 실리콘 웨이퍼를 제조하기 위하여 매번 새로운 박막층을 형성하고 실리콘 웨이퍼의 형상을 만든 후에 잔류 박막층을 제거하고 다시 새로운 박막층을 형성하는 박막층의 형성 및 제거의 반복된 공정을 생략함으로써, 3차원 실리콘 웨이퍼 형상 제조 공정을 단순화하는 데 있다.Another object of the present invention is to omit the repeated process of forming and removing the thin film layer which removes the remaining thin film layer and again forms a new thin film layer after forming a new thin film layer each time to form a three-dimensional silicon wafer and forming the shape of the silicon wafer. To simplify the manufacturing process of 3D silicon wafer shape.
본 발명의 다른 목적은 3차원 실리콘 웨이퍼 형상을 제조하는 시간,비용을 절감하여 생산성을 크게 향상시킨 3차원 실리콘 웨이퍼 형상 제조방법을 제공하는 데 있다.Another object of the present invention is to provide a three-dimensional silicon wafer shape manufacturing method which greatly improves productivity by reducing the time and cost of manufacturing a three-dimensional silicon wafer shape.
도1은 3차원 실리콘 웨이퍼의 개략도이다.1 is a schematic diagram of a three-dimensional silicon wafer.
도2는 종래의 방법에 따른 3차원 실리콘 웨이퍼 제조 방법을 나타내는 공정 순서의 개략도이다.2 is a schematic diagram of a process sequence showing a three-dimensional silicon wafer manufacturing method according to a conventional method.
도3은 본 발명의 실시예에 따른 상이한 깊이를 가진 박막층에 의한 3차원 실리콘 웨이퍼 제조 방법을 나타내는 공정 순서의 개략도이다.Figure 3 is a schematic diagram of a process sequence showing a three-dimensional silicon wafer manufacturing method by a thin film layer having a different depth in accordance with an embodiment of the present invention.
도4는 본 발명의 실시예에 따른 상이한 깊이를 가진 박막층에 의한 3차원 실리콘 웨이퍼 제조 방법으로 제조된 3차원 실리콘 웨이퍼를 촬영한 사진이다.4 is a photograph of a three-dimensional silicon wafer manufactured by a three-dimensional silicon wafer manufacturing method using a thin film layer having a different depth according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1,2,3,4,5: U홈 20,30: 실리콘 웨이퍼1,2,3,4,5: U-groove 20,30: silicon wafer
21,31: 박막층 22,39: PR층21,31: thin film layer 22,39: PR layer
32,33,35: 박막층 홈32,33,35: thin film groove
본 3차원 실리콘 웨이퍼 형상 제조 방법은 실리콘 웨이퍼에 형성될 3차원 형상의 유형별 종류에 대응되는 상이한 높이를 가진 박막층을 형성하는 단계와; 상기 상이한 높이의 박막층을 순차적으로 제거하여 선택적으로 실리콘 웨이퍼를 노출하는 단계와; 상기 노출된 실리콘 웨이퍼를 식각하는 단계를 포함한다.The three-dimensional silicon wafer shape manufacturing method includes the steps of forming a thin film layer having a different height corresponding to the type of three-dimensional shape to be formed on the silicon wafer; Sequentially removing the thin film layers of different heights to selectively expose a silicon wafer; Etching the exposed silicon wafer.
여기서 상기 박막층을 형성하는 단계는, 실리콘 웨이퍼에 전체적으로 균일한 높이의 박막층을 형성하는 단계와; 상기 박막층을 단계적으로 식각하여 상기 3차원 형상에 대응되는 박막층이 상이한 높이를 가지도록 하는 단계를 포함하는 것을 특징으로 할 수 있다.The forming of the thin film layer may include forming a thin film layer having a uniform height on a silicon wafer; And etching the thin film layer step by step so that the thin film layer corresponding to the three-dimensional shape has different heights.
또한 상기 상이한 높이의 박막층은 전체적으로 균일하게 식각됨에 따라 순차적으로 제거되는 것을 특징으로 할 수 있다.In addition, the thin film layer having different heights may be sequentially removed as the whole is uniformly etched.
이하, 첨부된 도면들을 참조로 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정해서 해석되어서는 아니되며, 발명자는 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다. 따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장바람직한 일 실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the present specification and claims should not be construed as being limited to the ordinary or dictionary meanings, and the inventors properly define the concept of terms in order to best explain the invention in the best way. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that it can. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.
도3은 본 발명의 실시예에 따른 상이한 깊이를 가진 박막층에 의한 3차원 실리콘 웨이퍼 제조 방법을 나타내는 공정 순서의 개략도이다.Figure 3 is a schematic diagram of a process sequence showing a three-dimensional silicon wafer manufacturing method by a thin film layer having a different depth in accordance with an embodiment of the present invention.
먼저 깨끗이 세정된 실리콘 웨이퍼(30)를 준비하여(a), 그 위에 질화막이나 산화막과 같은 박막층(31)을 균일한 높이로 형성하고, 그 위에 다시 예컨대 석판인쇄공정을 사용하여 패턴을 전사할 수 있도록 PR층(39)을 형성하는 것이 바람직하다(b).First, a clean silicon wafer 30 is prepared (a), and a thin film layer 31 such as a nitride film or an oxide film is formed thereon at a uniform height, and the pattern can be transferred again using, for example, a lithography process. It is preferable to form the PR layer 39 so as to (b).
석판인쇄공정에 의해 전사된 패턴에 따라 박막층(31)은 선택적으로 식각될 수 있다(c). 예컨대 도3의 (k)에 도시된 바와 같이 깊이 400㎛ U홈(5), 40㎛ U홈(3), 20㎛ U홈(2)을 가진 3차원 실리콘 웨이퍼를 제조하려면, 먼저 각 U홈들(5,3,2)에 대응되는 박막층 홈들(35,33,32)의 높이가 d1이 되도록 박막층(31)을 선택적으로 1차로 식각하는 것이 바람직하다(c). 여기서 높이 d1은 제조하고자 하는 3차원 실리콘 웨이퍼의 형상을 감안하여 결정할 수 있는 데, 즉 제조하려는 실리콘 웨이퍼의 3차원 형상의 유형별 종류의 개수에 상응하는 만큼의 단계로 박막층을 순차적으로 식각하기에 충분한 높이인 것이 바람직하다.The thin film layer 31 may be selectively etched according to the pattern transferred by the lithography process (c). For example, to fabricate a three-dimensional silicon wafer having a depth of 400 μm U groove 5, 40 μm U groove 3, and 20 μm U groove 2 as shown in FIG. It is preferable to selectively etch the thin film layer 31 first so that the height of the thin film layer grooves 35, 33, 32 corresponding to (5, 3, 2) becomes d1. The height d1 may be determined in consideration of the shape of the three-dimensional silicon wafer to be manufactured, that is, sufficient to sequentially etch the thin film layer in steps corresponding to the number of types of the three-dimensional shapes of the silicon wafer to be manufactured. It is preferable that it is height.
그 후에 U홈(2)이 형성될 위치의 박막층 홈(32)을 제외하고 석판인쇄공정에 의해 전사된 패턴에 따라 박막층을 2차로 식각하면, 박막층 홈(32)의 높이는 d1이지만 박막층 홈(33,35)의 높이는 d2가 될 것이다(d). 본 실시예에서는 0.5㎛의 균일한 높이로 형성된 박막층(31)을 d1=0.2㎛, d2=0.1㎛가 되도록 식각 하였다. 한편 도3에 나타낸 점선은 이전 공정에서의 박막층의 높이를 나타낸 것으로 현 공정에서 식각에 의해 제거된 박막층이 높이를 도시하기 위함이다.Subsequently, when the thin film layer is secondly etched according to the pattern transferred by the lithography process except for the thin film layer groove 32 at the position where the U groove 2 is to be formed, the height of the thin film layer groove 32 is d1 but the thin film layer groove 33 , 35) will be d2 (d). In this embodiment, the thin film layer 31 formed at a uniform height of 0.5 μm was etched to have d1 = 0.2 μm and d2 = 0.1 μm. Meanwhile, the dotted line shown in FIG. 3 indicates the height of the thin film layer in the previous process, in order to show the height of the thin film layer removed by etching in the current process.
다음에, U홈(2,3)이 형성될 위치의 박막층 홈(32,33)을 제외하고 석판인쇄공정에 의해 전사된 패턴에 따라 박막층을 3차로 식각하여 박막층 홈(35) 하부의 실리콘 웨이퍼가 노출되도록 한다(e). 이와 같이 단계적으로 박막층을 식각하면 박막층 홈들(35,33,32)의 높이는 각각 0,d2,d1으로 상이하게 되며, 실리콘 웨이퍼에 형성하고자 하는 3차원 형상의 유형별 종류인 U홈들(5,3,2)의 종류에 각각 대응되는 상이한 높이를 가진 박막층이 형성된다(e).Next, except for the thin film layer grooves 32 and 33 at the positions where the U grooves 2 and 3 are to be formed, the thin film layer is etched in a third order according to the pattern transferred by the lithography process, so that the silicon wafer under the thin film layer groove 35 is formed. (E) is exposed. When the thin film layer is etched in this manner, the heights of the thin film layer grooves 35, 33, and 32 are respectively 0, d 2, and d 1, and the U grooves 5, 3, which are types of three-dimensional shapes to be formed on the silicon wafer, are formed. Thin film layers having different heights respectively corresponding to the types of 2) are formed (e).
이처럼 노출된 실리콘 웨이퍼를 습식식각하여 먼저 U홈(5)을 360㎛의 깊이로 식각한다(f).The exposed silicon wafer is wet etched to first etch the U groove 5 to a depth of 360 μm (f).
그리고 박막층 홈(33) 하부의 실리콘 웨이퍼가 노출되도록 박막층(31)을 전체적으로 균일하게 식각한다(g). 여기서 박막층(31)은 상이한 높이를 가지고 있기 때문에, 박막층(31)을 전체적으로 균일하게 식각하면 박막층 홈(33) 하부의 실리콘 웨이퍼를 선택적으로 노출시킬 수 있다. 따라서 박막층(31)을 선택적으로 식각하기 위하여 석판인쇄공정을 사용할 필요가 없으며, 때문에 석판인쇄공정시에 발생하는 U홈의 경계 부분에서의 PR층 함몰, 돌출 등의 에지 비드(edge bead) 현상은 전혀 발생하지 않는다.The thin film layer 31 is uniformly etched as a whole so that the silicon wafer under the thin film layer groove 33 is exposed (g). Since the thin film layer 31 has different heights, the silicon wafer under the thin film layer groove 33 may be selectively exposed by uniformly etching the thin film layer 31 as a whole. Therefore, it is not necessary to use a lithographic printing process to selectively etch the thin film layer 31. Therefore, edge bead phenomenon such as PR layer depression and protrusion at the boundary portion of the U groove generated during the lithographic printing process It doesn't happen at all.
이렇게 노출된 실리콘 웨이퍼를 습식식각하여 U홈들(3,5)을 20㎛의 깊이로 식각하면, U홈(3)의 깊이는 20㎛로 되고 U홈(5)의 깊이는 380㎛가 된다(h).When the exposed silicon wafer is wet etched to etch the U grooves 3 and 5 to a depth of 20 μm, the depth of the U groove 3 is 20 μm and the depth of the U groove 5 is 380 μm ( h).
다시 박막층 홈(32) 하부의 실리콘 웨이퍼가 노출되도록 박막층(31)을 전체적으로 균일하게 식각한 후에(i), 노출된 실리콘 웨이퍼를 습식식각하여 U홈들(2,3,5)을 20㎛의 깊이로 식각하면, U홈(2)의 깊이는 20㎛로 되고, U홈(3)의 깊이는 40㎛의 깊이로 되며, U홈(5)은 400㎛의 깊이로 되어 원하는 3차원 형상을 얻을 수 있고(j), 실리콘 웨이퍼위의 잔류 박막층(31)을 제거하여(k), 실리콘 웨이퍼를 완성한다. 도4는 이렇게 제조된 3차원 실리콘 웨이퍼를 사진 촬영한 것이다.The thin film layer 31 is uniformly etched to expose the silicon wafer under the thin film layer groove 32 (i), and the exposed silicon wafer is wet etched to form the U grooves 2, 3, and 5 in a depth of 20 μm. Etching, the depth of the U groove 2 is 20㎛, the depth of the U groove 3 is 40㎛, the U groove 5 is 400㎛ depth to obtain the desired three-dimensional shape (J), the remaining thin film layer 31 on the silicon wafer is removed (k) to complete the silicon wafer. 4 is a photograph of a three-dimensional silicon wafer thus manufactured.
본 발명에 따른 3차원 실리콘 웨이퍼 형상 제조방법에 있어서, 박막층(31)을 전체적으로 균일하게 식각하는 것은 예컨대 반응성 이온 식각(recative ion etching)으로 식각하는 것이 바람직하며, 실리콘 웨이퍼는 식각용액 예컨대 이방성 식각용액인 수산화칼륨(KOH)용액이나 TMAH(Tetramethyl-ammoniumhydroxide)용액을 사용하여 습식식각하는 것이 바람직하다.In the method for manufacturing a three-dimensional silicon wafer shape according to the present invention, it is preferable to etch the entire thin film layer 31 uniformly by, for example, reactive ion etching, and the silicon wafer may be an etching solution such as an anisotropic etching solution. It is preferable to wet-etch using a phosphorus potassium hydroxide (KOH) solution or a tetramethyl-ammoniumhydroxide (TMAH) solution.
본 실시예에서는 상이한 높이를 가진 박막층을 형성하기 위하여 도3에 도시된 단계인 (c),(d),(e)의 순서로 박막층을 식각하는 것으로 설명하였으나, 이는 설명의 편의를 위한 것으로 박막층을 식각하는 순서를 바꿔 상이한 높이를 가진 박막층을 형성하는 것도 가능하며, 또한 식각이외의 다른 방법을 사용하여 상이한 높이를 가진 박막층을 형성할 수도 있음은 물론이다.In the present embodiment, the thin film layer is etched in the order of (c), (d), and (e), which are the steps shown in FIG. 3, to form a thin film layer having different heights, but this is for convenience of description. It is also possible to form a thin film layer having a different height by changing the order of etching, and may also form a thin film layer having a different height by using a method other than etching.
이상 실시예를 들어 본 발명에 대해 설명하였으나, 본 발명은 상술한 실시예에 한정되는 것은 아니며, 본 발명에 따른 제조 방법으로 제조할 수 있는 3차원 실리콘 웨이퍼는 다양한 깊이의 U홈이 형성된 실리콘 웨이퍼 뿐만 아니라, 다양한 형상이 형성되는 실리콘 웨이퍼 또는 반도체에도 동일한 발명 사상 및 원리로서 다양하게 변형되어 적용될 수 있다. 따라서, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술사상 및 기술범위내에서 행한 각종 변경 및 개량은 본 발명의 권리범위에 속하는 것임을 밝혀 둔다.Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above-described embodiments, and the three-dimensional silicon wafer which can be manufactured by the manufacturing method according to the present invention is a silicon wafer having U grooves of various depths. In addition, various modifications may be applied to the silicon wafer or the semiconductor having various shapes as the same idea and principle. Therefore, various changes and improvements made by those skilled in the art within the technical spirit and scope of the present invention fall within the scope of the present invention.
종래의 3차원 실리콘 웨이퍼 형상 제조 방법은 실리콘 웨이퍼를 식각할 때마다 반복적으로 실리콘 웨이퍼 위에 새로운 박막층을 형성하여 실리콘 웨이퍼를 식각한 후에 박막층을 제거하고 다시 새로운 박막층을 형성하는 공정을 반복하여야 했다.In the conventional three-dimensional silicon wafer shape manufacturing method, a new thin film layer is repeatedly formed on the silicon wafer every time the silicon wafer is etched, and the process of removing the thin film layer and forming a new thin film layer again after etching the silicon wafer.
그러나, 본 발명에 따른 3차원 실리콘 웨이퍼 형상 제조 방법은 최초에 형성된 박막층을 이용하여 실리콘 웨이퍼를 단계적으로 식각하여 3차원 실리콘 웨이퍼 형상의 제조를 마친 후에 최종적으로 박막층을 제거한다. 따라서 본 발명은 실리콘 웨이퍼의 매 식각공정마다 새로운 박막층을 형성하고 이를 제거한 후에 다시 새로운 박막층을 형성하는 반복된 공정을 생략할 수 있기 때문에, 3차원 실리콘 웨이퍼 형상 제조 공정을 현저하게 단순화하며, 시간,비용을 크게 절감하여 생산성을 향상시키는 효과가 있다.However, in the method for manufacturing a three-dimensional silicon wafer shape according to the present invention, the silicon wafer is etched step by step using the first thin film layer, and finally the thin film layer is finally removed after the production of the three-dimensional silicon wafer shape. Therefore, the present invention can omit the repeated process of forming a new thin film layer in every etching process of the silicon wafer, removing the new thin film layer, and then again forming a new thin film layer, thereby greatly simplifying the three-dimensional silicon wafer shape manufacturing process. There is a significant cost savings to improve productivity.
또한 본 발명은, 석판인쇄공정을 위하여 깊이가 수백㎛까지 차이가 나는 실리콘 웨이퍼의 U홈위에 PR층을 형성하여야 하는 종래의 방법과는 달리, 비교적 균일한 깊이인 0.5㎛이하의 깊이 차를 가진 박막층에서만 석판인쇄공정이 적용되기 때문에, PR층이 균일하게 코팅된다. 따라서, 포토 마스크를 웨이퍼상에 정렬할 때 정렬 오차를 최소화할 수 있으며, 포토 마스크와 실리콘 웨이퍼사이에 접촉정렬이우수하여 노광시에 회절의 발생이 최소화되기 때문에, 실리콘 웨이퍼상에 정확히 패턴을 전사할 수 있는 효과가 있다. 한편 PR층이 박막층위에서 비교적 균일하게 코팅되기 때문에, 석판인쇄의 현상공정에서 현상시간을 조절하기 용이한 효과가 있다.In addition, the present invention, unlike the conventional method for forming a PR layer on the U groove of the silicon wafer having a depth difference of several hundred micrometers for the lithography process, having a depth difference of less than 0.5㎛ that is a relatively uniform depth Since the lithography process is applied only to the thin film layer, the PR layer is uniformly coated. Therefore, alignment error can be minimized when aligning the photo mask on the wafer, and excellent contact alignment between the photo mask and the silicon wafer minimizes the occurrence of diffraction during exposure, thereby accurately transferring the pattern onto the silicon wafer. It can be effective. On the other hand, since the PR layer is coated relatively uniformly on the thin film layer, there is an effect of easily controlling the development time in the developing process of lithography.
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|---|---|---|---|---|
| JPS6197833A (en) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US4863560A (en) * | 1988-08-22 | 1989-09-05 | Xerox Corp | Fabrication of silicon structures by single side, multiple step etching process |
| JPH03295255A (en) * | 1990-04-12 | 1991-12-26 | Matsushita Electric Works Ltd | Manufacture of insulating layer isolating substrate |
| US5277755A (en) * | 1991-12-09 | 1994-01-11 | Xerox Corporation | Fabrication of three dimensional silicon devices by single side, two-step etching process |
-
2000
- 2000-07-29 KR KR1020000044108A patent/KR100342480B1/en not_active IP Right Cessation
- 2000-11-24 JP JP2000358110A patent/JP2002057140A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434840B1 (en) * | 2001-08-06 | 2004-06-07 | 주식회사 미뉴타텍 | Method for fabricating semiconductor devices by using pattern with three-dimensional |
| CN115841946A (en) * | 2023-02-24 | 2023-03-24 | 广州粤芯半导体技术有限公司 | Deep silicon etching optimization method |
| CN115841946B (en) * | 2023-02-24 | 2023-06-27 | 粤芯半导体技术股份有限公司 | Deep silicon etching optimization method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100342480B1 (en) | 2002-06-28 |
| JP2002057140A (en) | 2002-02-22 |
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