KR20020006362A - Method for forming a copper wiring layer in semiconductor device - Google Patents
Method for forming a copper wiring layer in semiconductor device Download PDFInfo
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- KR20020006362A KR20020006362A KR1020000039989A KR20000039989A KR20020006362A KR 20020006362 A KR20020006362 A KR 20020006362A KR 1020000039989 A KR1020000039989 A KR 1020000039989A KR 20000039989 A KR20000039989 A KR 20000039989A KR 20020006362 A KR20020006362 A KR 20020006362A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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Abstract
반도체 소자의 구리 배선층 형성 방법을 제공한다. 본 발명은 반도체 기판 상에 트랜치를 갖는 층간 절연막을 형성한 후, 상기 층간 절연막이 형성된 반도체 기판의 전면에 배리어 금속막과 씨드층을 순차적으로 형성한다. 상기 씨드층 상에 희생층을 형성한 후, 상기 층간 절연막 상의 배리어 금속막을 식각 정지점으로 상기 층간 절연막 상의 희생층 및 씨드층을 순차적으로 식각한다. 이때, 상기 희생층으로 인하여 트랜치 내의 씨드층이 소모되지 않고 식각시 화학용액과도 반응하지 않아 후의 구리층 형성시 도금 특성이 향상된다. 상기 트랜치 내에 남아 있는 희생층을 제거하여 상기 희생층 및 씨드층의 식각시 발생된 식각 부산물을 제거한다. 상기 트랜치 내에 선택적으로 구리층을 형성한 후, 상기 층간 절연막을 식각 정지점으로 하여 상기 구리층을 식각하여 상기 트랜치 내에 구리 배선층을 형성한다.A copper wiring layer forming method of a semiconductor device is provided. According to the present invention, after forming an interlayer insulating film having a trench on the semiconductor substrate, a barrier metal film and a seed layer are sequentially formed on the entire surface of the semiconductor substrate on which the interlayer insulating film is formed. After the sacrificial layer is formed on the seed layer, the sacrificial layer and the seed layer on the interlayer insulating layer are sequentially etched using the barrier metal layer on the interlayer insulating layer as an etch stop. At this time, due to the sacrificial layer, the seed layer in the trench is not consumed and does not react with the chemical solution during etching, thereby improving the plating property when forming the copper layer. The sacrificial layer remaining in the trench is removed to remove etching by-products generated during the etching of the sacrificial layer and the seed layer. After the copper layer is selectively formed in the trench, the copper layer is etched using the interlayer insulating layer as an etch stop to form a copper wiring layer in the trench.
Description
본 발명은 반도체 소자의 배선층 형성 방법에 관한 것으로, 보다 상세하게는 반도체 소자의 구리 배선층 형성 방법에 관한 것이다.The present invention relates to a method for forming a wiring layer of a semiconductor device, and more particularly, to a method for forming a copper wiring layer for a semiconductor device.
일반적으로, 반도체 소자 중에서 높은 속도가 요구되어지는 로직 소자를 중심으로 해서 RC 지연시간을 줄이기 위해 비저항이 낮은 구리 배선층을 이용하게 되었다. 그런데, 구리 금속의 식각 어려움으로 인하여 콘택홀의 매몰과 배선층을 동시에 형성하는 소위, "다마신(Damascene)" 공정을 이용하여 구리 배선층을 형성한다.In general, a low resistivity copper wiring layer has been used to reduce the RC delay time, particularly in logic devices that require high speed among semiconductor devices. However, due to the difficulty of etching the copper metal, a copper wiring layer is formed by using a so-called “Damascene” process of simultaneously forming a buried contact hole and a wiring layer.
도 1a 내지 도 1f는 다마신 공정을 이용한 종래의 반도체 소자의 구리 배선층 형성방법을 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating a method for forming a copper wiring layer of a conventional semiconductor device using a damascene process.
구체적으로, 반도체 기판(1) 상에 트랜치(3)를 갖는 층간 절연막(5)을 형성한다. 상기 트랜치(3)는 상부폭이 하부 폭보다 작게 형성되어 있으며, 후의 구리 배선층 형성시 원하는 모양에 따라 변경될 수 있다(도 1a 참조). 이어서, 상기 층간 절연막(5)이 형성된 반도체 기판(1)의 전면에 배리어 금속막(7, barrier metal layer)을 형성한다(도 1b 참조).Specifically, the interlayer insulating film 5 having the trench 3 is formed on the semiconductor substrate 1. The trench 3 has an upper width smaller than the lower width, and may be changed according to a desired shape when forming a copper wiring layer later (see FIG. 1A). Subsequently, a barrier metal layer 7 is formed on the entire surface of the semiconductor substrate 1 on which the interlayer insulating film 5 is formed (see FIG. 1B).
다음에, 상기 배리어 금속막(7)이 형성된 반도체 기판의 전면에 씨드층(9)을 형성한다(도 1c 참조). 계속하여, 1차로 화학기계적연마(Chemical Mechanical Polishing, CMP)법으로 상기 층간 절연막(5) 상의 씨드층(9)을 제거한다. 이렇게 되면, 상기 층간 절연막(5) 상의 배리어 금속막(7)은 노출되며, 트랜치(3) 내에는 배리어 금속막(7)과 씨드층 패턴(9a)이 순차적으로 형성된다(도 1d 참조).Next, a seed layer 9 is formed over the entire surface of the semiconductor substrate on which the barrier metal film 7 is formed (see FIG. 1C). Subsequently, the seed layer 9 on the interlayer insulating film 5 is first removed by chemical mechanical polishing (CMP). In this case, the barrier metal film 7 on the interlayer insulating film 5 is exposed, and the barrier metal film 7 and the seed layer pattern 9a are sequentially formed in the trench 3 (see FIG. 1D).
다음에, 상기 씨드층 패턴(9a)이 형성된 결과물 상에 전해 또는 무전해 도금법으로 구리층(11)을 형성하여 상기 트랜치(3)를 매립한다(도 1e 참조). 계속하여, 2차로 화학기계적연마법을 이용하여 구리층(11)을 연마하여 트랜치(3)를 매립하는 구리 배선층(11a)을 형성한다. 이때, 상기 층간 절연막(5) 상에 형성된 배리어 금속막(7)도 연마되어 제거되므로 트랜치(3) 내에만 배리어 금속막 패턴(7a)이 형성된다(도 1f 참조).Next, the trench 3 is filled by forming a copper layer 11 on the resultant on which the seed layer pattern 9a is formed by electrolytic or electroless plating (see FIG. 1E). Subsequently, the copper layer 11 is polished by chemical mechanical polishing in a second manner to form a copper wiring layer 11a filling the trench 3. At this time, the barrier metal film 7 formed on the interlayer insulating film 5 is also polished and removed, so that the barrier metal film pattern 7a is formed only in the trench 3 (see FIG. 1F).
상술한 바와 같은 종래의 반도체 소자의 구리 배선층 형성 방법은 도 1d에 도시한 바와 같이 씨드층(9)의 화학기계적연마시 부산물(10)이 트랜치(3) 내에 남아 있거나 씨드층(9)이 슬러리에 첨가되어 있는 화학용액과 반응하여 도 1e와 같이트랜치(3) 내에 구리층(11)이 완전히 매몰되지 못하는 문제점이 있다. 이렇게 구리층(11)이 트랜치(3) 내에 완전히 매몰되지 못하면 구리층(11) 형성후 2차로 화학기계적연마를 하여도 트랜치(3) 내에 도 1f와 같이 부산물(12)이 남게된다.As described above, in the method of forming a copper wiring layer of a semiconductor device, as shown in FIG. 1D, the by-product 10 in the chemical mechanical polishing of the seed layer 9 remains in the trench 3, or the seed layer 9 is slurry. The copper layer 11 is not completely buried in the trench 3 as shown in FIG. If the copper layer 11 is not completely buried in the trench 3, the by-product 12 remains in the trench 3 as shown in FIG. 1F even if the copper layer 11 is chemically polished after the formation of the copper layer 11.
따라서, 본 발명이 이루고자 하는 기술적 과제는 상술한 문제점을 해결하여 트랜치 내에 구리층을 잘 매립할 수 있는 반도체 소자의 구리 배선층 형성 방법을 제공하는 데 있다.Therefore, the technical problem to be achieved by the present invention is to provide a method for forming a copper wiring layer of a semiconductor device that can solve the above-described problems and to bury the copper layer in the trench well.
도 1a 내지 도 1f는 다마신 공정을 이용한 종래의 반도체 소자의 구리 배선층 형성방법을 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating a method for forming a copper wiring layer of a conventional semiconductor device using a damascene process.
도 2a 내지 도 2h는 다마신 공정을 이용한 본 발명의 반도체 소자의 구리 배선층 형성방법을 도시한 단면도들이다.2A to 2H are cross-sectional views illustrating a method for forming a copper wiring layer of a semiconductor device of the present invention using a damascene process.
상기 기술적 과제를 달성하기 위하여, 본 발명은 반도체 기판 상에 트랜치를 갖는 층간 절연막을 형성한 후, 상기 층간 절연막이 형성된 반도체 기판의 전면에 배리어 금속막과 씨드층을 순차적으로 형성한다. 상기 씨드층 상에 희생층을 형성한 후, 상기 층간 절연막 상의 배리어 금속막을 식각 정지점으로 상기 층간 절연막 상의 희생층 및 씨드층을 순차적으로 식각한다. 이때, 상기 희생층으로 인하여 트랜치 내의 씨드층이 소모되지 않고 식각시 화학용액과도 반응하지 않아 후의 구리층 형성시 도금 특성이 향상된다. 상기 트랜치 내에 남아 있는 희생층을 제거하여 상기 희생층 및 씨드층의 식각시 발생된 식각 부산물을 제거한다. 상기 트랜치 내에 선택적으로 구리층을 형성한 후, 상기 층간 절연막을 식각 정지점으로 하여 상기 구리층을 식각하여 상기 트랜치 내에 구리 배선층을 형성한다.In order to achieve the above technical problem, the present invention forms an interlayer insulating film having a trench on a semiconductor substrate, and then sequentially forms a barrier metal film and a seed layer on the entire surface of the semiconductor substrate on which the interlayer insulating film is formed. After the sacrificial layer is formed on the seed layer, the sacrificial layer and the seed layer on the interlayer insulating layer are sequentially etched using the barrier metal layer on the interlayer insulating layer as an etch stop. At this time, due to the sacrificial layer, the seed layer in the trench is not consumed and does not react with the chemical solution during etching, thereby improving the plating property when forming the copper layer. The sacrificial layer remaining in the trench is removed to remove etching by-products generated during the etching of the sacrificial layer and the seed layer. After the copper layer is selectively formed in the trench, the copper layer is etched using the interlayer insulating layer as an etch stop to form a copper wiring layer in the trench.
이하, 첨부 도면을 참조하여 본 발명의 실시예들을 상세히 설명한다. 그러나, 다음에 예시하는 본 발명의 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예들에 한정되는 것은 아니다. 본 발명의 실시예들은 당 업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되어지는 것이다. 도면에서 막 또는 영역들의 크기 또는 두께는 명세서의 명확성을 위하여 과장되어진 것이다. 또한, 어떤 막이 다른 막 또는 기판의 "위(상)"에 있다라고 기재된 경우, 상기 어떤 막이 상기 다른 막의 위에 직접 존재할 수도 있고, 그 사이에 제3의 다른 막이 개재될 수도 있다.Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; However, embodiments of the present invention illustrated below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the size or thickness of films or regions is exaggerated for clarity. In addition, when a film is described as "on" another film or substrate, the film may be directly on top of the other film, and a third other film may be interposed therebetween.
도 2a 내지 도 2h는 다마신 공정을 이용한 본 발명의 반도체 소자의 구리 배선층 형성방법을 도시한 단면도들이다. 도 2a 내지 도 2h는 이중 다마신 공정을 이용하여 설명하고 있으나, 단일 다마신 공정에도 적용할 수 있다.2A to 2H are cross-sectional views illustrating a method for forming a copper wiring layer of a semiconductor device of the present invention using a damascene process. 2A to 2H are described using a dual damascene process, but may also be applied to a single damascene process.
도 2a를 참조하면, 반도체 기판(21) 상에 트랜치(23)를 갖는 층간 절연막(25)을 형성한다. 상기 트랜치(23)는 사진식각공정을 이용하여 형성한다. 상기 트랜치(23)은 상부폭이 하부 폭보다 작게 형성하며, 후의 구리 배선층 형성 모양에 따라 변경될 수 있다. 본 실시예서는 상기 트랜치(23)의 깊이는 1000∼30,000Å의 범위로 형성한다.Referring to FIG. 2A, an interlayer insulating layer 25 having trenches 23 is formed on the semiconductor substrate 21. The trench 23 is formed using a photolithography process. The trench 23 has an upper width smaller than the lower width, and may be changed according to the shape of the copper wiring layer formed later. In the present embodiment, the depth of the trench 23 is formed in the range of 1000 to 30,000 Å.
도 2b를 참조하면, 상기 층간 절연막(25)이 형성된 반도체 기판(21)의 전면에 배리어 금속막(27, barrier metal layer)을 형성한다. 상기 배리어 금속막(27)은 후의 구리 배선층의 형성시 접촉성(adhesion)을 좋게 하고 구리 배선층의 구리가 층간절연막(25)으로 확산하는 것을 방지하기 위하여 형성한다. 상기 배리어 금속막(27)은 Ta, TaN, TaAlN, TaSiN, TaSi2, Ti, TiN, TiSiN, WN, Co, CoSi2또는 이들간의 조합으로 된 복합층을 이용하여 형성한다. 본 실시예에서, 상기 배리어 금속막(27)은 100∼2000Å의 두께로 형성한다.Referring to FIG. 2B, a barrier metal layer 27 is formed on the entire surface of the semiconductor substrate 21 on which the interlayer insulating layer 25 is formed. The barrier metal film 27 is formed in order to improve the adhesion during the formation of the subsequent copper wiring layer and to prevent the copper of the copper wiring layer from diffusing into the interlayer insulating film 25. The barrier metal film 27 is formed using a composite layer made of Ta, TaN, TaAlN, TaSiN, TaSi 2 , Ti, TiN, TiSiN, WN, Co, CoSi 2 or a combination thereof. In the present embodiment, the barrier metal film 27 is formed to a thickness of 100 to 2000 kPa.
도 2c를 참조하면, 상기 배리어 금속막(27)이 형성된 반도체 기판(21)의 전면에 씨드층(29)을 형성한다. 상기 씨드층(29)은 후에 형성되는 구리 배선층을 균일하게 형성하기 위하여 형성한다. 상기 씨드층(29)은 물리적화학증착법, 예컨대 스퍼터링법이나 화학기상증착법을 이용하여 구리층으로 100∼5000Å의 두께로 형성한다. 상기 씨드층(29)는 구리층 이외에 Pt(platinum)층, Pd(palladium)층, Ru(rubidium)층, St(strontium)층, Rh(rhodium)층, Co(cobalt)층 등의 전이 금속층을 사용할 수도 있다.Referring to FIG. 2C, the seed layer 29 is formed on the entire surface of the semiconductor substrate 21 on which the barrier metal layer 27 is formed. The seed layer 29 is formed to uniformly form a copper wiring layer to be formed later. The seed layer 29 is formed to a thickness of 100 to 5000 kPa of the copper layer by physical chemical vapor deposition, for example, sputtering or chemical vapor deposition. The seed layer 29 may include a transition metal layer such as a Pt (platinum) layer, a Pd (palladium) layer, a Ru (rubidium) layer, a St (strontium) layer, a Rh (rhodium) layer, and a Co (cobalt) layer in addition to the copper layer. Can also be used.
도 2d를 참조하면, 상기 씨드층(29) 상에 희생층(31)을 10∼10,000Å의 두께로 형성한다. 상기 희생층(31)은 금속막이나 금속막이 아닌 비금속막을 이용하여 형성한다. 상기 희생층용 금속막의 예로는 알루미늄(Al)막, 타이타늄(Ti)막, 타이타늄질화(TiN)막, 텅스텐(W)막 등을 들 수 있고, 희생층용 비금속막의 예로는 BPSG(boron-phosporous-silicate glass)막, USG(undoped silicate glass)막, PE-TEOS(plasma enhanced tetra-ethyl-ortho-silicate)막, HTO(high temperature oxide)막, SiN막, SiON막, 폴리실리콘막, SOG(silion on glass)막, 유동성 산화막 등을 들 수 있다. 특히, 상기 희생층으로는 Ti막이나 PE-TEOS막을 사용하는 것이 바람직하다.Referring to FIG. 2D, a sacrificial layer 31 is formed on the seed layer 29 to a thickness of 10 to 10,000 Å. The sacrificial layer 31 is formed using a non-metal film instead of a metal film or a metal film. Examples of the metal layer for the sacrificial layer include an aluminum (Al) film, a titanium (Ti) film, a titanium nitride (TiN) film, a tungsten (W) film, and the like, and an example of the non-metal film for the sacrificial layer is boron-phosporous-silicate. glass (USG) film, USG (undoped silicate glass) film, plasma enhanced tetra-ethyl-ortho-silicate (PE-TEOS) film, high temperature oxide (HTO) film, SiN film, SiON film, polysilicon film, silicon on SOG glass) films, fluidized oxide films, and the like. In particular, it is preferable to use a Ti film or a PE-TEOS film as the sacrificial layer.
도 2e를 참조하면, 1차로 화학기계적연마(Chemical Mechanical Polishing, CMP)법을 이용하고, 상기 층간 절연막(25) 상의 배리어 금속막(27)을 식각 정지점으로 하여 상기 층간 절연막(25) 상의 희생층(31) 및 씨드층(29)을 순차적으로 식각한다. 상기 1차 화학기계적연마시 상기 배리어 금속막(27)이 상기 씨드층(29)에 대하여 잘 갈리지 않는 슬러리로써, 연마 입자가 없는 슬러리를 사용하는 것이 바람직하다. 이렇게 되면, 상기 층간 절연막(25) 상의 배리어 금속막(27)은 노출되며, 트랜치(23) 내에는 배리어 금속막(27), 씨드층 패턴(29a) 및 희생층 패턴(31a)이 순차적으로 피복된 구조가 된다.Referring to FIG. 2E, a sacrificial material on the interlayer insulating layer 25 is first used by using a chemical mechanical polishing (CMP) method, using the barrier metal layer 27 on the interlayer insulating layer 25 as an etch stop. The layer 31 and the seed layer 29 are sequentially etched. It is preferable to use a slurry free of abrasive particles as the slurry in which the barrier metal film 27 is hardly divided with respect to the seed layer 29 during the primary chemical mechanical polishing. In this case, the barrier metal layer 27 on the interlayer insulating layer 25 is exposed, and the barrier metal layer 27, the seed layer pattern 29a, and the sacrificial layer pattern 31a are sequentially covered in the trench 23. It becomes the structure which became.
그런데, 본 발명은 종래와 비교하여 상기 1차로 화학기계적 연마시 상기 트랜치(23) 내의 씨드층(29)은 상기 희생층(31)으로 인하여 소모되지 않고 슬러리에 첨가되어 있는 화학용액과도 반응하지 않아 후에 전해 또는 무전해 도금에 의한 구리층 형성시 도금 특성을 크게 향상시킬 수 있다.However, in the present invention, the seed layer 29 in the trench 23 is not consumed due to the sacrificial layer 31 and does not react with the chemical solution added to the slurry during chemical mechanical polishing. Therefore, it is possible to greatly improve the plating characteristics when forming a copper layer by electrolytic or electroless plating.
도 2f를 참조하면, 습식 식각공정을 이용하여 트랜치(23)의 측벽 및 바닥에 형성되어 있는 상기 희생층 패턴(31a)를 제거한다. 이때, 상기 희생층 패턴(31a)만을 선택적으로 식각할 수 있는 화학용액을 이용한다. 이렇게 트랜치(23)의 측벽 및 바닥에 형성된 희생층 패턴(31a)을 제거해줌으로써 상기 1차로 화학기계적연마시 트랜치(23) 내에 남았는 부산물들을 모두 제거할 수 있어 후속의 전해 또는 무전해 도금시 도금 특성을 크게 향상시킬 수 있다.Referring to FIG. 2F, the sacrificial layer pattern 31a formed on the sidewalls and the bottom of the trench 23 is removed using a wet etching process. In this case, a chemical solution capable of selectively etching only the sacrificial layer pattern 31a is used. By removing the sacrificial layer pattern 31a formed on the sidewalls and the bottom of the trench 23, all of the by-products remaining in the trench 23 during the first chemical mechanical polishing can be removed so that the plating characteristics during subsequent electrolytic or electroless plating Can greatly improve.
도 2g를 참조하면, 전해 또는 무전해 도금법으로 상기 씨드층 패턴(29a) 상에 선택적으로 구리층(33)을 형성하여 상기 트랜치(23)를 매립한다. 특히, 상기 구리층(33)은 씨드층 패턴(29a)이 남아있는 트랜치(23) 내에서만 선택적으로 형성된다.Referring to FIG. 2G, the trench 23 is buried by selectively forming a copper layer 33 on the seed layer pattern 29a by electrolytic or electroless plating. In particular, the copper layer 33 is selectively formed only in the trench 23 in which the seed layer pattern 29a remains.
도 2i를 참조하면, 2차로 화학기계적연마법을 이용하고 상기 층간절연막(25)을 식각 정지점으로 상기 구리층(33)을 식각함으로써 트랜치(23)를 매립하는 구리 배선층(33a)을 형성한다. 이때, 상기 층간 절연막(25) 상에 형성된 배리어 금속막(27)도 연마되어 제거되므로 트랜치 내에만 배리어 금속막 패턴(27a)이 형성된다. 상기 2차 화학기계적 연마시 배리어 금속막(27)과 구리층(33)의 연마 속도가 동일한 슬러리를 사용하는 것이 바람직하다.Referring to FIG. 2I, a copper wiring layer 33a filling a trench 23 is formed by using a chemical mechanical polishing method and etching the copper layer 33 using the interlayer insulating layer 25 as an etch stop. . At this time, since the barrier metal film 27 formed on the interlayer insulating film 25 is also polished and removed, the barrier metal film pattern 27a is formed only in the trench. In the second chemical mechanical polishing, it is preferable to use a slurry having the same polishing rate as that of the barrier metal film 27 and the copper layer 33.
상술한 바와 같이 본 발명의 반도체 소자의 구리 배선층 형성 방법에 의하면, 씨드층 상에 희생층을 형성하여 1차로 화학기계적 연마시 상기 트랜치 내의 씨드층은 소모되지 않고 슬러리에 첨가되어 있는 화학용액과도 반응하지 않아 도금 특성을 크게 향상시킬 수 있다.As described above, according to the method for forming a copper wiring layer of the semiconductor device of the present invention, when the sacrificial layer is formed on the seed layer and the chemical mechanical polishing is performed first, the seed layer in the trench is not consumed but is also added to the chemical solution added to the slurry. Since it does not react, plating property can be improved significantly.
그리고, 본 발명의 반도체 소자의 구리 배선층 형성 방법에 의하면, 트랜치의 측벽 및 바닥에 형성된 희생층 패턴을 제거해줌으로써 상기 1차로 화학기계적연막시 트랜치 내에 남았는 부산물을 모두 제거할 수 있어 도금 특성을 크게 향상시킬 수 있다.In addition, according to the method for forming a copper wiring layer of the semiconductor device of the present invention, by removing the sacrificial layer patterns formed on the sidewalls and the bottom of the trench, all by-products remaining in the trench during the first chemical mechanical vapor deposition can be removed, thereby greatly improving plating characteristics. You can.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020000039989A KR20020006362A (en) | 2000-07-12 | 2000-07-12 | Method for forming a copper wiring layer in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020000039989A KR20020006362A (en) | 2000-07-12 | 2000-07-12 | Method for forming a copper wiring layer in semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100403197B1 (en) * | 2001-06-21 | 2003-10-23 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR20040009789A (en) * | 2002-07-25 | 2004-01-31 | 아남반도체 주식회사 | Semiconductor device and fabrication method thereof |
| KR100467494B1 (en) * | 2002-06-17 | 2005-01-24 | 동부전자 주식회사 | Method for forming copper electrodeposition film within metal wire contact hole |
| US10332791B2 (en) | 2016-12-02 | 2019-06-25 | Samsung Electronics Co., Ltd. | Semiconductor device with a conductive liner |
-
2000
- 2000-07-12 KR KR1020000039989A patent/KR20020006362A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100403197B1 (en) * | 2001-06-21 | 2003-10-23 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR100467494B1 (en) * | 2002-06-17 | 2005-01-24 | 동부전자 주식회사 | Method for forming copper electrodeposition film within metal wire contact hole |
| KR20040009789A (en) * | 2002-07-25 | 2004-01-31 | 아남반도체 주식회사 | Semiconductor device and fabrication method thereof |
| US10332791B2 (en) | 2016-12-02 | 2019-06-25 | Samsung Electronics Co., Ltd. | Semiconductor device with a conductive liner |
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