KR20020004798A - Apparatus and method for data processing using multiply-accumulate instructions - Google Patents

Abstract

PURPOSE: A device and a method for data processing are provided to detect overflow and to perform a multiplication accumulation instruction. CONSTITUTION: The dedicated and general register banks of an N-bit data processing register, a selector, a multiplier and an accumulator are provided or used. The selector is connected to the dedicated and general register banks and selects either of the register banks and the selected register bank outputs N-bit results. The N-bit results and N-bit data held by the general register bank form a 2N-bit additional operand. The multiplier performs a multiplication operation about the first and second operands and outputs 2N-bit results. The accumulator is connected to the multiplier, selector and general register bank, performs an accumulation operation about the 2N-bit results and the 2N-bit additional operand and outputs 2N-bit accumulation results.

Description

Apparatus and method for processing data using multiply accumulate instructions {APPARATUS AND METHOD FOR DATA PROCESSING USING MULTIPLY-ACCUMULATE INSTRUCTIONS}

The present invention relates to an apparatus and method for a data processing system. More specifically, the present invention relates to an apparatus and method for a data processing system using a multiply accumulate instruction. Data processing systems can easily detect overflow conditions and can simplify execution and shorten execution time.

In the field of data processing, it is necessary to be able to perform certain operations with operands stored in various data registers. One such operation is to multiply the first N bit operand with the second N bit operand and add the third N bit operand to the result. Another similar operation is to multiply the first N bit operand by the second N bit operand and add the 2N bit operand to the result.

1 is a block diagram illustrating a conventional multiplication accumulator for a data processing system of US Pat. No. 5,583,804, entitled "DATA PROCESSING USING MULTIPLY-ACCUMULATE INSTRUCTIONS." The system performs a first class of multiply accumulate instructions in the form of N * N + 2N → 2N, and performs a second class of multiply accumulate instructions in the form of N * N + N → N.

The multiply accumulator includes a first data register 10, a second data register 20, an N * N multiplier 30, an N + N accumulator 40, and a 2N + 2N accumulator 50. The multiplier 30 may calculate N * N to obtain a result value of N or 2N. The N + N accumulator 40 may calculate N + N to obtain a result of N. The 2N + 2N accumulator 50 may calculate 2N + 2N to obtain a result value of 2N.

However, when performing operations with N * N + N → N class instructions, the last N result may be larger than what can be represented within the N bit size. When this happens, it is important for the user to realize that an overflow condition has occurred in the operation. The drawback of the multiply accumulator of Figure 1 is that it does not indicate this overflow condition. Providing this important information to the user in a way as efficient as possible is one of the reasons why the multiplication accumulator of the present invention has been developed.

It is therefore an object of the present invention to provide a data processing system comprising a single accumulator capable of detecting overflow conditions and performing multiply accumulate instructions. Thus, system configuration is simplified and provides useful overflow information. Data processing systems can easily detect overflow conditions and simplify execution to reduce execution time.

1 is a block diagram illustrating a conventional multiply accumulator for a data processing system.

2 is a block diagram illustrating a multiply accumulator for a data processing system according to the present invention.

In order to achieve the above and other advantages according to the object of the present invention, the present invention embodied and broadly described herein comprises a first register bank consisting of N bit data processing registers, a first consisting of N bit data processing registers. A data processing device including two register banks, a selector, a multiplier, and an accumulator is provided. The selector is connected with the first register bank and the second register bank, and is used to select one of the first and second register banks to output N bit data from the selected register bank. The output N bit data and the N bit data held in the second register bank form a 2N bit addition operand. The multiplier performs a multiplication operation with the first operand and the second operand and outputs a 2N bit multiplication result. An accumulator is connected to a multiplier, a selector, and a second register bank, and performs an accumulate operation with a 2N bit multiplication result and a 2N bit addition operand to output a 2N bit accumulate result.

In a data processing apparatus, a selector additionally used to receive a class signal selects one of the first and second register banks in response to a signal in the class.

The class signal of the data processing device is used to indicate a first class command or a second class command.

The data processing device further includes a detection device connected to the accumulator to receive the 2N bit accumulated result value and check whether an overflow condition occurs.

In the data processing apparatus, the N bit data output from the selector and the N bit data held in the second register bank are formed by combining the first N bit portion and the second N bit portion of the 2N bit add operand, and the class signal is If the signal is a second class instruction, the accumulation result value includes a third N bit portion and a fourth N bit portion, and the detection apparatus includes a first N bit portion of the 2N bit addition operand and a third N bit portion of the accumulation result value. Compare to to determine if an overflow condition occurs.

In order to achieve the above and other advantages according to the present invention, the present invention embodied and broadly described herein comprises a first register bank consisting of N bit data processing registers, a second register bank consisting of N bit data processing registers, A data processing method using a device having a selector, a multiplier, and an accumulator is provided, wherein the method selects one of the first and second register banks, and selects N bit data from the selected register bank—the N bit data and the second output therein. Outputting the N bit data held in the register bank forms a 2N bit addition operand; Performing a multiplication operation with the first operand and the second operand and outputting a 2N bit multiplication result value; Performing an accumulation operation with a 2N bit multiplication result and a 2N bit addition operand, and outputting a 2N bit accumulation result.

In the data processing method, selecting one of the first and second register banks and outputting N-bit data from the selected register bank further includes receiving a class signal and by means of a class signal received by the selector. The selection of the register bank is determined.

The class signal is used to indicate a first class command or a second class command.

The data processing method further includes receiving a 2N bit accumulation result value and checking whether an overflow condition occurs.

In the data processing method, the N bit data output from the selector and the N bit data held in the second register bank are formed by combining the first N bit portion and the second N bit portion of the 2N bit add operand, and the class signal. Is the second class instruction, the accumulating result value includes a third N bit portion and a fourth N bit portion, and compares the first N bit portion of the 2N bit addition operand with the third N bit portion of the accumulation result value. Determine if a flow condition occurs.

The foregoing general description and the detailed description below are both exemplary and are intended to provide further explanation of the invention in the claims.

Example

Reference numerals will be embodied in a preferred embodiment of the invention, embodiments of the invention are described in the accompanying drawings. The same reference numerals are used in the descriptions to refer to the same or similar parts as the drawings.

Referring to FIG. 2, FIG. 2 is a block diagram illustrating a multiply accumulator 200 of a data processing system in accordance with the present invention. The multiply accumulator 200 includes a selector 160, a multiplier 130, and an accumulator 150. Special register bank 110 and general purpose register bank 120 provide data. The multiplier 130 is connected to the accumulator 150. Special register bank 110 and general purpose register bank 120 are coupled to selector 160. The selector 160 is connected to the accumulator 150. General purpose register bank 120 is also directly connected to accumulator 150. The multiply accumulator 200 further includes a detector 170 coupled with the accumulator 150.

The multiplier 130 may multiply two N bit operands, and then output a 2N bit multiplication result 134. For example, N * N outputs a 2N result. As shown in FIG. 2, the first N bit operand denoted E and the second N bit operand denoted F are input to the multiplier 130. The multiplier 130 outputs a 2N bit result value 134. The 2N bit multiplication result 134 from multiplier 130 is sent to accumulator 150 and added with the add operand. The addition operand is also 2N bits including the first N bit portion and the second N bit portion. In the present invention only one accumulator is needed to make more favorable calculations. For example, if the prior art wants two calculations, such as N * N + N → N and N * N + 2N → 2N, then at least two accumulators are needed for this desired calculation. In the configuration of the present invention, only one accumulator is required for the two calculations. The circuit shown in FIG. 2 can implement this feature.

In the present invention, the class signal 100 is provided to the selector 160 to indicate one of two different class commands. The class signal 100 indicates which class command is performed. For example, a first class command such as N * N + 2N → 2N or a second class command such as N * N + N → N. The class signal is set by a decoding instruction provided to the multiply accumulator 200. The first class instruction requires more execution time and a more precise result is output from the first class instruction. The second class instruction requires less execution time than the first class instruction.

If the class instruction is a first class instruction, i.e., the desired calculation is N * N + 2N → 2N, the class signal 100 causes the selector 160 to provide data from the general purpose register bank 120 to the accumulator 150. do. In other words, the 2N bits of the addition signal 152 include (N, N). The first N bit portion of the addition signal 152 is denoted C and the second N bit portion is denoted D. The first N bit portion C is provided by the general purpose register bank 120. As shown in FIG. 2, the second N bit portion D is also provided by the general purpose register bank 120.

If the class command is a second class, N * N + N → N, the class signal 100 causes the selector 160 to provide data from the special register bank 110 to the accumulator 150. That is, special register bank 110 provides the first N bit portion C of add operand 152. The user can access the special register bank 110 by software control. The second N bit portion D is provided by the general purpose register bank 120. In the multiply accumulator 200 of the preferred embodiment of the present invention, the accumulator 150 has 2N bits (although the calculation of N * N + N → N only needs to add N bit data to output the N bit accumulate result). 152) is added to output a 2N bit result value. The configuration of the present invention provides several advantages. For example, this design easily detects overflow conditions. It describes in detail below. Another advantage is to simplify some calculations to shorten execution time. E.g X _k Y _k = X ₀ Y ₀ + X ₁ Y ₁ +... If a calculation such as X _n Y _n is desired, the comparison between the preferred embodiment and the prior art is as follows.

In the prior art, the programming language is

for (k = 0; k≥n; k ++) {

Move X _k to R ₀

Move Y _k to R ₁

R ₂ = R ₀ * R ₁ + R ₂ ; MLA R ₂ , R ₀ , R ₁ , R ₂

k = k + 1

}

Where "MLA" is a command for N * N + N → N and the result after executing the "MLA" command is 32 bits long.

In a preferred embodiment, the programming language is

for (k = 0; k≥n; k ++) {

Move X _k to R ₀

Move Y _k to R ₁

(R _CP , R ₂₎ = R ₀ * R ₁ + (R _CP , R ₂ ); MLA R ₂ , R ₀ , R ₁ , R ₂

k = k + 1

}

Where "MLA" is a command for N * N + N → N, and the result value after executing the "MLA" command in the program of the present invention is 64 bits long.

The accumulated result is 64 bits in the preferred embodiment of the present invention and 32 bits in the prior art. If a 64-bit result is desired in the prior art, a calculation of N * N + 2N → 2N is required, which requires more execution time than the embodiment of the present invention. In other words, the simplified calculation in the present invention requires the same execution time as the prior art.

After accumulation, the accumulator 150 outputs an accumulation result value 154. Accumulation result 154 is 2N bits and includes a first N bit portion H and a second N bit portion I. The accumulation result value 154 is an output result value of the multiplication accumulator 200. The accumulated result value 154 is also output to the detection device 170 to detect the overflow condition indicated by the detection result value 172.

If the class instruction wants to calculate a second class, that is, N * N + N → N, the detection device 170 provides the first N bit portion H of the accumulation result value 154 and the special register bank 110 to provide. The first N bit portions C of the addition operand 152 are compared. If the first N-bit portion H of the accumulation result value 154 is not the same as the first N-bit portion C of the add operand 152, it means that an overflow condition has occurred in the calculation.

For clarity, the two N bit operands input to the multiplier 130 are denoted E and F , respectively. The calculation of N * N + N → N commands can be executed by E * F + CD → HI according to the present invention. This case where C is not equal to H means that an overflow occurs. N * N + 2N → 2N instruction calculations can also be executed from E * F + CD → HI by the same configuration of the present invention.

For N * N + 2N → 2N class instructions, the accumulator adds CD to the result of the E * F multiplication operation and outputs the accumulated result HI . The accumulator performs only one type of calculation, 2N + 2N → 2N. For N * N + N → N class instructions, the accumulator outputs the HI result by adding CD to the result of the E * F multiplication operation. In this case C is provided by special register bank 110. If the addition operand H is not equal to C , an overflow has occurred.

While the multiply accumulator of FIG. 1 does not provide the overflow indication, the overflow indicator provides useful information quickly and conveniently to the user. This is another advantage of the present invention.

It will be apparent to those skilled in the art that numerous modifications can be made to the invention without departing from the spirit and scope of the invention. In view of the foregoing, it is intended that the present invention include modifications within the scope of the appended claims and equivalents.

As described above, the present invention can easily detect an overflow condition in a data system using a multiply accumulate instruction. It also simplifies calculations and shortens execution time.

Claims (16)

A special register bank consisting of N bit data processing registers; A general purpose register bank composed of N bit data processing registers; N bit result value selected from a special and general purpose register bank and selected from the selected register bank, wherein the N bit result value and the N bit data form a 2N bit addition operand. Output selector; A multiplier for performing a multiplication operation with the first operand and the second operand and outputting a 2N bit multiplication result value; An accumulator connected to a multiplier, a selector, and a general purpose register bank and performing an accumulate operation with a 2N bit multiply result and a 2N bit add operand to output a 2N bit accumulator result. Data processing device comprising a. The method of claim 1, And said N bit data is held in a general purpose register bank. The method of claim 1, And the selector further receives a class signal and selects one of the special and general purpose register banks in response to the class signal. The method of claim 3, The class signal is used to indicate a first class command or a second class command, the first class command performs a first calculation of N * N + 2N → 2N and the second class command is N * N + N → A data processing device that performs a second calculation of N. The method of claim 4, wherein And a detection device coupled to the accumulator and inspecting whether an overflow condition occurs by receiving a 2N bit accumulation result value. The method of claim 5, The N bit result value output from the selector and the N bit data held in the general purpose register bank combine to form a first N bit portion and a second N bit portion of the 2N bit add operand, The accumulation result value includes a third N bit portion and a fourth N bit portion, If the class signal is a second class instruction, the detection device compares the first N bit portion of the 2N bit add operand with the third N bit portion of the accumulation result value to determine whether an overflow condition occurs. Device. The method of claim 1, And a detection device coupled to the accumulator and inspecting whether an overflow condition occurs by receiving a 2N bit accumulation result value. The method of claim 7, wherein The N bit result value output from the selector and the N bit data combine to form a first N bit portion and a second N bit portion of the 2N bit add operand, The accumulation result value includes a third N bit portion and a fourth N bit portion, If the class signal is a second class instruction, the detection device compares the first N bit portion of the second N bit add operand with the third N bit portion of the accumulation result value to determine whether an overflow condition occurs. Device. A data processing method using a device having a special register bank composed of N bit data processing registers, a general purpose register bank composed of N bit data processing registers, a selector, a multiplier, and an accumulator, Selecting one of the special and general purpose register banks and outputting an N bit result value from the selected register bank, wherein the N bit result value and the N bit data form a 2N bit addition operand; Performing a multiplication operation with the first operand and the second operand to output a 2N bit multiplication result value; Performing an accumulation operation with a 2N bit multiplication result and a 2N bit addition operand, and outputting a 2N bit accumulation result Data processing method comprising a. The method of claim 9, And said N bit data is held in said general register bank. The method of claim 10, Selecting one of the special and general purpose register banks and outputting N bit data from the selected register bank further comprises receiving a class signal, wherein the selection of the register bank is determined by the class signal received by the selector. How data is processed. The method of claim 11, The class signal is used to indicate a first class command or a second class command, wherein the first class command performs a first calculation of N * N + 2N → 2N and the second class command performs N * N + N → A data processing method for performing a second calculation of N. The method of claim 12, Receiving a 2N bit accumulation result value and checking whether an overflow condition occurs. The method of claim 13, The N bit result value output from the selector and the N bit data held in the general purpose register bank combine to form a first N bit portion and a second N bit portion of the 2N bit add operand, The accumulation result value includes a third N bit portion and a fourth N bit portion, And when the class signal is a second class instruction, the detection device compares the first N bit portion of the 2N bit add operand with the third N bit portion of the accumulation result value to determine whether an overflow condition occurs. . The method of claim 9, Receiving a 2N bit accumulation result value and checking whether an overflow condition occurs. The method of claim 15, The N bit result value output from the selector and the N bit data held in a general purpose register bank combine to form a first N bit portion and a second N bit portion of the 2N bit add operand, The accumulation result value includes a third N bit portion and a fourth N bit portion, If the class signal is a second class instruction, the detection device compares the first N bit portion of the 2N bit add operand with the third N bit portion of the accumulation result value to determine whether an overflow condition occurs. Way.