KR20010072118A - Video conferencing interface - Google Patents

Abstract

The video conferencing circuit 12 according to the invention is configured to receive an input 26 from one of a plurality of video input devices. The video signal is then stored, compressed and transmitted by an interface circuit such as modem 18. Video signals from the remote location are received from the modem 18, decompressed, stored, and then transmitted for display on one of the plurality of video output devices.

Description

Video conferencing interface

Video conferencing systems typically include NTSC cameras ("NTSC" refers to North American and Japanese analog video standards), PAL cameras ("PAL" refers to European analog video standards), digital cameras, or high-speed serial interface cameras (eg Is designed for use with one particular type of video input device, such as a FireWire or Universal Serial Bus (USB) camera. In addition, such systems are typically designed for use with one particular output device, such as an NTSC or PAL video monitor, television receiver, liquid crystal display (LCD) screen, or computer monitor.

Rather than required, systems that have interfaces for a video conferencing system in which users or manufacturers of such systems mix video input / output devices of their choice or indicate a particular video conferencing application are not known. That is, it is believed that existing systems require a specific video input device and a specific output device indicated by the official video signal to the selected video conferencing system.

This application claims the benefit of US Provisional Patent Application No. 60 / 094,646, filed July 30, 1998.

The present invention relates to a video conferencing system, and more particularly to a system for interfacing with at least one of a plurality of video input devices and at least one of a plurality of output devices.

1 is a block explanatory diagram of a basic ASIC of the prior art suitable for use in video signal processing.

2 is a block diagram of an ASIC suitable for use with one type of video system of the present invention.

3 is a block diagram of an ASIC suitable for use with another type of video system of the present invention.

4 is a block diagram of a high speed serial interface circuit for use with the video system of the present invention.

5 is a block diagram of a video input block of an ASIC used with the video system of the present invention.

6 is a block diagram of a bus control block of an ASIC used with the video system of the present invention.

7 is a block diagram of a video output block of an ASIC used with the video system of the present invention.

The video conferencing interface of the present invention is part of a standard video conferencing system with excellent video and audio quality, high compression and great flexibility at low cost. This interface includes application specific integrated circuits (ASICs) that incorporate a unique blend of computational and data path designs implemented in hardware as well as processing and control circuits developed for flexibility using standard processors.

The "hybrid" method of computation and control that can be used in the disclosed system provides an advantage over the counterparts of "single solution" where computation and control are implemented only in dedicated hardware. The use of dedicated hardware only leads to relative inflexibility in bit rate control. The "hybrid" method of computation and control in the disclosed system offers advantages over corresponding methods using only software-programmed processors, thus giving up the speed advantage of hardware implementation.

The disclosed system uses hardware to implement and provide data paths and operations to provide high speed data processing at much faster rates than can be performed in a processor-only environment (ie, software). Standard software-based processors can be manufactured to allow the system to adapt to a variety of different configurations by allowing for flexibility of control. However, the result is a slower speed due to the software configuration. In order to achieve higher speeds using hardware, a separate hardware configuration is often required for each necessary change, which incurs significant cost and complexity for implementation.

For example, it is often desirable to control the bit rate at which the system interface processes the image so that a suitable balance can be made between the quality of the image being processed on the one hand and the speed at which the image is processed on the other hand. For example, when high speed operation occurs in a processed image, it is typically desirable to operate at an increased bit rate such that the high speed operation is processed and communicated quickly. However, high speed processing has a negative effect on image quality. When the image to be processed is relatively static from image to image (e.g., frame to frame), it is typically desirable to operate at reduced bit rates, but at increased image quality. In hardware-only implementations, such flexibility must be wired at higher costs or simply cannot be used. In software-only implementations, flexibility is however maintained at the expense of reduced processing speed. The present invention uses a "hybrid" approach not known so far to ensure the benefit of fixed hardware and fixed software solutions.

In the disclosed embodiment of the present invention, the ASIC is the key to implementing this hybrid approach. ASICs provide hardwired execution for computation and data movement while providing inherent flexibility for processor-based processing and control.

In addition to the ASIC, the system incorporates memory for storing video information as it is compressed and / or displayed. The system also includes a processor, memory for command and data storage for audio inputs and outputs and an electrically erasable programmable read only memory (EEPROM), and a modulator / demodulator (MODEM) for a telephone / network interface. (EEPROM and MODEM are virtually arbitrary based on high performance requirements.)

ASICs also include a variety of interfaces that are flexible in their ability to allow a variety of different system configurations with minimal variation or cost impact. These interfaces include video inputs, video outputs, and high speed serial interfaces.

Best Mode of Invention

As shown in FIG. 1, a conventional ASIC 10 may be included on a circuit board 12. The circuit board 12 includes a memory 14 connected to a memory control circuit 30 forming a memory module 15 that functions to hold video signals. Memory 14 may be implemented as dynamic random access memory (DRAM), static random access memory (SCRAM), or other suitable memory device structure known to those skilled in the art.

Circuit board 12 may have any EEPROM module 16. An audio input / output (I / O) module 20 (e.g., connected to a microphone or speaker) that functions together as a remote video interface circuit 19, and a MODEM and / or network interface (e.g., a LAN or local area network interface) A separate processor memory module (eg, SCRAM, DRAM, etc.) may be included on the circuit board 12.

In one operational configuration, video-in circuitry 24 receives digital video signals 26 from a single or selected video signal source. "I-L263" is a video compression / decompression standard established by the International Telecommunications Association (ITU). The H.263 encode circuit 34 directs the memory control circuit 30 towards the stored digital video data transmitted from the video memory module 15 to it. The memory control circuit 30 transmits the stored video data that it receives along with it on the memory bus 32. As the H.263 encode circuit 34 encodes (i.e., compresses) the stored digital video data, it is displayed at a remote station (shown at a location where the digital video data can be decoded and subsequently displayed for user viewing. Pass the currently encoded digital video data to the MODEM or network module 22 for transmission. The remote station may include the advanced video conferencing interface disclosed herein or may be a conventional video conferencing system interface.

The encoded digital video data is transmitted or received by a remote station or other station via MODEM or network 22. MODEM or network 22 transmits and receives data. When MODEM is used, the signal is modulated and / or demodulated and transmitted on the appropriate line, such as a telephone line or any equivalent thereof. Alternatively, it can be transmitted via a network wiring arrangement configured to provide video signal transmission.

Data received from a distance via MODEM, network, or anything that may be extended is sent to the bus control circuit 36 through the processor circuit 40. Bus control circuit 36 passes data on data bus 38 to H.263 decode circuit 42 for decoding. After decoding the digital video data, the H.263 decode circuit 42 proceeds the decoded digital video data onto the memory bus 32 to the memory control circuit 30 for storage in the DRAM 14. The video out circuit 44 is then video out circuit in digital form for display by a selected video display device (not shown) to which the memory control circuit 30 is connected to receive a video signal from the video out circuit 44. Retrieval of stored digital video data from DRAM 14 for output by 44.

Alternatively, serial digital video signals or serial control signals from an attached computer system are input or output via high speed serial interface circuit 46, as described in more detail below.

The support circuit 48 performs certain "housekeeping" and control functions. The support circuit 48 has a well known I ² C bus 50 that handles the interrupt signal INT and the reset signal RST and programs an array of programmable I / O pins (PIO) (not shown). Interact with the EEPROM module 16 through.

EEPROM module 16 may be used to store machine code for operation of processor circuit 40. When initiated, machine code may be transferred from the relatively slow EEPROM module 16 to the relatively fast processor memory device 18 for use by the processor circuit 40 during normal operation.

The system of the invention shown in FIG. 2 incorporates a number of video input options supplied by the video input means 11, the output of which is supplied as an input video signal 26. The input means 11 here appear to comprise two or more sources of video signals. Exemplary sources include an internal digital camera 52, an internal NTSC or PAL video camera 56, and an external NTSC or PAL video camera 58. Input may be from an external high speed serial camera 60. Although shown separately from the input means 11, the high speed serial camera 60 can be incorporated into the input means 11 or individually arranged to supply an input signal to the data bus 38.

The "inner" camera 52 is a camera where the lens and interface control circuitry is installed inside the system enclosure, while the "outer" camera is interfaced via a connector, which may be a video decoder 54.

More specifically, as shown in FIG. 2, the digital video signal 26 is either NTSC or from an internal digital camera 52 or from an internal NTSC or PAL video camera 56 or from an external NTSC or PAL video camera 58. It can be generated by the video decoder module 54 to convert the PAL signal into a digital video signal 26. Alternatively, or in addition, a digital camera 60 having a high speed serial output, such as a FireWire or USB port, may transmit a serial digital video signal to the high speed serial interface 46 for further processing and transmission to the data bus 38. You can output

The ASIC 10 of FIG. 2 is configured to have a memory means 15 comprising a DRAM 14 and a memory control circuit 30. The memory control circuit 30 sends the digital video signal 26 to the H.263 module 34 for compression before processing it into the DRAM 14 for storage from the memory bus 32 and into the video processing means 35. send. The video processing means 35 comprises a processor 40 as well as a support circuit 48 and a bus control circuit 36. This may include processor memory 18 and EEPROM 16, if provided.

Video processing means 35 and more particularly processor circuit 40 direct the encoded digital video data to remote interface circuit 19. The remote interface circuit 19 is any suitable circuit for transmitting and receiving video conferencing signals to and from a remote source. In other words, the remote interface circuit 19 is configured to receive video signals from a remote source that affects video signals and preferably what can be called video conferencing. The outgoing video signals as well as the audio signals are transmitted to a remote location, ideally for returning similar video and audio signals for presentation as a video signal on a selected video display or output device and for processing with an ASIC. The remote interface means 19 is here illustrated as including a MODEM 22 and an audio circuit 20.

The ASIC 10 of FIG. 2 has all the remaining processing circuitry of FIG. 1 as shown in FIG. 2, while simultaneously multiple video input arrangements use a combination of software and hardware to promote processing speed and flexibility. It is remarkably differentiated in that it can be tolerated from the means 11.

The system of the present invention of another embodiment, shown in FIG. 3, is provided by conductors 73 via NTSC / PAL 68, video modulator 62, LCD 72, RGB 71 and high speed serial interface 46. It can also integrate one of several video output options, including a connected remote device.

More specifically, as shown in FIG. 3, the digital video output of the video out circuit 44 here converts the digital video output from the video out circuit 44 into a modulated analog signal 64. May be provided to the video output means 43 shown to include the < RTI ID = 0.0 > The analog signal is then multiplexed by the cable multiplexer module 66 to output as a TV channel (eg, channel "3") to the monitor 68. Alternatively, the digital video output of video out circuit 44 may be converted by video encode module 70 to an NTSC or PAL analog format suitable for input by video encoder module 70 to a dedicated port on monitor 68. Or can be converted into an LCD format signal for the LCD screen 72. In another alternative, video encoder module 70 may convert digital video output from video out circuit 44 into an RGB signal 71 suitable for direct application to a computer monitor (not shown).

The system of the present invention may be configured or modified through the special use of a high speed serial interface 46 connected to a separate video 47 that is not illustrated in FIG. Video means 47 (FIG. 4) can be used for video input and / or video output. It can also be used to connect a system that secures a peripheral or remote device to another controller. Such a controller may be, for example, a cable box, set top box, personal computer or any number of general purpose or business controller devices. Likewise, this allows the system to be easily integrated directly into a standalone teleconferencing device or videophone.

More specifically, as shown in FIG. 4, the illustrated ASIC 10 outputs high speed serial interface circuit 46 (e.g., FireWire or USB port) for outputting serial digital video data 71 to video means 47. FIG. Has Video means 47 may comprise a controller by modem 74, which interfaces with a separate monitor or telephone system 76, such as monitor 68.

As shown in FIG. 5, video-in circuit 24 includes input configuration circuitry 78 that receives digital video signal 26 as well as serial digital video data from data bus 38. The control register circuit 30 (see FIG. 2) fixed by the bus control circuit 36 allows the input configuration circuit 78 to output data from the signal 26 or the data bus 38 in 4: 2: 2 YUV format. Allows selection and output The pixel decimation circuit 82 reduces the "color" component of the output signal and thereby reduces the data density of the signal by outputting a 4: 1: 1 YUV format signal. The first in, first out (FIFO) buffer 84 then holds the output signal before transferring it to the memory means 15 via the memory bus 32.

As shown in FIG. 6, the bus control circuit 36 includes a skeletal interface circuit 86 (otherwise known as a "backbone") and a processor circuit 40 for receiving data from the data bus 38. Processor interface circuitry 88 in communication with (see FIG. 4). The adjustment and control circuitry 90 that selects the interface circuits 86 and 88 will be activated at any point in time, and the host interface circuit 92 communicates data internally to and from the selected interface control circuit 94. On the other hand, the register information proceeds to the register interface control circuit 96. Both circuits 94 and 96 are in communication with third party module circuit 98, such as Firewire or USB serial-parallel circuitry.

As shown in FIG. 7, the video out circuit 44 directs the memory control circuitry (see FIG. 1) to direct the digital control data from the video memory module 14 (see FIG. 1) in the appropriate sequence. Circuit 100. The line memory circuit 102 then acts as a buffer for storing video data until two video lines of data are stored. The interpolator circuit 104 reverses the operation of the pixel decimation circuit 82 (see FIG. 5) by interpolating between each two lines of video data it receives to generate a 4: 2: 2 YUV signal. . The storage FIFO buffer 106 then stores the interpolated video data, and the control register circuit 108 controlled by the bus control circuit 36 (see FIG. 1) stores the video data in which the encoder control circuit 110 is stored. Output, or the situation may be indicated. At the same time, the stored video data is provided to the bus control circuit 36 (FIG. 1) on the data bus 38 for use by the high speed serial interface circuit 46 (FIG. 1).

2 or 3 may include a PC peripheral for camera or video conferencing; Cable box peripherals for camera or video conferencing; And remote cameras for surveillance systems, which can be easily and inexpensively configured as a variety of different devices including but not limited to these. Also, a system including the circuit of FIG. 2 or 3 may include a set top box video conferencing system; Cable box video conferencing system; And tightly coupled to other hardware to create other devices, including but not limited to videophones.

Of course, it should be understood that the systems shown in FIGS. 2-7 may be transmitting or receiving stations or perhaps the best video conferencing system.

The examples illustrated and disclosed herein are not intended to limit the scope of the invention as defined in the following claims.

Claims (24)

In a video conferencing circuit for use with multiple video input devices and video output devices, The video conference circuit, Video input means for providing an input video signal from one of a plurality of video signal generators; A remote interface circuit; A video output device; An application specific integrated circuit (ASIC) connected to said video input means, said video output device and said remote interface circuit, The application specific integrated circuit (ASIC), Video-in circuitry connected to said video input means for receiving a video input signal from one of said plurality of video signal generators; A memory circuit connected to the video-in circuit for receiving the video input signal, the memory circuit configured to hold and transmit the video input signal as stored data; Data compression means connected to the memory circuit to receive the stored data and compress the stored data through an encoding process to form compressed data; A video processing means connected to receive the compressed compressed data and connected to the remote interface circuit to transmit the extracted compressed data from a remote station and to receive the compressed compressed data, further comprising an internal video signal The video processing means connected to the video-in circuit, the memory circuit, the video decompressing means, the video receiving means, and the video image out means to control the flow of fields; A video decompression means connected to the video processing means to receive the incoming compressed data and configured to decompress the incoming compressed data and send it to the memory unit, wherein the memory circuit is configured to decompress the incoming compressed data; Video decompression means configured to convert the data into incoming stored data; And video image out means connected to receive the stored data incoming from the memory circuit and to transmit the incoming stored data as a video image signal to a video display device. The method of claim 1, And the remote interface circuitry comprises a modem. The method of claim 1, And the memory circuit includes a memory structure and a memory control circuit to convert video input signals into stored data and to convert the incoming compressed data into incoming stored data. The method of claim 3, wherein And the memory structure is dynamic RAM (DRAM) configured to receive and store the stored data and the incoming stored data. The method of claim 1, The video input means comprises video decoder circuitry for receiving selected video signals and converting the selected video signals into an input video signal. The method of claim 5, The video-in circuit is connected to an input configuration circuit connected to receive a plurality of video input signals, to the video processing means to receive control signals therefrom, and to the input configuration circuit to supply input control signals, And a control register to cause an input configuration circuit to operate to supply one of the plurality of video input signals to the memory circuit as the video input signal. The method of claim 6, The output of the input configuration circuit is supplied to a decimation circuit that operates to reduce the density of the output signal and is connected to a buffer to store and transmit an output that is video. The method of claim 1, And further comprising a data bus interconnected between the video-in circuit, the memory circuit, the encoding circuit, the decoding circuit and the video out circuit for transmitting control signals therein, the video processing means And a bus control circuit connected to the data bus for supplying the control signals thereto. The method of claim 8, The bus control circuit comprises a skeletal interface circuit connected to the data bus, the skeletal interface circuit configured to generate and supply the control signals to the data bus. The method of claim 9, The video processing means includes a data processor connected to the remote interface circuit, a processor interface connected to the data processor for supplying data thereto, a processor interface and a skeleton interface circuit, and a skeleton interface circuit and a processor. Adjustment and control circuitry configured to select and activate one of the interfaces, and host interface circuitry coupled to the adjustment and control circuitry, wherein the host interface circuitry supplies data to and receives data from the processor interface and the skeleton interface circuitry. And the adjustment and control circuitry is further connected to supply video signals to and receive video signals from an external device for obtaining and displaying a video image. In a video conferencing circuit for use with multiple video output devices and video input devices, The video conference circuit, Video output means for providing output video signals to one of the plurality of video output devices; A remote interface circuit; A video input device; An application specific integrated circuit (ASIC) connected to said video input device, said video output means and said remote interface circuit, The application specific integrated circuit, Video-in circuitry connected to the video input device for receiving video input signals from the plurality of video input devices; Memory circuitry connected to the video-in circuitry for receiving the video input signal and configured to hold and transmit the video input signal as stored data; Data compression means connected to the memory circuit to receive the stored data and compress the stored data through an encoding process to form compressed data; Is connected to receive the extracted compressed data, is connected to the remote interface circuit to transmit the extracted compressed data from a remote station and to receive the incoming compressed data, and also controls the flow of internal video signals Video processing means connected to said video-in circuit, said memory circuit, said video decompression means, said video receiving means, and said video image out means; A video decompression means connected to the video processing means to receive the incoming compressed data and configured to decompress the incoming compressed data and send it to the memory unit, wherein the memory circuit is configured to decompress the incoming compressed data; Said video decompression means configured to convert data into incoming stored data; A video conferencing circuit connected to receive stored data incoming from the memory circuit and to transmit the incoming stored data as a video image signal to one of the plurality of video output devices of the video output means. . The method of claim 11, And the remote interface circuitry comprises a modem. The method of claim 11, And the memory circuit includes a memory structure and a memory control circuit to convert video input signals to stored data and to convert the incoming compressed data to incoming stored data. The method of claim 13, And the memory structure is dynamic RAM (DRAM) configured to receive and store the stored data and the incoming stored data. The method of claim 11, The video-in circuit is connected to an input configuration circuit connected to receive the video input signal, to the video processing means to receive control signals therefrom, and to the input configuration circuit to supply input control signals, And a control register to enable the input configuration circuit to supply the video input signal to the memory circuit. The method of claim 15, The output of the input configuration circuit is supplied to a decimation circuit that operates to reduce the density of the output signal and is connected to a buffer to store and transmit an output that is video. The method of claim 11, And further comprising a data bus interconnected between the video-in circuit, the memory circuit, the encoding circuit, the decoding circuit, and the video out circuit for transmitting control signals therein. Means comprises a bus control circuit connected to the data bus to supply the control signals thereto. The method of claim 17, The bus control circuit includes a skeletal interface circuit connected to the data bus, the skeletal interface circuit configured to generate the control signals and to feed the data bus. The method of claim 18, The video processing means includes a data processor connected to the remote interface circuit, a processor interface connected to the data processor for supplying data thereto, a processor interface and a skeleton interface circuit, and a skeleton interface circuit and a processor. Adjustment and control circuitry configured to select and activate one of the interfaces, and a host interface coupled to the adjustment and control circuit, the host interface circuitry supplying data to and receiving data from the processor interface and the skeleton interface circuitry. Video conferencing circuitry configured to. The method of claim 11, The video image out circuit, A memory control sequencer coupled to the memory circuit, the memory control sequencer being configured to generate and transmit memory circuit commands to cause the memory circuit to supply the incoming stored data to a memory control sequencer and to supply the incoming stored data as an output. The memory control sequencer; A line buffer connected to receive the incoming stored data from the memory control sequencer, storing a video line of the incoming stored data as a first video out signal and another video of the stored video data as a second video out signal The line buffer, configured to store a line; An interpolator circuit connected to said line buffer to receive said first video out signal and said second video out signal and to generate an interpolated video signal; A buffer connected to the interpolator circuit to receive the interpolated video signal therefrom; A control register coupled to the data bus to receive control signals from the video processing control, the control register coupled to the buffer to supply signals to cause the buffer to supply the interpolated video signal; A buffer connected to the buffer to receive the interpolated video signal therefrom, and to receive the signals so that the interpolated video signal is supplied as a video image signal to one of the plurality of video output devices of the output means. A video conferencing circuit comprising a connected encoder. In a video conferencing circuit for use with multiple video output devices and video input devices, The video conference circuit, Video output means for providing output video signals to one of the plurality of video output devices; A remote interface circuit; Video input means for providing input video signals from one of a plurality of video signal generators; An application specific integrated circuit (ASIC) connected to said video input means, said video output means and said remote interface circuit, said application specific integrated circuit comprising: A video-in circuit connected to said video input means for receiving a video input signal from said plurality of video signal generators; Memory circuitry connected to the video-in circuitry for receiving the video input signal and configured to hold and transmit the video input signal as stored data; Data compression means connected to the memory circuit to receive the stored data and compress the stored data through an encoding process to form compressed data; A video processing means connected to receive the compressed compressed data and connected to the remote interface circuit to transmit the extracted compressed data from a remote station and to receive the compressed compressed data, further comprising an internal video The video processing means connected to the video-in circuit, the memory circuit, the video decompression means, the video receiving means, and the video image out means to control the flow of signals; A video decompression means connected to the video processing means to receive the incoming compressed data and configured to decompress the incoming compressed data and send it to the memory unit, wherein the memory circuit is configured to decompress the incoming compressed data; Said video decompression means configured to convert data into incoming stored data; And a video image out circuit connected to receive the stored data incoming from the memory circuit and to transmit the incoming stored data as a video image signal to one of the plurality of video output devices of the video output means. In a video conferencing circuit for use with multiple video input devices and multiple video output devices, The video conference circuit, Video input means for providing an input video signal from one of a plurality of video signal generators; A remote interface circuit; Video output means for providing output video signals to one of the plurality of video output devices; An application specific integrated circuit (ASIC) connected to said video input means, said video output device and said remote interface circuit, The application specific integrated circuit (ASIC), Receive the input video signal in each of a separate video signal format from one of a plurality of separate video input devices, Store the received data as stored data, Compressing the stored data through an encoding process to generate compressed data to be extracted; Output the extracted compressed data to the remote station through the remote interface circuit, Receive compressed data coming from the remote station via the remote interface circuit, Decompresses the incoming compressed data through a decoding process, Save the uncompressed data, Means for programming to output decompressed data through the video output means for display by one of the plurality of video output devices. The method of claim 22, And the remote interface circuit comprises a modem. The method of claim 23, wherein Said video input means comprising video decoder circuitry for receiving selected video signals and converting them into an input video signal.