KR20010064961A - Method for manufacturing single electron transistor - Google Patents
Method for manufacturing single electron transistor Download PDFInfo
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- KR20010064961A KR20010064961A KR1019990059449A KR19990059449A KR20010064961A KR 20010064961 A KR20010064961 A KR 20010064961A KR 1019990059449 A KR1019990059449 A KR 1019990059449A KR 19990059449 A KR19990059449 A KR 19990059449A KR 20010064961 A KR20010064961 A KR 20010064961A
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
- H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/937—Single electron transistor
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- Thin Film Transistor (AREA)
Abstract
본 발명은 도트의 균일성과 재현성을 향상시켜 소자의 신뢰성을 극대화하는데 적당한 싱글 일렉트론 트랜지스터 제조방법을 제공하기 위한 것으로, 본 발명의 싱글 일렉트론 트랜지스터 제조방법은 SOI웨이퍼의 실리콘층에 불순물 이온주입을 실시하여 소오스 및 드레인 영역을 형성하는 공정과, 상기 실리콘층을 패터닝하여 싱글 일렉트론 트랜지스터 형성영역을 정의하는 공정과, 상기 패터닝된 실리콘층상에 제 1 절연층을 형성한 후, 상기 제 1 절연층의 소정부분을 제거하여 상기 실리콘층을 소정부분 노출시키는 공정과, 상기 상기 노출부위의 실리콘층을 식각하여 상기 SOI웨이퍼의 산화막이 노출되도록 트렌치를 형성하는 공정과, 상기 실리콘층의 식각부위에 제 2 절연층을 형성하는 공정과, 상기 트렌치내에 전도성 물질을 매립하여 도트를 형성하는 공정과, 상기 도트상에 제 3 절연층을 형성한 후, 상기 제 3 절연층상에 컨트롤 게이트를 형성하는 공정을 포함하여 이루어진다.The present invention is to provide a method of manufacturing a single electron transistor suitable for maximizing the reliability of the device by improving the uniformity and reproducibility of the dot, the method of manufacturing a single electron transistor of the present invention by implanting impurity ions into the silicon layer of the SOI wafer Forming a source and drain region; patterning the silicon layer to define a single electron transistor formation region; and forming a first insulating layer on the patterned silicon layer, and then forming a predetermined portion of the first insulating layer. Removing a portion of the silicon layer to expose a predetermined portion of the silicon layer; forming a trench to expose the oxide layer of the SOI wafer by etching the silicon layer on the exposed portion; and a second insulating layer on the etching portion of the silicon layer. Forming a dot by filling a conductive material in the trench After forming the third insulating layer in the process and, on the dots, it comprises the step of forming a control gate on said third insulating layer.
Description
본 발명은 반도체 소자에 관한 것으로, 특히 싱글 일렉트론 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method for manufacturing a single electron transistor.
이하, 첨부된 도면을 참조하여 종래 싱글 일렉트론 트랜지스터를 설명하기로 한다.Hereinafter, a conventional single electron transistor will be described with reference to the accompanying drawings.
도 1은 싱글 일렉트론 트랜지스터의 구조를 도시한 것이다.1 shows the structure of a single electron transistor.
도 1과 같은 구조를 갖는 싱글 일렉트론 트랜지스터의 구조는 MOSFET와 거의 유사하다.The structure of the single electron transistor having the structure as shown in FIG. 1 is almost similar to that of the MOSFET.
즉, 소오스, 드레인, 게이트라고 불리는 세개의 전극을 갖고 있으며, 게이트 전극에 인가된 전압에 의해 소오스에서 드레인으로의 전자의 흐름이 제어된다.That is, it has three electrodes called a source, a drain, and a gate, and the flow of the electron from a source to the drain is controlled by the voltage applied to the gate electrode.
미설명 부호 "11"은 절연층이고, "12"는 도트, 그리고 "13"은 터널링 산화막을 지시한다.Reference numeral “11” denotes an insulating layer, “12” denotes a dot, and “13” denotes a tunneling oxide film.
이와 같은 싱글 일렉트론 트랜지스터는 구조적으로는 MOSFET와 유사하지만, 동작원리는 MOSFET와는 매우 상이하다.Such a single electron transistor is structurally similar to a MOSFET, but its operation principle is very different from that of a MOSFET.
도 2a 내지 2b는 싱글 일렉트론 트랜지스터의 동작원리를 설명하기 위한 도면이다.2A to 2B are diagrams for describing an operating principle of a single electron transistor.
드레인에 전압 Vg를 인가하면, 도 2a에 도시한 바와 같이, 소오스, 도트(dot) 및 드레인순으로 포텐셜 배열을 갖게 된다.When the voltage Vg is applied to the drain, as shown in Fig. 2A, potential arrays are provided in the order of source, dot and drain.
즉, 컨트롤 게이트에 전압을 인가하지 않고, 드레인에 포지티브(positive) 전압을 인가하면 싱글 일렉트론 트랜지스터의 도트(DOT)는 포지티브하게 된다. 따라서, 소오스내에 있는 전자들은 도트의 인력(attractive force)를 받게 되어 전자가 도트 안으로 터널링(tunneling)된다.In other words, when a positive voltage is applied to the drain without applying a voltage to the control gate, the dot DOT of the single electron transistor becomes positive. Thus, the electrons in the source are subjected to an attractive force of the dot so that the electrons are tunneled into the dot.
따라서, 전자가 도트안으로 들어가면 도 2b에 도시된 바와 같이, 도트의포텐셜이 감소하게 된다.Therefore, when electrons enter the dot, the potential of the dot is reduced, as shown in Fig. 2B.
이후, 컨트롤 게이트에 전압을 인가하게 되면 소오스쪽에서 터널링되어 들어온 전자에 의해 낮아졌던 도트의 포텐셜(potential)이 다시 높아지게 되고, 그에따라 상기 전자는 드레인쪽으로 터널링된다.Subsequently, when a voltage is applied to the control gate, the potential of the dot lowered by the electrons tunneled from the source is increased again, and the electrons are then tunneled toward the drain.
그러나 상기와 같은 종래 싱글 일렉트론 트랜지스터는 도트의 균일성과 재현성이 떨어져서 소자의 신뢰성이 좋지 않은 문제점이 있었다.However, the conventional single electron transistor as described above has a problem in that the reliability of the device is poor due to the poor uniformity and reproducibility of the dot.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 도트의 균일성과 재현성을 향상시켜 소자의 신뢰성을 극대화하는데 적당한 싱글 일렉트론 트랜지스터 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a single electron transistor suitable for maximizing the reliability of the device by improving the uniformity and reproducibility of the dot.
도 1은 종래 기술에 따른 싱글 일렉트론 트랜지스터의 구조단면도1 is a structural cross-sectional view of a single electron transistor according to the prior art
도 2는 종래 싱글 일렉트론 트랜지스터의 동작원리를 설명하기 위한 도면2 is a view for explaining the operation principle of a conventional single electron transistor
도 3a 내지 3g는 본 발명 싱글 일렉트론 트랜지스터 제조방법을 설명하기 위한 공정단면도3A to 3G are cross-sectional views illustrating a method of manufacturing a single electron transistor according to the present invention.
도 4는 도 3a공정 수행에 따른 평면도4 is a plan view according to the process of FIG.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31 : SOI웨이퍼 31c : 실리콘층31 SOI wafer 31c Silicon layer
35 : 제 2 절연층 36a : 도트35 second insulating layer 36a dot
37 : 제 3 절연층 38a : 컨트롤 게이트37: third insulating layer 38a: control gate
상기의 목적을 달성하기 위한 본 발명의 싱글 일렉트론 트랜지스터 제조방법은 SOI웨이퍼의 실리콘층에 불순물 이온주입을 실시하여 소오스 및 드레인 영역을 형성하는 공정과, 상기 실리콘층을 패터닝하여 싱글 일렉트론 트랜지스터 형성영역을 정의하는 공정과, 상기 패터닝된 실리콘층상에 제 1 절연층을 형성한 후, 상기 제 1 절연층의 소정부분을 제거하여 상기 실리콘층을 소정부분 노출시키는 공정과, 상기 상기 노출부위의 실리콘층을 식각하여 상기 SOI웨이퍼의 산화막이 노출되도록 트렌치를 형성하는 공정과, 상기 실리콘층의 식각부위에 제 2 절연층을 형성하는 공정과, 상기 트렌치내에 전도성 물질을 매립하여 도트를 형성하는 공정과, 상기 도트상에 제 3 절연층을 형성한 후, 상기 제 3 절연층상에 컨트롤 게이트를 형성하는 공정을 포함하여 이루어진다.In order to achieve the above object, a method of manufacturing a single electron transistor according to the present invention includes a process of forming a source and a drain region by implanting impurity ions into a silicon layer of an SOI wafer, and patterning the silicon layer to form a single electron transistor formation region. Defining a step, and forming a first insulating layer on the patterned silicon layer, removing a predetermined portion of the first insulating layer to expose a predetermined portion of the silicon layer, and Forming a trench to etch the oxide film of the SOI wafer by etching, forming a second insulating layer on an etching portion of the silicon layer, embedding a conductive material in the trench, and forming a dot; Forming a control gate on the third insulating layer after forming the third insulating layer on the dot; Achieved.
이하, 본 발명의 싱글 일렉트론 트랜지스터 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a single electron transistor of the present invention will be described with reference to the accompanying drawings.
도 3a 내지 3f는 본 발명의 싱글 일렉트론 트랜지스터 제조방법을 설명하기위한 공정단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a single electron transistor according to the present invention.
도 3a에 도시한 바와 같이, 실리콘 기판(31a)상에 산화막(oxide)(31b)과 실리콘층(silicon)(31c)이 차례로 적층된 SOI(Silicon On Insulator)웨이퍼(31)의 상기 실리콘층(31c)상에 마스크를 이용하여 싱글 일렉트론 트랜지스터의 소오스와 드레인이 형성될 영역에 이온주입을 실시한다.As shown in FIG. 3A, the silicon layer of the silicon on insulator (SOI) wafer 31 in which an oxide 31b and a silicon layer 31c are sequentially stacked on the silicon substrate 31a. Ion implantation is performed on a region on which source and drain of the single electron transistor are to be formed using a mask on 31c).
이어, 상기 실리콘층(31c)을 선택적으로 제거하여 도 4에 도시한 바와 같이, 싱글 일렉트론 트랜지스터가 형성될 영역을 형성한다.Next, the silicon layer 31c is selectively removed to form a region in which a single electron transistor is to be formed, as shown in FIG. 4.
이어, 상기 실리콘층(31c)상에 제 1 절연층(32)을 형성한다.Subsequently, a first insulating layer 32 is formed on the silicon layer 31c.
그리고, 상기 제 1 절연층(32)상에 포토레지스트(33)를 도포한 후, 패터닝하여 도트가 형성될 영역을 정의(define)한다.The photoresist 33 is coated on the first insulating layer 32 and then patterned to define a region where dots are to be formed.
도 3b에 도시한 바와 같이, 상기 포토레지스트(33)를 마스크로 이용한 식각 공정으로 상기 제 1 절연층(32)을 식각한다.As shown in FIG. 3B, the first insulating layer 32 is etched by an etching process using the photoresist 33 as a mask.
이후, 상기 포토레지스트(33)를 제거한 후, 상기 식각된 제 1 절연층(32) 패턴을 마스크로 SOI웨이퍼(31)의 실리콘층(31c)을 식각하여 도 3c에 도시한 바와 같이, 트렌치(34)를 형성한다.After removing the photoresist 33, the silicon layer 31c of the SOI wafer 31 is etched using the etched first insulating layer 32 pattern as a mask, and as shown in FIG. 3C, a trench ( 34).
이후, 상기 실리콘층(31c)의 식각된 부위에 터널링 산화막으로 사용될 제 2절연층(35)을 형성한다.Thereafter, a second insulating layer 35 to be used as a tunneling oxide film is formed on the etched portion of the silicon layer 31c.
여기서, 상기 제 2 절연층(35)은 산화막으로써, 산화 공정을 통해 상기 실리콘층(31c)의 식각된 부위에만 성장시키며 상기 제 2 절연층(35)의 두께는 약 30Å이하가 되도록 조절한다.Here, the second insulating layer 35 is an oxide film, grown only on the etched portion of the silicon layer 31c through an oxidation process, and the thickness of the second insulating layer 35 is adjusted to be about 30 kPa or less.
이어, 도 3d에 도시한 바와 같이, 상기 트렌치(34)를 포함한 전면에 도트(DOT)형성을 위한 제 1 폴리실리콘층(36)을 형성한다.Subsequently, as shown in FIG. 3D, the first polysilicon layer 36 for forming dots (DOT) is formed on the entire surface including the trench 34.
도 3e에 도시한 바와 같이, 상기 제 1 폴리실리콘층(36)을 에치백하여 상기 트렌치(34)를 매립시켜 도트(36a)를 형성한다.As shown in FIG. 3E, the first polysilicon layer 36 is etched back to fill the trench 34 to form a dot 36a.
여기서, 상기 도트(DOT)의 사이즈는 대략 0.1×0.1㎛2정도가 되도록 한다.Here, the size of the dot DOT is about 0.1 × 0.1 μm 2 .
한편, 상기 제 1 절연층(32)은 상기 도트 형성을 위한 에치백 공정시 소정두께로 식각되는데, 상기 제 1 절연층(32)의 잔류 두께가 약 1500Å 정도가 되도록 조절하여 이후에 형성할 컨트롤 게이트와 상기 실리콘층(31c)이 전기적으로 절연되도록 한다.On the other hand, the first insulating layer 32 is etched to a predetermined thickness during the etch back process for forming the dot, the control to be formed later by adjusting so that the remaining thickness of the first insulating layer 32 is about 1500Å The gate and the silicon layer 31c are electrically insulated from each other.
도 3f에 도시한 바와 같이, 상기 도트(36a)상에 컨트롤 게이트의 게이트 절연막으로 사용될 제 3 절연층(37)을 약 100Å정도의 두께로 형성한다.As shown in Fig. 3F, a third insulating layer 37 to be used as the gate insulating film of the control gate is formed on the dot 36a to a thickness of about 100 mW.
이후, 상기 제 3 절연층(37)을 포함한 전면에 컨트롤 게이트용 제 2 폴리실리콘층(38)을 형성한다.Thereafter, the second polysilicon layer 38 for the control gate is formed on the entire surface including the third insulating layer 37.
이때, 상기 제 2 폴리실리콘층(38)의 두께는 약 1500Å정도로 조절한다.At this time, the thickness of the second polysilicon layer 38 is adjusted to about 1500 kPa.
이어, 도 3g에 도시한 바와 같이, 상기 제 2 폴리실리콘층(38)을 선택적으로 제거하여 컨트롤 게이트(38a)를 형성하면 본 발명의 싱글 일렉트론 트랜지스터의제조공정이 완료된다.3G, when the second polysilicon layer 38 is selectively removed to form the control gate 38a, the manufacturing process of the single electron transistor of the present invention is completed.
참고적으로, 상기 도트(36a) 양쪽의 실리콘층(31c)은 소오스와 드레인으로 사용된다.For reference, the silicon layer 31c on both sides of the dot 36a is used as a source and a drain.
이상 상술한 바와 같이, 본 발명의 싱글 일렉트론 트랜지스터 제조방법은 전체적인 공정이 단순하고, 도트(DOT)의 균일도 및 재현성을 개선시켜 소자의 신뢰성을 향상시키는 효과가 있다.As described above, the single electron transistor manufacturing method of the present invention is simple in the overall process, has the effect of improving the reliability of the device by improving the uniformity and reproducibility of the dot (DOT).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100800508B1 (en) * | 2006-12-27 | 2008-02-04 | 재단법인 서울대학교산학협력재단 | Single-electron transistor with self-aligned trench and manufacturing method |
| KR100830203B1 (en) * | 2002-01-10 | 2008-05-16 | 충북대학교 산학협력단 | Manufacturing method of single electronic device |
| KR100949038B1 (en) * | 2007-09-14 | 2010-03-24 | 충북대학교 산학협력단 | Manufacturing method of single electron logic device operating at room temperature |
| KR101052868B1 (en) * | 2008-02-29 | 2011-07-29 | 주식회사 하이닉스반도체 | SOI element and its manufacturing method |
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| KR100866948B1 (en) | 2003-02-07 | 2008-11-05 | 삼성전자주식회사 | Single-electron transistor with memory function and manufacturing method thereof |
| KR100968032B1 (en) | 2007-09-14 | 2010-07-08 | 충북대학교 산학협력단 | Method for manufacturing single-electron nanodevices operating at room temperature |
| KR100973272B1 (en) * | 2008-04-25 | 2010-08-02 | 주식회사 하이닉스반도체 | SOI element and its manufacturing method |
| KR101000472B1 (en) * | 2008-05-07 | 2010-12-14 | 주식회사 하이닉스반도체 | SOI element and its manufacturing method |
| KR101246306B1 (en) | 2011-08-16 | 2013-03-21 | 서울대학교산학협력단 | Single electron transistor and fabrication method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100830203B1 (en) * | 2002-01-10 | 2008-05-16 | 충북대학교 산학협력단 | Manufacturing method of single electronic device |
| KR100800508B1 (en) * | 2006-12-27 | 2008-02-04 | 재단법인 서울대학교산학협력재단 | Single-electron transistor with self-aligned trench and manufacturing method |
| KR100949038B1 (en) * | 2007-09-14 | 2010-03-24 | 충북대학교 산학협력단 | Manufacturing method of single electron logic device operating at room temperature |
| KR101052868B1 (en) * | 2008-02-29 | 2011-07-29 | 주식회사 하이닉스반도체 | SOI element and its manufacturing method |
| US8232149B2 (en) | 2008-02-29 | 2012-07-31 | Hynix Semiconductor Inc. | SOI device having an increasing charge storage capacity of transistor bodies and method for manufacturing the same |
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