KR20010063722A - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR20010063722A KR20010063722A KR1019990061799A KR19990061799A KR20010063722A KR 20010063722 A KR20010063722 A KR 20010063722A KR 1019990061799 A KR1019990061799 A KR 1019990061799A KR 19990061799 A KR19990061799 A KR 19990061799A KR 20010063722 A KR20010063722 A KR 20010063722A
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- copper
- damascene pattern
- diffusion barrier
- polishing
- forming
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 45
- 239000010949 copper Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 36
- 238000005498 polishing Methods 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 239000002002 slurry Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 15
- 238000007517 polishing process Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 230000004888 barrier function Effects 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 11
- 238000009413 insulation Methods 0.000 abstract 3
- 230000003139 buffering effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007518 final polishing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 구리 배선의 구리가 절연막으로 확산되는 것을 방지하기 위하여 형성되는 전도체 확산 방지막을 구리층 형성전에 다마신 패턴 이외의 부분에 존재하는 전도체 확산 방지막을 미리 제거하여 구리배선 형성을 위한 화학적 기계적 연마공정시 전도체 확산 방지막의 연마공정을 생략할 수 있어 공정 소요시간 및 슬러리의 양을 줄여 공정단가를 절감할 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and in particular, a conductor diffusion preventing film, which is formed to prevent diffusion of copper from a copper wiring into an insulating film, is present in a portion other than the damascene pattern before the copper layer is formed. Method for forming a copper wiring of a semiconductor device which can reduce the process time by reducing the process time and the amount of slurry by eliminating the preliminary step and eliminating the polishing process of the conductor diffusion barrier during the chemical mechanical polishing process for forming copper wiring. will be.
일반적으로 알려진 구리 배선 형성과정에서 전도체 확산 방지막으로는 Ta 또는 TaN이 사용된다. Ta 및 TaN의 화학적 특성은 구리와 상이하기 때문에 화학적 기계적 연마공정시 통상 2단계로 구분하여 먼저 대부분의 구리를 연마하면서 평탄화 시킨 다음에 잔류구리와 전도체 확산 방지막을 연마하게 된다. 그러나 이들 전도체 확산 방지막은 쉽게 연마되지 않으며, 현재 개발되어 있는 Ta 및 TaN용 슬러리(Slurry)에서의 연마속도는 약 500Å/min 정도로 매우 낮기 때문에 2단계 연마공정을 채택한다 할지라도 잔류 구리와 전도체 확산 방지막을 연마하는 공정에 상당한 시간이 소요된다. 전도체 확산 방지막의 연마에 소요되는 시간이 길기 때문에 디싱(Dishing)이나 산화막침식이 심해지는 문제가 발생하게 되어 구리 배선/전도체 확산 방지막/층간절연막의 선택비가 1:1:1인 슬러리의 필요성이 대두되었으나 이 또한 층간 절연막의 연마공정이 추가되어 전도체 확산 방지막의 제거에 많은 시간이 소요되기 때문에 공정시간 지연과 슬러리의 소모량이 많다는 문제점이 있다.Generally, Ta or TaN is used as a conductive diffusion barrier in the known copper wiring formation process. Since the chemical properties of Ta and TaN are different from those of copper, the chemical mechanical polishing process is generally divided into two stages. First, most of copper is polished and planarized, followed by polishing of residual copper and conductor diffusion barrier. However, these conductive diffusion barriers are not easily polished and the residual copper and conductor diffusion even if a two-step polishing process is adopted since the polishing rate in currently developed slurries for Ta and TaN is very low, about 500 kW / min. The process of polishing the protective film takes considerable time. Due to the long time required for polishing of the conductive diffusion barrier, there is a problem of severe dishing and oxide erosion. However, since the polishing process of the interlayer insulating film is added, it takes a long time to remove the conductive diffusion preventing film, and thus there is a problem of delay in processing time and consumption of slurry.
따라서, 본 발명은 전도체 확산 방지막의 연마공정을 생략할 수 있도록 공정을 개선하여 연마공정의 소요시간 및 슬러리의 양을 줄일 수 있는 반도체 소자의 구리배선 형성방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device which can reduce the required time and the amount of slurry of the polishing process by improving the process so that the polishing process of the conductive diffusion preventing film can be omitted.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리 배선 형성방법은 층간 절연막에 다마신 패턴이 형성된 기판이 제공되는 단계; 상기 다마신 패턴을 포함한 상기 층간 절연막 표면에 전도체 확산 방지막을 형성하는 단계; 상기 다마신 패턴 이외의 부분에 형성된 상기 전도체 확산 방지막을 제거하여 상기 다마신 패턴 부분에만 상기 전도체 확산 방지막을 남기는 단계; 및 상기 전도체 확산 방지막을 포함한 전체구조 상부에 구리증착 및 화학적 기계적 연마공정에 의해 구리배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming a copper wiring of a semiconductor device, the method comprising: providing a substrate having a damascene pattern formed on an interlayer insulating film; Forming a conductive diffusion barrier on a surface of the interlayer insulating film including the damascene pattern; Removing the conductive diffusion barrier formed in portions other than the damascene pattern to leave the conductive diffusion barrier only in the damascene pattern; And forming a copper wiring on the entire structure including the conductor diffusion barrier by copper deposition and chemical mechanical polishing.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 기판 10 : 층간 절연막1 substrate 10 interlayer insulating film
11 : 전도체 확산 방지막 12 : 포토래지스트막11 conductor diffusion prevention film 12 photoresist film
12A : 포토레지스트 패턴 13 : 구리층12A: Photoresist Pattern 13: Copper Layer
130 : 구리 배선130: copper wiring
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 구리 배선 형성방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
도 1a를 참조하여, 반도체 소자를 형성하기 위해 여러 요소가 형성된 기판(1)의 상부에 층간 절연막(10)을 형성한 후, 다마신(DAMASCENE) 방식에 의해 트렌치(Trench)와 콘택홀(Contact Hole)로 이루어진 다마신 패턴을 형성한다. 다마신 패턴을 포함한 층간 절연막(10)의 상부 표면에 전도체 확산 방지막(11) 및 포토레지스트막(12)을 순차적으로 형성한다. 전도체 확산 방지막(11)은 Ta 또는 TaN등을 사용하여 수백Å의 두께로 형성한다.Referring to FIG. 1A, after forming the interlayer insulating film 10 on the substrate 1 on which various elements are formed to form a semiconductor device, a trench and a contact hole are formed by a DAMASCENE method. A damascene pattern formed of holes is formed. The conductor diffusion barrier film 11 and the photoresist film 12 are sequentially formed on the upper surface of the interlayer insulating film 10 including the damascene pattern. The conductor diffusion barrier 11 is formed to a thickness of several hundred micrometers by using Ta or TaN.
도 1b를 참조하여, 다마신 패턴 형성시에 사용된 마스크와 반데의 상을 갖는 리버스(Reverse) 마스크를 이용하여 포토레지스트막(12)을 패터닝하고, 이로 인하여 다마신 패턴 상에 포토레지스트 패턴(12A)이 형성된다. 포토레지스트 패턴(12A)을 식각 마스크로 이용한 식각공정으로 노출된 전도체 확산 방지막(11)을 제거하여 다마신 패턴에만 확산 방지막(11)을 남긴다.Referring to FIG. 1B, the photoresist film 12 is patterned by using a reverse mask having a mask and a bande image used when forming the damascene pattern, thereby forming a photoresist pattern on the damascene pattern ( 12A) is formed. The conductive diffusion barrier 11 exposed by the etching process using the photoresist pattern 12A as an etching mask is removed to leave the diffusion barrier 11 only in the damascene pattern.
도 1c를 참조하여, 포토레지스트 패턴(12A)를 제거한 후, 다마신 패턴이 매립되도록 전체 구조상에 구리층(13)을 형성한다.Referring to FIG. 1C, after removing the photoresist pattern 12A, the copper layer 13 is formed on the entire structure so that the damascene pattern is embedded.
상기에서, 구리층(13)은 구리 시드층(Cu seed layer)을 물리 기상 증착(PVD)법으로 형성한 후, 전채도금법, 무전해도금법, 금속유기 화학기상 증착법등 여러가지 방법에 의해 형성한다.In the above-described copper layer 13, a copper seed layer is formed by physical vapor deposition (PVD), followed by various methods such as an electroplating method, an electroless plating method, and a metal organic chemical vapor deposition method.
도 1d를 참조하여, 구리 연마용 슬러리를 사용하여 화학적 기계적 연마공정으로 층간 절연막(10)의 상부면이 노출될 때가지 구리층(13)을 연마한 후, 화학적 기계적 연마 장비에서 버핑(Buffing) 하거나 세정하여 다마신 패턴내에 구리배선(130)을 형성한다.Referring to FIG. 1D, after polishing the copper layer 13 until the upper surface of the interlayer insulating layer 10 is exposed by a chemical mechanical polishing process using a copper polishing slurry, buffing in the chemical mechanical polishing equipment. Or by cleaning to form a copper wiring 130 in the damascene pattern.
상기한 본 발명의 실시예에서는 구리배선을 형성하기 위한 연마공정시 구리연마용 슬러리만을 사용하고 전도체 확산 방지막 연마용 슬러리는 사용하지 않는다.In the above-described embodiment of the present invention, only the copper polishing slurry is used in the polishing process for forming copper wiring, and the slurry for polishing the conductive diffusion barrier is not used.
구리배선 형성공정에서 구리의 확산방지막 역할을 하는 Ta 및 TaN는 화학적으로 매우 안정하여 높은 연마속도를 갖는 슬러리가 현재로서는 개발되어 있지 않다. 여러 슬러리 제조업체에서 나름대로 전도체 확산 방지막용 슬러리를 개발하여 구리층 연마후에 전도체 확산 방지막을 연마할 수 있도록 하고는 있지만 평균 연마속도가 500Å/min로 매우 낮기 때문에 공정시간이 많이 소요되며, 특히 현재 전도체 확산 방지막용 슬러리는 디싱(Dishing)과 산화막 침식현상을 억제하기 위한 방편으로 구리:전도체 확산 방지막:층간 절연막의 연마 선택비가 1:1:1을 가지도록 개발되고 있는 추세이나 1:1:1 슬러리는 연마대상막의 연마속도가 동일하기 대문에 옵티컬(Optical)방식의 EPD(End Point Detection) 시스템을 활용할 수 없을 때 웨이퍼간의 연마속도 차이에서 오는 최종 목표의 변화를 정확히 제어할 수 없는 문제가 있다. 반면 본 발명과 같이 전도체 확산 방지막을 미리 식각공정을 통해 제거하면 최종 연마공정에서 고선택비 슬러리를 사용할 수 있기 때문에 우선 공정마진 확보라는 측면에서 우수한 특성을 가지고 있고 기존의 어느 EPD 시스템이든지 최종공정까지 이용할 수 있어 공정제어 측면에서도 장점이 있다.Ta and TaN, which serve as a diffusion barrier of copper in the copper wiring forming process, are chemically very stable, and a slurry having a high polishing rate has not been developed at present. Although many slurry manufacturers have developed slurry for conductor diffusion barriers, it is possible to polish the conductor diffusion barrier after polishing the copper layer. However, the average polishing speed is very low, 500 속도 / min. Slurry for prevention film is a method for suppressing dishing and oxide erosion and is developed to have a 1: 1: 1 polishing selectivity of copper: conductor diffusion prevention film: interlayer insulating film. Since the polishing rate of the film to be polished is the same, there is a problem in that the final target change resulting from the difference in polishing rate between wafers cannot be accurately controlled when an optical end point detection (EPD) system cannot be utilized. On the other hand, if the conductive diffusion barrier is removed through an etching process in advance as in the present invention, since the high selectivity slurry can be used in the final polishing process, it has excellent characteristics in terms of securing process margins, and any existing EPD system to the final process. There is also an advantage in terms of process control.
상술한 바와 같이, 본 발명은 구리 배선의 구리가 절연막으로 확산되는 것을방지하기 위하여 형성되는 전도체 확산 방지막을 구리층 형성전에 다마신 패턴 이외의 부분에 존재하는 전도체 확산 방지막을 미리 제거하여 구리배선 형성을 위한 화학적 기계적 연마공정시 전도체 확산 방지막의 연마공정을 생략할 수 있어 공정 소요시간 및 슬러리의 양을 줄여 공정단가를 절감할 수 있다.As described above, the present invention removes the conductor diffusion barrier film formed to prevent the diffusion of the copper of the copper wiring into the insulating film in advance by removing the conductor diffusion barrier film present in the portion other than the damascene pattern before forming the copper layer. During the chemical mechanical polishing process, the polishing process of the conductive diffusion barrier layer can be omitted, thereby reducing the process time and the amount of slurry to reduce the process cost.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990061799A KR20010063722A (en) | 1999-12-24 | 1999-12-24 | Method of forming a copper wiring in a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990061799A KR20010063722A (en) | 1999-12-24 | 1999-12-24 | Method of forming a copper wiring in a semiconductor device |
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| Publication Number | Publication Date |
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| KR20010063722A true KR20010063722A (en) | 2001-07-09 |
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| KR1019990061799A KR20010063722A (en) | 1999-12-24 | 1999-12-24 | Method of forming a copper wiring in a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9331015B2 (en) | 2012-12-11 | 2016-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device with a multilayer wire |
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1999
- 1999-12-24 KR KR1019990061799A patent/KR20010063722A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9331015B2 (en) | 2012-12-11 | 2016-05-03 | Samsung Electronics Co., Ltd. | Semiconductor device with a multilayer wire |
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