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KR20010057048A - Build-up substrate - Google Patents

Build-up substrate Download PDF

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Publication number
KR20010057048A
KR20010057048A KR1019990058792A KR19990058792A KR20010057048A KR 20010057048 A KR20010057048 A KR 20010057048A KR 1019990058792 A KR1019990058792 A KR 1019990058792A KR 19990058792 A KR19990058792 A KR 19990058792A KR 20010057048 A KR20010057048 A KR 20010057048A
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KR
South Korea
Prior art keywords
stacked
insulating layer
laminated
layer
seconds
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KR1019990058792A
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Korean (ko)
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KR100349123B1 (en
Inventor
탁철
Original Assignee
이형도
삼성전기주식회사
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Priority to KR1019990058792A priority Critical patent/KR100349123B1/en
Publication of KR20010057048A publication Critical patent/KR20010057048A/en
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Publication of KR100349123B1 publication Critical patent/KR100349123B1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467Adding a circuit layer by thin film methods
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE: A stacked substrate is provided to prevent signal reflection by maintaining the insulation layer at constant thickness, and prevent time delay of signal transmission by matching the designed resistance of parts and the designed resistance of PCB. CONSTITUTION: A stacked substrate comprises a plurality of CCLs(copper-clad laminates)(110) having electrode patterns(100) stacked onto and beneath the CCL and first insulation layers(120) stacked onto and beneath the CCL; copper sheet layers(130) stacked to the first insulation layers; second insulation layers(140) stacked to the copper sheet layers through a pressing and drying process; and electrode layers(150) stacked to the second insulation layers. The second insulation layer is made up of epoxy dry film, and stacked to the copper sheet layer by being pressed at a pressure of 170 to 190Kg/cm¬2 and a temperature of 40 to 70°C for 10 to 20 seconds, secondly pressed at a temperature of 140 to 160°C for 10 to 20 seconds, and dried at a temperature of 150°C for 10 to 20 seconds.

Description

적층기판{BUILD-UP SUBSTRATE}Multilayer Board {BUILD-UP SUBSTRATE}

본 발명은 전자 신호처리의 고속화(HIGH SPEED SIGNAL)에 따른 기판사의 인피던스(IMPEDANCE)제어가 필수적인 고속 모듈기판및 통신기기류에 사용되는 적층 기판에 있어서, 인쇄방식으로 층간의 절연층 확보를 할경우 발생되는 절연층의 두께 편차에 의한 저항이 증가하여 신호전송에 타임 디레이가 발생하는 것을 방지토록 절연층을 정형화 되는 에폭시 계열의 드라이 필름에 의해 가압 적층하는 적층기판에 관한 것이다.In the present invention, a high-speed module substrate and a laminated substrate used in communication devices, which are required to control the impedance of the substrate company according to the high speed signal of the electronic signal processing, are generated when the insulating layer is secured between layers by a printing method. The present invention relates to a laminated substrate in which an insulating layer is pressure-laminated by an epoxy-based dry film to form a mold to prevent time delay in signal transmission due to an increase in resistance due to thickness variation of the insulating layer.

일반적으로, 전자기기의 고속회로 전송시스템에서는 보다많은 양의 신호(DATD)를 가장빠른 시간에 전달하는 것이 필수적이고, 고속으로 많은 신호의 전송을 위해서는 부품상의 설계저항과 인쇄회로기판상의 설계저항이 일치되어야 하며, 이와같은 인쇄회로기판은 전자 신호처리의 고속화에 따른 기판상의 인피던스제어가 필수적인 고속 모듈기판등에 사용된다.In general, in a high-speed circuit transmission system of an electronic device, it is necessary to transmit a larger amount of signals (DATD) at the fastest time, and in order to transmit a large amount of signals at high speed, a design resistance on a part and a design resistance on a printed circuit board are Such a printed circuit board is used for a high-speed module board and the like, in which inductance control on the board is required due to the high speed of electronic signal processing.

이와같은 기술과 관련된 종래의 적층기판은 도1에 도시한 바와같이, 25㎛의 두께를 갖도록 전극층(10)을 인쇄에 의해 형성한후 그 상측에 열 경화성수지로서 이루어 지는 제1절연층(20)을 인쇄에 의해 적층형성하며, 상기 제1절연층(20)의 상측에 35㎛의 두께를 갖는 동박층(30)을 적층형성한후 그 상측으로 제2절연층(40)과 전극패턴(50)이 상하측에 형성되는 CCL(60)이 적층되어 캐패시터를 형성하고, 상기 제2절연층(40)의 상측에 동박층(30)과 제1절연층(20) 및 전극층(10)이 순차로 적층되는 구성으로 이루어 진다.As shown in FIG. 1, the conventional laminated substrate related to the above technique has a first insulating layer 20 formed of a thermosetting resin on the upper side after forming the electrode layer 10 by printing to have a thickness of 25 μm. ) Is laminated by printing, and a copper foil layer 30 having a thickness of 35 μm is laminated on the first insulating layer 20, and then the second insulating layer 40 and the electrode pattern ( CCL (60) having 50 is formed on the upper and lower sides are stacked to form a capacitor, and the copper foil layer (30), the first insulating layer (20) and the electrode layer (10) are formed on the upper side of the second insulating layer (40). It consists of a configuration that is sequentially stacked.

상기와 같은 적층기판에 있어서는, 상하측에 전극패턴(50)을 갖는 CCL(60)과 그 상하측에 격자형의 파이버와 레진으로 이루어지는 제2절연층(40)을 삽입하고, 이때 상기 전극패턴(50)에 전원(VCC)과 접지전원(GND)을 공급할때 그 사이에 전하가 축적되고, 이때 상기 동박층(30)의 상측에 적층되는 제1절연층(20)의 절연거리(두께)를 일정하게 유지하여 일정 저항값을 갖도록 하는 것이다.In the laminated substrate as described above, the CCL 60 having the electrode patterns 50 on the upper and lower sides thereof and the second insulating layer 40 made of the lattice-shaped fibers and resins are inserted on the upper and lower sides thereof. When the power supply VCC and the ground power supply GND are supplied to the 50, electric charges are accumulated therebetween, and at this time, an insulation distance (thickness) of the first insulating layer 20 stacked on the copper foil layer 30. It is to keep a constant to have a constant resistance value.

그러나, 상기와 같은 적층기판은, 열경화성수지로 제1절연층(20)을 인쇄에의해 도포하여 적층 형성할 경우 작업자의 숙련도에 따라 도포두께의 편차가 발생되고, 이에의해 특성값에 영향을 주는 중요한 인자로서 도체를 통하여 전송되는 전기신호의 저항에 변화가 발생되어 신호가 반사되고, 인쇄회로기판에 실장되는 부품의 설계저항과 인쇄회로기판의 설계저항이 불일치하여 신호전송에 타임딜레이(TIME DELAY) 현상이 발생되어 정확한 신호전송이 이루어지지 않게 되며, 이에따라 고속전송이 불가능하게 되는 단점이 있었던 것이다.However, in the laminated substrate as described above, when the first insulating layer 20 is formed by laminating by printing with a thermosetting resin, variation in coating thickness occurs according to the skill of the operator, thereby affecting characteristic values. As an important factor, a change occurs in the resistance of an electrical signal transmitted through a conductor, which causes the signal to be reflected, and a time delay for signal transmission due to a mismatch between the design resistance of a component mounted on a printed circuit board and the design resistance of a printed circuit board. ) Phenomenon occurs, so that accurate signal transmission is not possible, and therefore, high speed transmission is impossible.

본 발명은 상기한 바와같은 종래의 여러 문제점들을 개선하기 위한 것으로서 그 목적은, 작업자의 숙련도에 상관없이 도포두께의 편차 발생이 방지되어 신호의 반사가 없고, 인쇄회로기판에 실장되는 부품의 설계저항과 인쇄회로기판의 설계저항이 일치하여 정확한 신호전송이 이루어지며, 고속전송이 가능하게 되고, 기판의 제작시간을 최소화 하는 적층기판을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention is directed to improving various conventional problems as described above. The object of the present invention is to prevent variations in coating thickness, regardless of the skill of the operator, so that there is no reflection of a signal and design resistance of a component mounted on a printed circuit board. And the design resistance of the printed circuit board is matched to achieve accurate signal transmission, high-speed transmission is possible, to provide a laminated substrate that minimizes the production time of the substrate.

도1은 종래의 적층기판 적층상태를 도시한 평면도1 is a plan view showing a laminated state of a conventional laminated substrate

도2는 본 발명에 따른 적층기판의 적층상태를 도시한 평면도2 is a plan view showing the laminated state of the laminated substrate according to the present invention;

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100...전극패턴 110...CCL100 ... electrode pattern 110 ... CCL

120...제1절연층 130...동박층120 First insulating layer 130 Copper foil layer

140...제2절연층 150...전극층140 second insulating layer 150 electrode layer

상기 목적을 달성하기 위한 기술적인 구성으로서 본 발명은,The present invention as a technical configuration for achieving the above object,

상하측면에 전극패턴이 적층되며, 제1절연층이 상하측에 적층되는 복수의 CCL과,A plurality of CCLs in which electrode patterns are stacked on upper and lower sides, and a first insulating layer is stacked on upper and lower sides;

상기 절연층의 일측에 적층되는 동박층및Copper foil layer laminated on one side of the insulating layer and

상기 동박층의 일측에 적층되는 드라이 필름이 적층되어 형성되는 제2절연층과,A second insulating layer formed by stacking dry films stacked on one side of the copper foil layer;

상기 제2절연층에 적층되는 전극층을 포함하는 구성으로 이루어진 적층기판을 마련함에 의한다.By providing a laminated substrate having a configuration including an electrode layer laminated on the second insulating layer.

이하, 첨부된 도면에 의거하여 본 발명의 실시예를 상세하게 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도2는 본 발명에 따른 적층기판의 적층상태를 도시한 평면도로서 본 발명은, 상하측면에 전극패턴(100)이 일체로 적층인쇄되는 적어도 하나 이상의 CCL(110)에 접하도록 제1절연층(120)이 적층인쇄되어 복수의 CCL(110)이 일체로 적층 형성된다.FIG. 2 is a plan view illustrating a laminated state of a laminated substrate according to the present invention. The present invention is directed to contacting at least one CCL 110 in which electrode patterns 100 are integrally stacked and printed on upper and lower sides thereof. 120 is laminated and printed to form a plurality of CCL (110) integrally stacked.

상기 제1절연층(120)에 35㎛의 두께를 갖도록 동박층(130)을 일체로 적층 인쇄한다.The copper foil layer 130 is integrally laminated and printed on the first insulating layer 120 to have a thickness of 35 μm.

상기 동박층(130)에 에폭시 계열의 아지노모토(AJINOMOTO) 제품인 드라이 필름을 적층하여 40~60℃의 온도에서 170~190kg/㎠의 압력으로 가압착한후 140~160℃의 온도에서 170~190kg/㎠ 압력으로 압착하고, 150℃의 온도로 10~20초 동안 건조하여 제2절연층(140)을 형성한다.Epoxy-based Ajinomoto (AJINOMOTO) product dry film laminated on the copper foil layer 130 and press-bonded at a pressure of 170 ~ 190kg / ㎠ at a temperature of 40 ~ 60 ℃ and 170 ~ 190kg / ㎠ at a temperature of 140 ~ 160 ℃ Pressurized under pressure and dried at a temperature of 150 ° C. for 10 to 20 seconds to form a second insulating layer 140.

상기 드라이 필름층(140)에 동재질로서 25㎛의 두께를 갖는 전극층(150)을 인쇄에 의해 적층형성하는 구성으로 이루어 진다.The dry film layer 140 is made of a material that is laminated with the electrode layer 150 having a thickness of 25 μm as a material by printing.

이와같은 구성으로 이루어진 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention made of such a configuration as follows.

도2에 도시한 바와같이, 상하측에 전극패턴(100)이 일체로 인쇄되어 적층 형성되는 복수의 CCL(110)이 그 상하측에 파이버와 레진으로 이루어지는 절연층(120)에 의해 적층될때 각각의 CCL(110)에 접지전원(GND)과 입력전원(VCC)이 연결되어 공급되면 캐패시턴스가 형성토록 된다.As shown in Fig. 2, when a plurality of CCLs 110, in which the electrode patterns 100 are integrally printed and stacked on the upper and lower sides, are laminated by the insulating layer 120 made of fiber and resin on the upper and lower sides thereof, respectively. When the ground power supply GND and the input power supply VCC are connected to and supplied to the CCL 110, the capacitance is formed.

상기 제1절연층(120)에 35㎛의 두께를 갖도록 동박층(130)을 일체로 적층 인쇄한후 그 일측에 에폭시 계열의 아지노모토(AJINOMOTO) 제품으로 50㎛및 75㎛의 두께로 규격화 되어 생산되는 반경화 상태의 드라이 필름을 적층한다.The copper foil layer 130 is integrally laminated and printed on the first insulating layer 120 so as to have a thickness of 35 μm, and then, on one side thereof, an epoxy-based AJINOMOTO product is standardized to a thickness of 50 μm and 75 μm. The dry film of the semi-hardened state is laminated | stacked.

그리고, 상기 드라이 필름을 40~60℃에서 170~190kg/㎠압력으로 10~20초간 가압착하고, 이어서 상기 드라이 필름을 140~160℃의 온도에서 170~190kg/㎠의 압력으로 10`20초간 압착하고, 상기 드라이 필름의 압착이 완료되면 150℃의 온도로 10~20초 동안 건조하여 제2절연층(140)을 형성한다.Then, the dry film is pressed for 10 to 20 seconds at a pressure of 170 to 190 kg / cm 2 at 40 to 60 ° C, and the dry film is pressed at 10 to 20 seconds at a pressure of 170 to 190 kg / cm 2 at a temperature of 140 to 160 ° C. In addition, when the pressing of the dry film is completed, the second insulating layer 140 is formed by drying at a temperature of 150 ° C. for 10 to 20 seconds.

상기 드라이 필름층(140)에 동(cu) 재질로서 25㎛의 두께를 갖는 전극층(150)을 인쇄에 의해 적층형성하여 적층 기판을 완성한다.An electrode layer 150 having a thickness of 25 μm as a cu material is formed on the dry film layer 140 by printing to complete a laminated substrate.

이때, 상기 제2절연층(140)은, 정형화 되어 생산되는 반경화 상태의 드라이 필름을 가압에 의해 적층 접합하여 종래의 일정두께를 갖는 절연층의 형성을 위하여 인쇄를 반복 수행할때 발생되는 숙련도의 차이에 의한 절연층의 두께편차를 ±15㎛ 에서 ±5㎛로 줄일수 있어 그 차이에 의한 저항의 불일치로 인한 신호의 반사 및 타입 딜레이를 미연에 방지토록 하게 되는 것이다.In this case, the second insulating layer 140 is a proficiency generated when the printing is repeatedly performed to form an insulating layer having a predetermined thickness by laminating and bonding a semi-cured dry film produced by shaping by pressing. The thickness deviation of the insulating layer due to the difference can be reduced from ± 15 μm to ± 5 μm to prevent the reflection of the signal and the type delay due to the mismatch of the resistance caused by the difference.

이상과 같이 본 발명에 따른 적층기판에 의하면, 작업자의 숙련도에 상관없이 도포두께의 편차 발생이 방지되어 신호의 반사가 없고, 인쇄회로기판에 실장되는 부품의 설계저항과 인쇄회로기판의 설계저항이 일치하여 정확한 신호전송이 이루어지며, 고속전송이 가능하게 하는 등의 우수한 효과가 있는 것이다.As described above, according to the laminated board according to the present invention, the variation of the coating thickness is prevented regardless of the skill of the operator, there is no signal reflection, and the design resistance of the component mounted on the printed circuit board and the design resistance of the printed circuit board are In accordance with the accurate signal transmission is made, high speed transmission is possible, such as excellent effects.

Claims (4)

상하측면에 전극패턴이 적층형성되며, 제1절연층이 상하측에 적층되는 복수의 CCL과,A plurality of CCLs in which electrode patterns are stacked on upper and lower surfaces, and a first insulating layer is stacked on upper and lower sides; 상기 절연층의 일측에 적층되는 동박층및Copper foil layer laminated on one side of the insulating layer and 상기 동박층에 드라이 필름을 가압,건조에 의해 적층하는 제2절연층과,A second insulating layer laminated on the copper foil layer by pressing and drying the dry film; 상기 제2절연층에 적층되는 전극층을 포함하여 구성되는 것을 특징으로 하는 적층 기판A laminated substrate comprising an electrode layer laminated on the second insulating layer 제 1항에 있어서, 상기 제2절연층은, 에폭시 계열의 드라이 필름으로 이루어 지는 것을 특징으로 하는 적층 기판The laminated substrate of claim 1, wherein the second insulating layer is formed of an epoxy-based dry film. 제 2항에 있어서, 상기 제2절연층은, 170~190Kg/㎠ 의 압력으로 40~70℃의 온도로 10~20초간 가압착 한후 140~160℃의 온도로 10~20초간 압착하여 적층형성되는 것을 특징으로 하는 적층 기판The method of claim 2, wherein the second insulating layer is press-bonded at a temperature of 40 to 70 ° C. for 10 to 20 seconds at a pressure of 170 to 190 Kg / cm 2, and then pressed at a temperature of 140 to 160 ° C. for 10 to 20 seconds to form a laminate. Laminated substrate, characterized in that 제 1항에 있어서, 상기 제2절연층은, 140~160℃의 온도로 10~20초간 건조하여 적층형성되는 것을 특징으로 하는 적층 기판The laminated substrate of claim 1, wherein the second insulating layer is laminated by drying at a temperature of 140 ° C. to 160 ° C. for 10 to 20 seconds.
KR1019990058792A 1999-12-17 1999-12-17 Build-up substrate KR100349123B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100645613B1 (en) * 2004-08-16 2006-11-15 삼성전기주식회사 A printed circuit board with embedded capacitors, and a manufacturing process thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3311450B2 (en) * 1993-12-28 2002-08-05 イビデン株式会社 Method of manufacturing multilayer printed wiring board and multilayer printed wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100645613B1 (en) * 2004-08-16 2006-11-15 삼성전기주식회사 A printed circuit board with embedded capacitors, and a manufacturing process thereof

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