KR20010056788A - Method for fabricating soi substrate - Google Patents
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- KR20010056788A KR20010056788A KR1019990058397A KR19990058397A KR20010056788A KR 20010056788 A KR20010056788 A KR 20010056788A KR 1019990058397 A KR1019990058397 A KR 1019990058397A KR 19990058397 A KR19990058397 A KR 19990058397A KR 20010056788 A KR20010056788 A KR 20010056788A
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 68
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000005498 polishing Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000227 grinding Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 19
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000007654 immersion Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract 6
- 238000007254 oxidation reaction Methods 0.000 abstract 6
- 230000003746 surface roughness Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 210000000988 bone and bone Anatomy 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 에스오아이(SOI) 기판의 제조방법에 관한 것으로, 특히, 반도체층의 표면 거칠기를 개선하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a SOI substrate, and more particularly, to a method for improving the surface roughness of a semiconductor layer.
반도체 소자의 고집적화 및 고성능화가 진행됨에 따라, 벌크 실리콘으로 이루어진 실리콘 기판을 대신하여 에스오아이(SOI : Silicon On Insulator) 기판을 이용한 반도체 집적 기술이 주목되고 있다. 상기 SOI 기판은 지지 수단인 베이스 기판과 소자가 형성될 반도체층 사이에 매몰산화막이 개재된 구조로서, 이러한 SOI 기판 상에 형성된 반도체 소자는 접합 용량(junction capacitance)의 감소에 따른 고속화 및 완전한 소자 분리에 따른 래치 업(latch-up) 감소 등의 장점을 갖는다.As high integration and high performance of semiconductor devices have progressed, semiconductor integration technologies using a silicon on insulator (SOI) substrate have been attracting attention instead of a silicon substrate made of bulk silicon. The SOI substrate has a structure in which a buried oxide film is interposed between a base substrate, which is a supporting means, and a semiconductor layer, on which the device is to be formed. This has the advantage of reducing the latch-up (latch-up).
상기 SOI 기판을 제조하기 위한 방법으로서는, 산소 이온주입을 이용하는 SIMOX(seperation by implanted oxygen)법과, 두장의 실리콘 기판을 매몰산화막의 개재하에 본딩시키는 본딩법이 이용되어져 왔다. 그런데, 상기 SIMOX법을 이용한 SOI 기판의 제조방법은 소자가 형성될 반도체층의 두께 조절이 어렵고, 또한, 제조 시간이 길다는 단점이 있기 때문에, 최근에는 본딩법을 이용한 SOI 기판의 제조방법이 주로 이용되고 있다.As a method for manufacturing the SOI substrate, a SIMOX (seperation by implanted oxygen) method using oxygen ion implantation and a bonding method of bonding two silicon substrates under the buried oxide film are used. However, since the method of manufacturing the SOI substrate using the SIMOX method has a disadvantage in that it is difficult to control the thickness of the semiconductor layer on which the device is to be formed and the manufacturing time is long, recently, the method of manufacturing the SOI substrate using the bonding method is mainly used. It is used.
본딩법을 이용한 SOI 기판의 제조방법을 간략하게 설명하면, 우선, 지지 수단인 베이스 기판, 또는, 반도체층을 얻기 위한 반도체 기판 중에서 어느 하나의 기판에 매몰산화막을 형성하고, 이어서, 매몰산화막의 개재하에 베이스 기판과 반도체 기판을 본딩시킨다. 그런다음, 반도체 기판 후면의 일부 두께를 공지된 기술인 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정으로 제거하여, 소자가 형성될 반도체층을 얻는다.Briefly describing a method for manufacturing an SOI substrate using the bonding method, first, an investment oxide film is formed on any one of a base substrate as a support means or a semiconductor substrate for obtaining a semiconductor layer, and then intervening the investment oxide film. The base substrate and the semiconductor substrate are bonded together. Then, a part of the thickness of the back surface of the semiconductor substrate is removed by a known technique called Chemical Mechanical Polishing (CMP) to obtain a semiconductor layer on which the device is to be formed.
한편, 본딩법을 이용한 SOI 기판의 제조방법에 있어서는 CMP 공정시에 연마정지층이 없기 때문에 원하는 두께의 반도체층을 얻는데, 그 곤란함이 있다. 따라서, 이러한 문제를 해결하기 위하여, 반도체 기판 내에 트렌치형 소자 분리막을 구비시키고, 이후, 상기 트렌치형 소자 분리막을 연마정지층으로 하는 CMP 공정을 수행하여, 원하는 두께의 반도체층이 얻어지도록 하는 방법이 제안되었다.On the other hand, in the manufacturing method of the SOI substrate using the bonding method, since there is no polishing stop layer during the CMP process, it is difficult to obtain a semiconductor layer having a desired thickness. Therefore, in order to solve such a problem, a method is provided in which a trench type device isolation film is provided in a semiconductor substrate, and thereafter, a CMP process using the trench type device isolation film as a polishing stop layer is performed to obtain a semiconductor layer having a desired thickness. Proposed.
도 1a 및 도 1b는 종래 기술에 따른 SOI 기판의 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A and 1B are cross-sectional views illustrating a method for manufacturing a SOI substrate according to the prior art, which will be described below.
먼저, 도 1a에 도시된 바와 같이, 벌크 실리콘으로 이루어진 반도체 기판(1)을 마련하고, 상기 반도체 기판(1)의 표면에 소정 깊이의 트렌치를 형성한 후, 상기 트렌치 내에 산화막을 매립시켜, 트렌치형의 소자분리막(2)을 형성한다. 여기서, 상기 트랜치는 소자가 형성될 반도체층의 두께와 유사한 깊이를 갖도록 형성한다. 그런다음, 상기 결과물 상에 매몰산화막(3)를 형성한다.First, as shown in FIG. 1A, a semiconductor substrate 1 made of bulk silicon is provided, a trench having a predetermined depth is formed on the surface of the semiconductor substrate 1, and then an oxide film is embedded in the trench to form a trench. Device isolation film 2 is formed. The trench is formed to have a depth similar to the thickness of the semiconductor layer on which the device is to be formed. Then, the buried oxide film 3 is formed on the resultant.
다음으로, 도 1b에 도시된 바와 같이, 매몰산화막(3) 상에 베이스 기판(4)을 본딩시키고, 이어서, 상기 반도체 기판의 후면을 그라인딩(grinding) 및 스핀 식각한 후, 연이어서, 상기 트렌치형의 소자분리막(2)을 연마정지층으로 하는 CMP 공정으로 그라인딩 및 스핀 식각된 상기 반도체 기판의 후면을 연마하여 반도체층(1a)을 얻으며, 이 결과로, 소자 분리막(2)을 갖는 SOI 기판(10)을 완성한다.Next, as illustrated in FIG. 1B, the base substrate 4 is bonded onto the buried oxide film 3, and then the back surface of the semiconductor substrate is ground and spin-etched, followed by the trenches. The semiconductor layer 1a is obtained by polishing the back surface of the semiconductor substrate that is ground and spin-etched by the CMP process using the device isolation film 2 as the polishing stop layer. As a result, the SOI substrate having the device isolation film 2 is obtained. Complete (10).
그러나, 상기와 같은 종래의 SOI 기판의 제조방법에 있어서는, 그라인딩, 식각 및 연마에 의해 얻어지는 반도체층의 표면 거칠기가 불량한 것에 기인하여, 상기 반도체층에 형성되는 트랜지스터와 같은 소자의 특성이 저하되는 문제점이 있다.However, in the conventional method for manufacturing a SOI substrate as described above, the surface roughness of the semiconductor layer obtained by grinding, etching and polishing is poor, resulting in deterioration of characteristics of devices such as transistors formed in the semiconductor layer. There is this.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 양호한표면 거칠기를 갖는 반도체층을 얻을 수 있는 SOI 기판의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for producing an SOI substrate which can obtain a semiconductor layer having good surface roughness.
도 1a 및 도 1b는 종래 기술에 따른 에스오아이 기판의 제조방법을 설명하기 위한 공정 단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a S-OI substrate according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 에스오아이 기판의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing an SOH substrate according to an exemplary embodiment of the present invention.
도 3은 도 2c의 A 부분을 확대한 단면도.3 is an enlarged cross-sectional view of portion A of FIG. 2C;
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 반도체 기판 11a : 반도체층11 semiconductor substrate 11a semiconductor layer
12 : 트렌치형 소자분리막 13 : 매몰산화막12: trench type isolation layer 13: investment oxide film
14 : 베이스 기판 15 : 자연산화막14 base substrate 15 natural oxide film
20 : 에스오아이 기판20: S.O.I.substrate
상기와 같은 목적을 달성하기 위한 본 발명의 SOI 웨이퍼의 제조방법은, 일측면에 트렌치형의 소자분리막이 구비된 반도체 기판을 제공하는 단계; 상기 트렌치형의 소자분리막을 포함한 상기 반도체 기판의 일측면 상에 매몰산화막을 형성하는 단계; 상기 매몰산화막 상에 베이스 기판을 본딩시키는 단계; 상기 반도체 기판의 타측면을 순차적으로 그라인딩, 식각 및 연마해서 반도체층을 형성하는 단계; 상기 반도체층의 표면에 습식 처리를 통해 자연산화막을 형성하는 단계; 상기 자연산화막을 제거하는 단계; 상기 반도체층의 표면에 열 공정을 통해 열산화막을 형성하는 단계; 및 상기 열산화막을 제거하는 단계를 포함한다.SOI wafer manufacturing method of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a trench type device isolation film on one side; Forming a buried oxide film on one side of the semiconductor substrate including the trench isolation device; Bonding a base substrate on the investment oxide layer; Sequentially grinding, etching and polishing the other side of the semiconductor substrate to form a semiconductor layer; Forming a natural oxide film on the surface of the semiconductor layer through a wet treatment; Removing the natural oxide film; Forming a thermal oxide film on a surface of the semiconductor layer through a thermal process; And removing the thermal oxide film.
상기에서, 상기 반도체층의 표면에 자연산화막을 형성시키기 위한 습식 처리는, 상기 SOI 기판을 H2O2를 포함한 케미컬, 핫 디아이 워터(Hot DI Water), 또는, 상기 H2O2를 포함한 케미컬과 핫 디아이 워터(Hot DI Water)의 혼합 용액에 30 내지 60분 정도 침적시키는 것을 통해 수행된다.In the above, the wet treatment for forming a natural oxide film on the surface of the semiconductor layer, the SOI substrate is a chemical containing H 2 O 2 , hot DI water, or the chemical containing the H 2 O 2 It is carried out by immersing in a mixed solution of hot DI water (Hot DI Water) for about 30 to 60 minutes.
본 발명에 따르면, 반도체층의 표면에 자연산화막을 형성한 후, 이를 제거하고, 이어서, 상기 반도체층의 표면에 열산화막을 형성한 후, 이를 제거함으로써, 상기 반도체층의 표면 거칠기를 개선시킬 수 있다.According to the present invention, after forming a natural oxide film on the surface of the semiconductor layer, and then removing it, and subsequently forming a thermal oxide film on the surface of the semiconductor layer, by removing it, it is possible to improve the surface roughness of the semiconductor layer have.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 SOI 기판의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing an SOI substrate according to an exemplary embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)의 일측면에 공지된 방법으로 트렌치형의 소자분리막(12)을 형성하고, 상기 소자분리막(12)을 포함한 반도체 기판(11)의 일측면 상에 매몰산화막(13)을 형성한 후, 상기 매몰산화막(13) 상에 베이스 기판(14)을 본딩시킨다.First, as shown in FIG. 2A, a trench type device isolation film 12 is formed on one side of the semiconductor substrate 11 by a known method, and one of the semiconductor substrates 11 including the device isolation film 12 is formed. After the buried oxide film 13 is formed on the side surface, the base substrate 14 is bonded on the buried oxide film 13.
그 다음, 도 2b에 도시된 바와 같이, 트렌치형의 소자분리막(12)에 인접된 부분까지 반도체 기판의 타측면을 그라인딩 및 스핀 식각하여 그 일부 두께를 제거하고, 연이어서, 트렌치형의 소자분리막(12)을 연마정지층으로 하는 CMP 공정을 통해 상기 반도체 기판의 타측면을 연마하여 반도체층(11a)을 형성한다. 이 결과, SOI 기판(20)이 얻어진다. 여기서, 상기 반도체층(11a)의 표면 거칠기는 종래 기술에서 설명한 바와 같이 매우 불량하다.Next, as shown in FIG. 2B, the other side of the semiconductor substrate is ground and spin-etched to a portion adjacent to the trench type device isolation film 12 to remove a part thickness thereof, and subsequently, a trench type device isolation film. The semiconductor layer 11a is formed by polishing the other side of the semiconductor substrate through the CMP process using the polishing stop layer 12 as the polishing stop layer. As a result, the SOI substrate 20 is obtained. Here, the surface roughness of the semiconductor layer 11a is very poor as described in the prior art.
다음으로, 도 2c에 도시된 바와 같이, 반도체층(11a)의 표면 거칠기를 개선하기 위하여, 상기 SOI 기판(20)을 H2O2포함한 케미컬, 핫 디아이 워터(Hot DI Water), 또는, 상기 H2O2를 포함한 케미컬과 핫 디아이 워터(Hot DI Water)의 혼합 용액에 30 내지 60분 정도 침적시켜, 상기 반도체층(11a)의 표면에 20 내지 30Å 두께의 자연산화막(15)을 형성시킨다. 이때, 상기 H2O2포함한 케미컬을 이용할 경우, 그 온도는 50 내지 80℃로 유지시키고, 상기 핫 디아이 워터(Hot DI Water)를이용할 경우, 그 온도는 50 내지 90℃로 유지시킨다.Next, as shown in FIG. 2C, in order to improve the surface roughness of the semiconductor layer 11a, the SOI substrate 20 includes chemical, hot DI water, or H 2 O 2. It is immersed for about 30 to 60 minutes in a mixed solution of the chemical containing H 2 O 2 and Hot DI Water to form a natural oxide film 15 having a thickness of 20 to 30 에 on the surface of the semiconductor layer 11a. . At this time, when using the chemical including the H 2 O 2 , the temperature is maintained at 50 to 80 ℃, when using the hot DI water (Hot DI Water), the temperature is maintained at 50 to 90 ℃.
그리고나서, 도 2d에 도시된 바와 같이, 100:1의 비율로 혼합된 HF 용액을 이용한 습식 식각 공정을 수행하여 상기 반도체층(11a)의 표면에 형성된 자연산화막을 제거하고, 이어서, 700 내지 1,000℃에서 열 공정을 수행하여 상기 반도체층(11a)의 표면에 50 내지 200Å 두께로 열산화막(도시안됨)을 형성한 후, 다시, HF 용액을 이용한 습식 식각 공정으로 상기 열산화막을 제거하여, 개선된 표면 거칠기를 갖는 반도체층(11a)을 얻는다.Then, as shown in Figure 2d, by performing a wet etching process using a HF solution mixed in a ratio of 100: 1 to remove the natural oxide film formed on the surface of the semiconductor layer (11a), then 700 to 1,000 A thermal oxide film (not shown) is formed on the surface of the semiconductor layer 11a to a thickness of 50 to 200Å by performing a thermal process at ℃, and then, the thermal oxide film is removed by a wet etching process using an HF solution. The semiconductor layer 11a which has the obtained surface roughness is obtained.
자세하게, 상기 SOI 기판(20)을 H2O2를 포함한 케미컬, 또는, 핫 디아이 워터에 침적시키게 되면, 도 3에 도시된 바와 같이, 골 부분(B)은 산 부분(C)에 비해 자연산화막(15)의 형성이 적게 일어나기 때문에, 후속에서 HF 용액으로 상기 자연산화막을 제거하게 되면, 산 부분(C)은 골 부분(B)에 비해 상대적으로 많이 제거된다. 마찬가지로, 자연산화막이 제거된 상태에서 열공정을 수행하게 되면, 도시하지는 않았으나, 산 부분은 골 부분 보다 상대적으로 열산화막의 형성이 많이 일어나므로, 후속에서 HF 용액을 이용한 열산화막의 제거가 이루어지면, 상기 산 부분은 상기 골 부분 보다 상대적으로 많이 제거된다.In detail, when the SOI substrate 20 is immersed in a chemical including H 2 O 2 or hot die water, as shown in FIG. 3, the bone portion B is formed of a natural oxide film compared to the acid portion C. Since less formation of (15) occurs, when the natural oxide film is subsequently removed with the HF solution, the acid portion C is removed relatively more than the bone portion B. Similarly, when the thermal process is performed in a state where the natural oxide film is removed, although not shown, since the acid portion is formed more thermally than the bone portion, the thermal oxide film is subsequently removed using HF solution. The acid portion is removed relatively more than the valley portion.
그러므로, 자연산화막의 형성 및 제거, 그리고, 열산화막의 형성 및 제거를 거치는 동안, 반도체층의 표면은 평탄하게 되며, 결과적으로는, 양호한 표면 거칠기를 갖는 반도체층(11a)이 얻어진다.Therefore, during the formation and removal of the natural oxide film and the formation and removal of the thermal oxide film, the surface of the semiconductor layer becomes flat, and as a result, the semiconductor layer 11a having a good surface roughness is obtained.
한편, 열 공정을 수행하여 열산화막을 형성하고, 이를 제거할 경우에는 상기반도체층의 실질적인 두께가 감소하게 된다. 따라서, 이러한 반도체층의 두께 감소를 방지하기 위해서는, 트렌치형 소자분리막의 형성시, 트렌치의 깊이를 상기 열산화막의 두께를 고려한 깊이로 형성함이 바람직하다.On the other hand, when performing a thermal process to form a thermal oxide film, and removing it, the substantial thickness of the semiconductor layer is reduced. Therefore, in order to prevent such a reduction in the thickness of the semiconductor layer, it is preferable to form the depth of the trench in consideration of the thickness of the thermal oxide film when forming the trench type isolation layer.
이상에서와 같이, 본 발명은 그라인딩 및 식각 공정과 CMP 공정을 통해 반도체층을 형성한 상태에서, 상기 반도체층의 표면에 자연산화막의 형성 및 상기 자연산화막의 제거와 열산화막의 형성 및 상기 열산화막의 제거를 순차적으로 수행하는 것을 통해 상기 반도체층의 표면 거칠기를 개선시킬 수 있다.As described above, the present invention is the formation of the natural oxide film on the surface of the semiconductor layer, the removal of the natural oxide film and the formation of the thermal oxide film and the thermal oxide film in the state of forming the semiconductor layer through the grinding and etching process and the CMP process The surface roughness of the semiconductor layer may be improved by sequentially removing the semiconductor layer.
따라서, 양호한 표면 거칠기를 갖는 반도체층을 얻을 수 있기 때문에, 상기 반도체층에 형성되는 소자의 특성을 향상시킬 수 있다.Therefore, since the semiconductor layer which has favorable surface roughness can be obtained, the characteristic of the element formed in the said semiconductor layer can be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한, 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (7)
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| KR1019990058397A KR20010056788A (en) | 1999-12-16 | 1999-12-16 | Method for fabricating soi substrate |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0395912A (en) * | 1989-09-07 | 1991-04-22 | Sony Corp | Manufacture of semiconductor substrate |
| JPH0555357A (en) * | 1991-08-27 | 1993-03-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR970052020A (en) * | 1995-12-30 | 1997-07-29 | 김주용 | SOH eye substrate manufacturing method |
| JPH09260620A (en) * | 1996-03-25 | 1997-10-03 | Shin Etsu Handotai Co Ltd | Manufacture of coupled wafer and coupled wafer manufactured by this method |
-
1999
- 1999-12-16 KR KR1019990058397A patent/KR20010056788A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0395912A (en) * | 1989-09-07 | 1991-04-22 | Sony Corp | Manufacture of semiconductor substrate |
| JPH0555357A (en) * | 1991-08-27 | 1993-03-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR970052020A (en) * | 1995-12-30 | 1997-07-29 | 김주용 | SOH eye substrate manufacturing method |
| JPH09260620A (en) * | 1996-03-25 | 1997-10-03 | Shin Etsu Handotai Co Ltd | Manufacture of coupled wafer and coupled wafer manufactured by this method |
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