KR20010027365A - Method for manufacturing semiconductor device having barrier metal layer - Google Patents
Method for manufacturing semiconductor device having barrier metal layer Download PDFInfo
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- KR20010027365A KR20010027365A KR1019990039069A KR19990039069A KR20010027365A KR 20010027365 A KR20010027365 A KR 20010027365A KR 1019990039069 A KR1019990039069 A KR 1019990039069A KR 19990039069 A KR19990039069 A KR 19990039069A KR 20010027365 A KR20010027365 A KR 20010027365A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000004888 barrier function Effects 0.000 title abstract description 24
- 229910052751 metal Inorganic materials 0.000 title abstract description 24
- 239000002184 metal Substances 0.000 title abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 4
- 238000005240 physical vapour deposition Methods 0.000 abstract description 78
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 76
- 239000010936 titanium Substances 0.000 abstract description 75
- 239000010410 layer Substances 0.000 abstract description 43
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052719 titanium Inorganic materials 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 27
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 6
- 229910052801 chlorine Inorganic materials 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 238000006396 nitration reaction Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 241000283707 Capra Species 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 티타늄(Ti)막과 질화티타늄(TiN)막을 포함하는 베리어 메탈층(barrier metal layer)을 갖춘 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a barrier metal layer including a titanium (Ti) film and a titanium nitride (TiN) film.
반도체 소자의 금속 배선에 필요한 금속 콘택 플러그(metal contact plug)를 형성할 때, 콘택홀을 채우는 금속 물질, 예를 들면 텅스텐(W)의 불량한 접착 특성을 향상시키기 위하여 통상적으로 Ti/TiN 구조를 갖는 배리어 메탈층을 채용한다.When forming a metal contact plug required for metal wiring of a semiconductor device, in order to improve the poor adhesion characteristics of the metal material filling the contact hole, for example, tungsten (W), it is usually of a Ti / TiN structure A barrier metal layer is adopted.
종래에는, Ti/TiN 구조를 갖는 배리어 메탈층을 형성하기 위하여 스퍼터링 방법과 같은 PVD(Physical Vapor Deposition) 방법을 이용하였다. 그러나, PVD 방법에 의하여 형성된 Ti/TiN막은 스텝 커버리지가 불량하다. 따라서, 아스펙트 비(aspect ratio)가 큰 콘택을 형성하는 경우에는 Ti/TiN막을 접착층 또는 배리어층으로 적용하였을 때 콘택홀의 입구에서 Ti/TiN막의 오버행(overhang)이 심하게 발생되고, 그 결과로서 후속의 텅스텐 증착 공정시 콘택 내에 큰 보이드(void)가 형성된다. 또한, Ti/TiN막의 불량한 스텝 커버리지로 인하여 콘택의 저면에서 Ti/TiN막의 두께가 너무 얇아지게 되면 후속의 텅스텐 증착 공정시 소스 가스로 사용되는 WF6가스와 Ti/TiN막의 Ti가 반응하여 부도체를 형성하거나 일부 기화된다. 그 결과, TiN막이 리프트(lift)되어 벗겨지는 현상이 발생된다. 이와 같은 현상이 발생되면 Ti/TiN막이 WF6가스에 대하여 배리어 역할을 할 수 없게 된다.Conventionally, a physical vapor deposition (PVD) method such as a sputtering method is used to form a barrier metal layer having a Ti / TiN structure. However, the Ti / TiN film formed by the PVD method has poor step coverage. Therefore, in the case of forming a contact having a large aspect ratio, when the Ti / TiN film is applied as an adhesive layer or a barrier layer, an overhang of the Ti / TiN film occurs severely at the inlet of the contact hole. Large voids are formed in the contact during the tungsten deposition process. In addition, if the thickness of the Ti / TiN film becomes too thin at the bottom of the contact due to the poor step coverage of the Ti / TiN film, the WF 6 gas, which is used as the source gas during the subsequent tungsten deposition process, reacts with the Ti of the Ti / TiN film to form an insulator. Formed or partially vaporized. As a result, a phenomenon in which the TiN film is lifted and peeled off occurs. When such a phenomenon occurs, the Ti / TiN film cannot act as a barrier to the WF 6 gas.
따라서, 최근에는 PVD 방법에 의하여 형성된 Ti막 위에 CVD(Chemical Vapor Deposition) 방법에 의하여 TiN막을 형성하여 PVD Ti/CVD TiN 스택 구조의 배리어 메탈층(barrier metal layer)을 형성하는 공정이 개발되어 양산에 적용되고 있다.Therefore, in recent years, a TiN film is formed on the Ti film formed by the PVD method by a chemical vapor deposition (CVD) method to form a barrier metal layer having a PVD Ti / CVD TiN stack structure. Is being applied.
특히, TiCl4가스를 사용하여 CVD 방법에 의하여 TiN막을 형성하는 방법은 우수한 스텝 커버리지를 가지는 TiN막을 얻을 수 있기 때문에 금속 콘택 또는 커패시터를 형성할 때 금속막의 접착층(glue layer) 또는 배리어 메탈층을 형성하는 방법으로서 많이 채용된다.In particular, since the TiN film is formed by the CVD method using TiCl 4 gas, a TiN film having excellent step coverage can be obtained, thereby forming a glue layer or a barrier metal layer when forming a metal contact or capacitor. It is employ | adopted a lot as a method to do it.
통상적으로, 소스 가스로서 TiCl4가스를 사용하여 CVD 방법에 의하여 형성된 TiN막 내에는 다량의 염소를 함유하게 된다. 이와 같이 염소 함량이 높은 TiN막은 높은 비저항을 나타낸다. 또한, 염소가 하지막인 Ti막으로 침투하여 Ti막을 손상시키게 되므로 Ti막에 대하여 고온의 RTN(Rapid Thermal Nitration) 처리 또는 NH3플라즈마 처리를 행하지 않으면 안된다.Typically, a large amount of chlorine is contained in the TiN film formed by the CVD method using TiCl 4 gas as the source gas. As such, the TiN film having a high chlorine content exhibits high specific resistance. In addition, since chlorine penetrates into the Ti film, which is the underlying film, to damage the Ti film, a high temperature RTN (Rapid Thermal Nitration) or NH 3 plasma treatment must be performed on the Ti film.
상기와 같이 Ti막에 대하여 고온의 RTN 처리 또는 NH3플라즈마 처리를 행하는 경우에는 다음과 같은 문제점이 발생된다.As described above, when the high temperature RTN treatment or the NH 3 plasma treatment is performed on the Ti film, the following problems arise.
첫째, 상기와 같은 처리 공정의 추가로 인하여 공정 수가 증가하고 반도체 소자의 제조 공정이 복잡해진다.First, the addition of such a treatment process increases the number of processes and complicates the manufacturing process of the semiconductor device.
둘째, 상기 처리 공정의 추가로 인하여 별도의 설비를 도입하여야 하며, 그 결과 설비 투자의 부담이 증가된다.Second, a separate facility must be introduced due to the addition of the above treatment process, which increases the burden of facility investment.
셋째, 반도체 소자에서 섈로우 정크션을 구현하고자 하는 것이 최근의 추세이며, 따라서 콘택홀 내부에 배리어막으로서 증착되는 Ti막의 허용 두께가 제한되고 있다. 그러나, 고온의 RTN 처리 또는 NH3플라즈마 처리에 의하여 Ti막 내에서 상당량의 Ti가 소모되는 결과가 초래된다. 그 결과, 잔류 Ti의 양이 적어지게 되어 안정된 콘택 저항을 확보할 수 없는 문제가 있다.Third, there is a recent trend to implement a hollow junction in a semiconductor device, and thus the allowable thickness of the Ti film deposited as a barrier film inside the contact hole is limited. However, high temperature RTN treatment or NH 3 plasma treatment results in the consumption of a significant amount of Ti in the Ti film. As a result, the amount of residual Ti becomes small, and there exists a problem which cannot secure stable contact resistance.
넷째, Ti막은 PVD 방법으로 증착하고 TiN막은 CVD 방법으로 증착하는 경우에 정상적인 콘택 저항을 얻기 위하여는 콘택의 저면 부위에 PVD Ti막을 특정 두께 이상 증착하여야 한다는 제한이 따르게 된다. 미세 콘택을 형성하는 경우 또는 아스펙트비(aspect ratio)가 큰 콘택을 형성하는 경우에는, 얻을 수 있는 스텝 커버리지(step coverage)를 고려한다면 콘택의 저면에서 필요한 PVD Ti막 두께를 얻기 위하여 웨이퍼상에 증착해야 할 PVD Ti막의 두께가 더욱 증가하게 된다. 예를 들면, 아스펙트비가 5 이상인 경우 얻어질 수 있는 스텝 커버리지는 10% 정도에 불과하며, 이 때 콘택 저면 부근에서 100Å 두께의 Ti막을 얻기 위하여 웨이퍼상에는 1000Å 이상의 Ti막을 증착하여야 한다. 그 결과, 콘택 플러그 형성에 필요한 배리어 메탈층을 형성할 때 스텝 커버리지를 개선하고자 하였던 당초의 의도가 무의미하게 된다.Fourth, when the Ti film is deposited by the PVD method and the TiN film is deposited by the CVD method, there is a restriction that a PVD Ti film must be deposited over a certain thickness in order to obtain normal contact resistance. In the case of forming a fine contact or in forming a contact having a large aspect ratio, considering the step coverage obtainable, the wafer is formed on the wafer to obtain the required PVD Ti film thickness at the bottom of the contact. The thickness of the PVD Ti film to be deposited is further increased. For example, when the aspect ratio is 5 or more, the step coverage that can be obtained is only about 10%. At this time, a Ti film of 1000 mW or more must be deposited on the wafer in order to obtain a 100 mW thick Ti film near the bottom of the contact. As a result, the original intention of improving the step coverage when forming the barrier metal layer required for forming the contact plug becomes meaningless.
본 발명의 목적은 상기한 종래 기술에서의 문제를 해결하고자 하는 것으로, CVD TiN 형성시 하부의 Ti막의 손상을 억제할 수 있는 구조를 가지는 베리어 메탈층을 갖춘 반도체 소자의 제조 방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems in the prior art, and to provide a method for manufacturing a semiconductor device having a barrier metal layer having a structure capable of suppressing damage to a lower Ti film during CVD TiN formation.
본 발명의 다른 목적은 배리어 메탈층을 얇은 두께로 형성하여도 콘택 저면에서 정상적인 콘택 저항을 얻는 것이 가능한 반도체 소자의 제조 방법을 제공하는 것이다.Another object of the present invention is to provide a method for manufacturing a semiconductor device which can obtain a normal contact resistance at the bottom of a contact even when the barrier metal layer is formed to a thin thickness.
도 1a 내지 도 1d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10: 반도체 기판, 12: 층간절연막, 20: 배리어 메탈층, 22: PVD Ti막, 24: PVD TiN막, 26: CVD TiN막, 30: 도전층10 semiconductor substrate, 12 interlayer insulating film, 20 barrier metal layer, 22 PVD Ti film, 24 PVD TiN film, 26 CVD TiN film, 30 conductive layer
상기 목적들을 달성하기 위하여, 본 발명에 따른 반도체 소자의 제조 방법에서는 PVD 챔버 내에서 반도체 기판상의 도전 영역을 노출시키는 콘택홀의 저면 및 측벽에 PVD Ti막을 형성한 후, 상기 PVD 챔버 내에서 상기 Ti막 형성 공정과 인-시튜(in-situ)로 진공 상태를 유지하면서 상기 Ti막 위에 연속적으로 PVD TiN막을 형성한다. 그 후, CVD 챔버 내에서 상기 PVD TiN막 위에 CVD TiN막을 형성한다.In order to achieve the above objects, in the method of manufacturing a semiconductor device according to the present invention, after forming a PVD Ti film on the bottom and sidewalls of a contact hole exposing a conductive region on a semiconductor substrate in a PVD chamber, the Ti film is formed in the PVD chamber. A PVD TiN film is continuously formed on the Ti film while maintaining a vacuum state in the formation process and in-situ. Thereafter, a CVD TiN film is formed on the PVD TiN film in a CVD chamber.
본 발명에 의하면, 아스팩트비가 큰 미세 콘택을 형성하는 경우에도 콘택의 저면에서 배리어 메탈층을 양호한 콘택 저항을 얻는 데 필요한 최소한의 두께로 형성하는 것이 가능하므로, 배리어 메탈층의 두께를 현저히 낮출 수 있으며, PVD Ti막 표면이 PVD TiN막에 의하여 덮여 있으므로, PVD Ti막이 염소에 의하여 손상되는 것을 방지할 수 있고, CVD TiN막 형성 전에 진공 상태가 해제되어도 대기중에서 거의 산화되지 않는 TiN막이 대기중에 노출되므로 자연산화막에 의한 콘택 저항 증가 현상을 방지할 수 있다.According to the present invention, even when forming a fine contact having a large aspect ratio, it is possible to form the barrier metal layer on the bottom of the contact to the minimum thickness necessary to obtain a good contact resistance, thereby significantly reducing the thickness of the barrier metal layer. Since the surface of the PVD Ti film is covered by the PVD TiN film, it is possible to prevent the PVD Ti film from being damaged by chlorine and to expose the TiN film to the atmosphere, which is hardly oxidized in the air even if the vacuum is released before the CVD TiN film is formed. Therefore, it is possible to prevent the increase in contact resistance caused by the natural oxide film.
다음에, 본 발명의 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
본 출원인은, 콘택 플러그 형성시 채용되는 배리어 메탈층을 종래 기술에서와 같이 PVD Ti/CVD TiN 구조로 형성하는 경우에 상기한 바와 같은 문제점을 발생시키는 원인으로서 다음과 같은 2가지 원인이 있음을 알아내었다.Applicant knows that the following two causes are caused when the barrier metal layer employed in forming the contact plug is formed in the PVD Ti / CVD TiN structure as in the prior art. Came out.
첫째, CVD TiN 증착시 사용되는 TiCl4가스에 의하여 PVD Ti막이 손상될 가능성이 크다.First, there is a high possibility that the PVD Ti film is damaged by the TiCl 4 gas used in CVD TiN deposition.
둘째, 종래 기술에서는 PVD Ti막을 형성한 후 CVD TiN막을 형성하기 전에 증착 챔버간 이동을 위하여 진공 상태를 해제하므로 PVD Ti막이 대기중에 노출될 때 상기 PVD Ti막 표면에 자연 산화막이 형성된다. 이 때 형성되는 자연 산화막에 의하여 콘택 저항이 크게 증가되는 것을 확인하였다.Second, in the prior art, after forming the PVD Ti film and before the CVD TiN film is formed, the vacuum state is released for movement between deposition chambers, so that a natural oxide film is formed on the surface of the PVD Ti film when the PVD Ti film is exposed to the air. It was confirmed that the contact resistance was greatly increased by the natural oxide film formed at this time.
따라서, 본 발명에서는 CVD TiN 증착시 TiCl4가스에 의하여 PVD Ti막이 손상되는 것을 방지하는 동시에, PVD Ti막이 대기중에 노출될 염려가 없도록 하기 위하여, PVD Ti막 형성 후 CVD TiN막 형성 전에 상기 PVD Ti막 형성 공정과 인-시튜(in-situ)로 상기 PVD Ti막 표면을 캡핑하는 PVD TiN막을 형성하는 방법을 제공한다.Therefore, in the present invention, in order to prevent the PVD Ti film from being damaged by TiCl 4 gas during CVD TiN deposition and to prevent the PVD Ti film from being exposed to the air, the PVD Ti is formed after the PVD Ti film is formed before the CVD TiN film is formed. A method of forming a PVD TiN film capping the surface of the PVD Ti film in a film forming process and in-situ is provided.
도 1a 내지 도 1d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
도 1a를 참조하면, 도전 영역(도시 생략)이 형성된 반도체 기판(10)상에 상기 도전 영역을 노출시키는 콘택홀(H)을 갖춘 층간절연막(12)을 형성한다.Referring to FIG. 1A, an interlayer insulating film 12 having a contact hole H exposing the conductive region is formed on a semiconductor substrate 10 on which a conductive region (not shown) is formed.
이어서, PVD 챔버 내에서 스퍼터링 방법을 이용하여 상기 결과물 전면에 Ti를 증착하여 상기 콘택홀(H)의 저면 및 측벽과 상기 층간절연막(12)의 상면에 PVD Ti막(22)을 형성한다. 이 때, 상기 PVD Ti막(22)은 상기 콘택홀(H)의 저면에서 약 5 ∼ 100Å, 바람직하게는 5 ∼ 15Å의 두께를 가지도록 형성하면 충분하다. 상기 콘택홀(H)의 아스펙트비가 5 정도이면 약 10%의 스텝 커버리지가 얻어지므로, 상기 PVD Ti막(22)이 상기 층간절연막(12)의 상면에서 약 100Å의 두께를 가지도록 증착하면 상기 콘택홀(H)의 저면에서 약 10Å의 두께를 가지는 PVD Ti막(22)을 얻을 수 있다.Subsequently, Ti is deposited on the entire surface of the resultant by sputtering in a PVD chamber to form a PVD Ti film 22 on the bottom and sidewalls of the contact hole H and the top surface of the interlayer insulating film 12. At this time, it is sufficient that the PVD Ti film 22 is formed to have a thickness of about 5 to 100 GPa, preferably 5 to 15 GPa at the bottom of the contact hole H. When the aspect ratio of the contact hole H is about 5, about 10% step coverage is obtained. Therefore, when the PVD Ti film 22 is deposited to have a thickness of about 100 GPa on the upper surface of the interlayer insulating film 12, At the bottom of the contact hole H, a PVD Ti film 22 having a thickness of about 10 GPa can be obtained.
도 1b를 참조하면, 상기 PVD Ti막(22) 형성시 이용된 PVD 챔버와 동일 챔버 내에서 상기 PVD Ti막(22) 위에 TiN을 스퍼터링 방법으로 증착하여 PVD TiN막(24)을 형성한다. 상기 PVD TiN막(24)은 상기 콘택홀(H)의 저면에서 약 5 ∼ 50Å, 바람직하게는 10 ∼ 20Å의 두께를 가지도록 형성한다.Referring to FIG. 1B, in the same chamber as the PVD chamber used to form the PVD Ti film 22, TiN is deposited on the PVD Ti film 22 by a sputtering method to form a PVD TiN film 24. The PVD TiN film 24 is formed to have a thickness of about 5 to 50 kPa, preferably 10 to 20 kPa at the bottom of the contact hole H.
상기 PVD TiN막(24) 형성 공정은 상기 PVD Ti막(22) 형성 공정과 일련의 공정으로서 인-시튜(in-situ)로 진공 상태를 유지하면서 연속적으로 행한다.The PVD TiN film 24 forming step is performed in series with the PVD Ti film 22 forming step while maintaining the vacuum state in-situ continuously.
상기 PVD TiN막(24)은 상기 PVD Ti막(22)의 표면을 보호하는 캡핑층 역할을 하는 것이다. 상기 PVD TiN막(24)은 대기중에 노출되어도 거의 산화되지 않는다. 따라서, 후속 공정을 위하여 대기중에 노출되었을 때 상기 PVD Ti막(22) 표면이 상기 PVD TiN막(24)에 의하여 덮여 있으므로 상기 PVD Ti막(22)의 표면이 산화되는 것을 방지할 수 있다.The PVD TiN film 24 serves as a capping layer protecting the surface of the PVD Ti film 22. The PVD TiN film 24 is hardly oxidized even when exposed to the atmosphere. Accordingly, since the surface of the PVD Ti film 22 is covered by the PVD TiN film 24 when exposed to the air for the subsequent process, the surface of the PVD Ti film 22 can be prevented from being oxidized.
또한, 상기 PVD Ti막(22) 표면이 상기 PVD TiN막(24)에 의하여 덮여 있으므로, 후속 공정에서 CVD 방법에 의하여 TiN막을 형성하기 위하여 TiCl4가스를 사용하여도 염소가 상기 PVD Ti막(22)으로 침투하는 것이 방지된다. 따라서, 상기 PVD Ti막(22)을 보호하기 위한 별도의 처리 단계, 예를 들면 상기 PVD Ti막(22)에 대한 고온의 RTN(Rapid Thermal Nitration) 처리 또는 NH3플라즈마 처리를 행할 필요가 없다.In addition, the PVD Ti film 22, the surface of the PVD because covered by the TiN film 24, the degree by using TiCl 4 gas to form a TiN film by the CVD method in the subsequent steps goat the PVD Ti film (22 Penetration is prevented. Therefore, there is no need to perform a separate processing step for protecting the PVD Ti film 22, for example, a high temperature rapid thermal nitration (RTN) process or an NH 3 plasma treatment on the PVD Ti film 22.
도 1c를 참조하면, CVD 챔버 내에서 TiCl4가스를 소스 가스로 사용하는 CVD 방법을 이용하여 PVD TiN막(24) 위에 TiN을 증착하여 CVD TiN막(26)을 형성한다. 이 때, 이미 설명한 바와 같이, 상기 PVD Ti막(22)은 상기 PVD TiN막(24)에 의하여 덮여 있으므로 염소가 상기 PVD Ti막(22)으로 침투하는 것이 방지된다.Referring to FIG. 1C, a CVD TiN film 26 is formed by depositing TiN on a PVD TiN film 24 using a CVD method using a TiCl 4 gas as a source gas in a CVD chamber. At this time, as described above, since the PVD Ti film 22 is covered by the PVD TiN film 24, chlorine is prevented from penetrating into the PVD Ti film 22.
이로써, 상기 PVD Ti막(22), PVD TiN막(24) 및 CVD TiN막(26)으로 이루어지는 배리어 메탈층(20)이 완성된다.As a result, the barrier metal layer 20 including the PVD Ti film 22, the PVD TiN film 24, and the CVD TiN film 26 is completed.
도 1d를 참조하면, 상기 결과물 전면에 예를 들면 W, Al, Cu와 같은 도전 물질을 PVD 또는 CVD 방법에 의하여 증착하여 도전층(30)을 형성한다.Referring to FIG. 1D, a conductive material such as, for example, W, Al, and Cu is deposited on the entire surface of the resultant by PVD or CVD to form a conductive layer 30.
상기와 같이, 본 발명에서는 반도체 소자 형성에 필요한 콘택 플러그를 형성하기 위하여 먼저 콘택홀 내에 PVD Ti막을 형성한 후 상기 PVD Ti막을 PVD TiN막으로 캡핑한 후 CVD TiN막을 형성함으로써, PVD Ti/PVD TiN/CVD TiN 스택 구조의 배리어 메탈층을 형성한다. 따라서, 아스팩트비가 큰 미세 콘택을 형성하는 경우에도 콘택의 저면에서 배리어 메탈층의 두께를 양호한 콘택 저항을 얻는 데 필요한 최소한의 두께로 형성하는 것이 가능하므로, 배리어 메탈층의 두께를 현저히 낮출 수 있다. 그 결과, 배리어 메탈층의 스텝 커버리지를 향상시킬 수 있다.As described above, in the present invention, PVD Ti / PVD TiN is formed by first forming a PVD Ti film in a contact hole, then capping the PVD Ti film with a PVD TiN film, and then forming a CVD TiN film to form a contact plug required for forming a semiconductor device. A barrier metal layer of a / CVD TiN stack structure is formed. Therefore, even when forming a fine contact having a large aspect ratio, it is possible to form the thickness of the barrier metal layer on the bottom of the contact to the minimum thickness necessary to obtain a good contact resistance, thereby significantly reducing the thickness of the barrier metal layer. . As a result, the step coverage of the barrier metal layer can be improved.
본 발명에 따른 방법은 CD(Critical Dimension)가 작을수록, 또는 아스팩트비가 클수록 유리하게 적용될 수 있는 것이다. 예를 들면, 0.25μm 이하의 작은 CD를 갖거나, 아스팩트비가 4 이상으로 큰 콘택을 형성하는 경우에, 배리어 메탈층을 본 발명에서와 같이 PVD Ti/PVD TiN/CVD TiN 스택 구조로 형성하면, 콘택의 저면에서 양호한 콘택 저항을 얻을 수 있다. 따라서, CD가 작은 경우 또는 아스팩트비가 큰 경우에도 충분한 공정 마진(margin)을 확보할 수 있다.The method according to the present invention can be advantageously applied to the smaller the critical dimension (CD), or the larger aspect ratio. For example, in the case of forming a contact with a small CD of 0.25 μm or less or having a large aspect ratio of 4 or more, when the barrier metal layer is formed of a PVD Ti / PVD TiN / CVD TiN stack structure as in the present invention, In the bottom of the contact, good contact resistance can be obtained. Therefore, even when the CD is small or the aspect ratio is large, sufficient process margin can be secured.
또한, PVD Ti막 표면이 PVD TiN막에 의하여 덮여 있으므로, 후속 공정에서 CVD 방법에 의하여 TiN막을 형성하기 위하여 TiCl4가스를 사용하여도 염소가 상기 PVD Ti막으로 침투하는 것이 방지될 수 있고, CVD TiN막 형성 전에 진공 상태가 해제되어도 대기중에서 거의 산화되지 않는 TiN막이 대기중에 노출되므로 자연산화막에 의한 콘택 저항 증가 현상을 방지할 수 있다.In addition, since the surface of the PVD Ti film is covered by the PVD TiN film, chlorine can be prevented from penetrating into the PVD Ti film even when using TiCl 4 gas to form the TiN film by the CVD method in a subsequent step, and the CVD Even if the vacuum is released before the TiN film is formed, the TiN film, which is hardly oxidized in the air, is exposed to the air, thereby increasing the contact resistance caused by the natural oxide film.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 이에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited thereto, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.
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