KR20010018400A - Error correciton method and apparatus thereof and error correction structure - Google Patents

Abstract

PURPOSE: Error correcting method, device, and structure are provided to multi-divide after column interleaving inner codes exceeding error correct operation range and to correct error in a Galois field by generating interleaved inner code parity. CONSTITUTION: Error correct codes are arranged in two-dimension to generate a second data unit for correcting error by collecting first data units as a basic unit. Outer code parity is generated for the arranged outer code. Inner codes exceeding a specific error correct operation range are column interleaved for multi divided into inner codes within the error correct operation range. Then, interleaved inner code parity is generated for the interleaved inner code to supply error corrected data. Herein, error correcting capacity is adjusted by varying number of inner code parity. Thus, error correction is performed in a Galois field GF(2¬8) regardless of length of data over 256 bytes.

Description

Error correction method and apparatus and error correction structure

TECHNICAL FIELD The present invention relates to the field of error correction, and more particularly, to an error correction method and apparatus for a high density recording medium, and an error correction structure for adjusting error correction capability by varying the number of parities for multi-segmented interleaved internal code.

As a technique for recording, reproducing, and erasing a large amount of information, a recording medium of a phase conversion method is known. The physical principle of such a recording medium is to change the state of the recording film into a crystalline phase and an amorphous phase with a recording pulse, read the crystalline phase as "1" (or "0"), and read the amorphous phase as "0" (or "1"). By reading), you read data. At this time, a random error due to jitter and a burst error due to a disk defect or the like occur. To correct this, a Reed-Solomon (RS) code is used. Conventional data structures include a product code and a long distance code (LDC), and three types of 0.5 KB, 1 KB, and 32 KB are used as ECC block sizes.

That is, a compact disc (CD), which is a representative example of an optical disc, has a sector size of 2 kilobytes ("KB"), and the structure of an error correction code ("ECC") block is 0.5 KB as shown in Fig. 1A. RS (28,24,5) RS (32, 28, 5) is used.

A write-write optical disk (Phase-write Dual) or MOD (Magnetic Optical Disc) uses LDC, and one sector has 0.5 KB (= 0.5 KB / sector), and is shown in FIG. As shown, the structure of the ECC block uses 5 way interleaved RSs 120, 104, and 17.

The ECC block structure of the Digital Versatile Disc-Random Access Memory (DVD-RAM) of 2 KB / sector and 32 KB / ECC block is RS (182, 172, 11), which is indicated by an appropriate symbol, as shown in FIG. RS (208, 192, 17) is used.

That is, 10 bytes of error correction parity is added to 172 bytes of data in the row direction as the inner code parity (PI), and 192 bytes of data in the column direction as the outer code parity (PO). An ECC block is formed by adding 16 bytes of error correction parity.

On the other hand, when a small scratch occurs on a High Density (HD) disc (" HD-DVD ") for higher density recording and playback than a DVD, the size of data loss due to this is inevitably larger than that of a general DVD. It is an error correction technique that can compensate for such data loss, and according to its application method, it greatly affects the amount of user data recorded and the reliability of user data during recording and playback. Therefore, if the error correction method applied to the DVD is applied to the HD-DVD as it is, the reliability of the reproduced data is much lowered.

That is, in the high density optical disc recording / reproducing apparatus, when the recording unit (sector) is set to 2 KB equal to DVD, in order to have the same collection error correction capability as that of DVD, the structure as shown in FIG. Or unless redundancy (parity, etc.) is increased.

Therefore, in order to have the same error density as the DVD in the high-density optical disc recording / reproducing apparatus, the ECC block must be large, but there is a problem that the error correction cannot be performed properly with the ECC block structure shown in FIG. The reason is that if the error correction operation range is exceeded (in Galois Field GF (2 ⁸ ) operation, the operation range must be within 256 bytes of ECC block length of RS code), that is, the data length is 256 bytes or more. This is because an error position cannot be obtained from the ECC block structure.

In order to solve the above problem, an object of the present invention is to interleave and multiply by interleaving an inner code over a predetermined error correction operation range, and to generate a multi-segmented interleaved inner code parity in gal and long GF ( ²⁸ ). An object of the present invention is to provide an error correction method capable of performing error correction.

It is another object of the present invention to perform an interpolation by internally interleaving an internal call over a predetermined error correction operation range, to generate a multi-division interleaved internal call parity, and to perform error correction in gal and long GF ( ²⁸ ). An error correction apparatus is provided.

It is still another object of the present invention to provide an error correction structure for a high density recording medium having variable internal call parity for multipart interleaved internal calls.

In order to achieve the above object, the error correction method according to the present invention arranges a predetermined error correction code in two dimensions in order to generate a second data unit for error correction by collecting a predetermined number of first data units which are basic recording units. Generating an outer code parity for the arranged outer code, splitting into an inner code within an error correction operation range while thermally interleaving for an inner code exceeding a predetermined error correction operation range, and interleaving an interleaved inner code. And generating error-encoded data by multiplying interleaved inner code parity.

In order to achieve the above another object, an error correction apparatus according to the present invention is a high density disk system comprising: a first data unit generator for generating a first data unit which is a basic recording unit and a predetermined number of first data units; Generate two data units, generate an outer code parity for the outer code, thermally interleave for an inner code that exceeds a predetermined error correction operation range, and divide into an inner code within an error correction operation range, And a second data unit generator for generating a multiplexed interleaved inner code parity for the inner code and providing error corrected encoded data.

In order to achieve the above another object, the error correction structure according to the present invention is a second data unit structure for error correction generated by gathering a predetermined number of first data units which are basic recording units. Multi-column interleaved for multi-column interleaved by multi-column interleaving for inner-codes that are arranged in two dimensions and added to outer-code parity for row-oriented outer-codes, and exceeding a predetermined error correction operation range. Inner parity is added.

1 (a) to (c) are diagrams showing conventional ECC blocks.

2 is an example of the data structure of each sector in an ECC block according to the present invention.

3 is an example of a data structure of an ECC block according to the present invention.

4 is a diagram illustrating a data configuration of an ECC block for explaining 5-way interleaved inner code parity according to an embodiment of the present invention.

5 is a block diagram of an optical recording and reproducing apparatus to which the present invention is applied.

6 is a lookup table for gal and long multiplication required to generate an ECC block of the present invention.

FIG. 7 is a detailed block diagram of an error correction encoder in the DSP encoder shown in FIG.

8 is a detailed block diagram of an error correction decoder in the DSP decoder shown in FIG.

9 is a diagram illustrating an error input / output relationship for random errors in order to help understanding of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the error correction method and apparatus and error correction structure according to the present invention.

A phase conversion method is adopted as a disc of a rewritable DVD-RAM, and a DVD-RAM having a recording capacity of 4.7 GB (Giga Bytes) is commercially available. 15 recently 20GB HD-RAM is under development. 3 than DVD As a method for achieving four times the recording capacity, an optical disk of a thin incident protective film, a blue laser, an objective lens having a high numerical aperture, and the like have been proposed.

In the present invention, the size of the ECC block is 64 KB in order to prevent a decrease in the correction capability due to the increase in the number of error bytes due to the increase in density, and in order to solve the problem (error location detection due to exceeding the error correction operation range), Introduces a parway interleaving method to the internal calls.

FIG. 2 is an example of a data structure of a sector (also referred to as a "first data unit") constituting an ECC block according to the present invention. In FIG. 6 bytes for Cyclic Redundancy Code (CCR) and 14 bytes of reserved data are added, and 4 bytes of Error Detection Code (EDC) are added to the 4116 data bytes obtained in this manner to add a 4120 byte first. Create a data unit. That is, the first data unit structure is 103 in the row direction. It is a 4KB sector with 5 bytes and 8 rows in the column direction.

3 is an example of a data structure of an ECC block (also referred to as a “second data unit”) according to the present invention. The ECC block includes 16 sectors (SECTOR 1). SECTOR 16) to collect 16 rows of outer arc parity (PO) and 5 An internal call parity (PI) of C (C is a variable internal call parity) column is generated. In order to improve the inner code parity correction capability and detect an error of the inner code beyond the error correction operation range, an inner code parity column interleaving method is applied.

4 is a diagram illustrating a data structure of an ECC block for describing 5-way interleaved internal code parity according to an embodiment of the present invention, wherein _{i in j, j, k} is a row index from 0 to 0; Up to 143, j is from 0 to 110 as a column index, and k is from 0 to 4 as an interleave index. Where C is 8 bytes.

That is, a 16-byte outer code parity is generated for an outer code of 128 bytes, and data having a length exceeding the error correction operation range is 103. Logical column interleaving for the 5 byte inner code to generate the first, second, third, fourth and fifth interleaved inner code parity (PI1, PI2, PI3, PI4, PI5), which is 5 It is called way interleaved inner code parity.

That is, modulo operation for each inner row of each row, where the remainder is zero, that is, the position where the interleaved index is "0" (B _0,0,0 , B _0,1,0 , ..., B _{0,102, 0} , B _1,0,0 , B _1,1,0 , ..., B _1,102,0 , ..., B _142,0,0 , B _142,1,0 , ..., B _142,102, A first inner code parity (PI1) is generated for the inner code of ₀ ), and a modulo operation is performed on the inner code of each row, where the remainder is 1, that is, the position where the interleaved index is "1" (B _{0,0 , 1} , B _0,1,1 , ..., B _0,102,1 , B _1,0,1 , B _1,1,1 , ..., B _1,102,1 , ..., B _{142,0 Create} a second inner code parity (PI2) for the inner arcs of _{, 1} , B _142,1,1 , ..., B _142,102,1 ), and _modulate the inner arcs of each row Position, that is, the position where the interleaved index is "2" (B _0,0,2 , B _0,1,2 , ..., B _0,102,2 , B _1,0,2 , B _1,1,2 , For the inner arc of ..., B _1,102,2 , ..., B _142,0,2 , B _142,1,2 , ..., B _142,102,2 ) Create, modulo for the inner arc of each row, and rest 3 Interleaving index "3" position _{(B 0,0,3, B 0,1,3, ...} , B 0,102,3, B 1,0,3, B 1,1,3, ... _Generate a fourth internal call parity (PI4) for the internal _{calls of} , B _1,102,3 , ..., B _142,0,3 , B _142,1,3 , ..., B _142,102,3 , Modulo operation on each row of each row, where the remainder is 4, that is, the position where the interleaved index is "4" (B _0,0,4 , B _0,1,4 , ..., B _0,102,4 , B _1,0,4 , B _1,1,4 , ..., B _1,102,4 , ..., B _142,0,4 , B _142,1,4 , ..., B _142,102,4 ) Generate a fifth inner code parity (PI5) for the inner code of to determine the error correction operation range (for example, the operation range of GF (2 ⁸ ) should be within 256 bytes in length). Even if the data length is over, error correction can be performed.

Fig. 5 is a block diagram for explaining an optical recording and reproducing apparatus (also called a DVD recorder) to which the present invention is applied, and performs recording and reproduction operations largely. When recording, the video and audio signals input by the analog-to-digital converter (ADC) 102, the digital signal processor (DSP) encoder 104, the recording compensator 106, and the optical power controller 108 are output to the optical disc 110. ). At the time of reproduction, the optical disc 110 by the optical detector 112, the reproduction amplifier 114, the reproduction equalizer 116, the synchronous decompressor 118, the DSP decoder 120 and the digital-to-analog converter (DAC, 122). The data read out from the original video signal and audio signal are reproduced and output.

During recording, the ADC 102 converts the video and audio signals, which are analog signals to be recorded, into digital signals, and the DSP encoder 104 provides binary information ("1", "0") provided through the ADC 102. Converts the input data bit stream consisting of ") into random data using an scrambler configured therein, and arranges data randomized by an error correction encoder configured therein in two dimensions for a predetermined error correction code, and two dimensions. The external code parity and the internal code parity are inserted into the error correction codes arranged in order to provide ECC block data, and the internally configured modulator converts the error correction coded data into a recording code string by a predetermined modulation scheme and converts the synchronization code. Insert it. Here, the synchronization code insertion is inserted every m bytes (= 5 * (103 + C) / n (n, m is an integer)). The write compensator 106 compensates for the write pulse in order to improve the recording density characteristic and to reduce the waveform interference during reproduction. The optical power controller 108 converts the compensated write pulse into an optical signal and writes it to the optical disk 110.

In reproduction, the photo detector 112 converts the optical signal reflected from the optical disk 110 into a current signal, the reproduction amplifier 114 amplifies the reproduction signal converted into the current signal, and the reproduction equalizer 116 The waveform shaping is performed after distortion and noise of the reproduction signal are removed, and the synchronization restorer 118 recovers the synchronization signal and the reproduction data from the reproduction signal provided from the reproduction equalizer 116. The detector configured inside the DSP decoder 120 determines whether there is a transition of the reproduction pulse of the light in a time zone determined by using the synchronization signal generated from the synchronization restorer 118, that is, a detection window. Is detected, and the demodulator configured to demodulate the detected code string into a data bit string, and the error correction decoder configured therein corrects an error of the demodulated data. The DAC 122 converts the demodulated data bit string into an analog video signal and an audio signal and outputs the analog video signal and the audio signal.

The ECC encoding performed by the error correction encoder inside the DSP encoder 104 shown in FIG. 5 will be described with reference to FIG. 6.

To generate an error correction code using GF (2 ⁸ ) primitive polynomials for 8-bit data codewords, the primitive polynomial of Equation 1 is used, and is shown in FIG. 6 for gal and long multiplication. Use a Look Up Table as shown.

Of GF (2 ⁸ ) The raw polynomial for generating is given by

here, Is the root of the above equation.

The ECC block layout of the appropriate sign used in the present invention is shown in the following equation (2).

Here, 103 + C is the total number of codewords in the row direction, 103 is the number of codewords in the inner code, C + 1 is the sum of the inner code parity plus 1, and C is the inner code parity. 144 is the total number of codewords in the column direction, 128 is the number of codewords in the outer code, and 17 is 1 plus the outer code parity.

According to the ECC block layout shown in Equation 2 above, the division polynomials shown in Equations 3 and 4 are calculated, and stored in a memory that can be composed of a lookup table, and then using the data stored in the memory. Generate outer code parity and inner code parity.

On the other hand, a detailed block diagram of the error correction encoder is shown in FIG. 7, for converting user data into sectors (4096 bytes) and for internal codes exceeding the range of error correction operations in an ECC block data structure consisting of 16 sectors. Column interleaving is performed to generate the inner code parity that does not exceed the error correction operation range of the GF (2 ⁸ ).

First, the first data unit generator 202 is given sector data and an ID as shown in FIG. 2, a CRC is generated from this ID, 14 bytes of spare data are appended, main data and an EDC. Generate a sector structure data of (4 bytes).

The error correction code generator 204 uses the raw polynomial shown in Equation 1 to generate the two-dimensional array of the second data unit structure from the 8-bit data codeword generated by the first data unit generator 202. Generate an error correction code. Here, the first LUT 206 is a lookup table for gal and field multiplication shown in FIG. 6. Addition for gal and long calculations for error correction codes is performed using an exclusive OR (XOR) operation and multiplication is calculated using the first LUT 206 to calculate the second product, the dot product.

The second LUT 210 stores values obtained by calculating the division polynomial for the outer code parity shown in Equation 4 according to the ECC block layout as shown in Equation 2, and the third LUT 214 stores the equation. According to the ECC block layout as shown in Equation 2, values obtained by calculating a division polynomial for the internal parity parity shown in Equation 3 are stored. Here, although the first to third LUTs are configured separately, they may be configured as one memory having the first to third LUTs.

The outer code parity generator 208 generates the outer code parity using the second LUT 210 and adds the generated outer code parity to the error correction code provided from the error correction code generator 204. The inner code parity generator 212 generates a 5-way interleaved inner code parity using the third LUT 214, and outputs the generated 5-way interleaved inner code parity from the outer code parity generator 208. Parity is added to the added error correction code to complete the error correction code generation. The row interleaver 216 performs row interleaving to add 16 rows of PO parity to the last row of 16 sectors. Row interleaved data is modulated sector by sector and recorded on the disc through pickup. Here, column interleaving for an inner call corresponds to logical interleaving, and row interleaving for an outer call corresponds to physical interleaving. The error correction code generator 204 to internal call parity generator 212 may be referred to as a second data unit generator.

Next, the ECC decoding process performed by the error correction decoder in the DSP decoder 120 shown in FIG. 5 will be described with reference to FIG. 8.

In the absence of erasure, the error can be corrected by solving the polynomial multiple-order simultaneous equation shown in Equation 5, which obtains an unknown value twice (that is, an error value and a position) twice the number of errors. This will be described.

Where X _i is the i th error position ( ), The error number is n _e , the parity number is n _p , the error location is l _i , and the error value is e _i . Up to 3 byte error correction is possible, and considering the data correction processing speed, only up to 2 byte error correction is possible. Modified Euclid Algorithm is used to find the location of the error. It can find the error location polynomial up to half the number of inner parity parity, calculate the error location using Chien search algorithm and calculate the inverse matrix. Correct the error at the error location. In outer code correction decoding, as much as the number of outer code parity can be corrected (referred to as erasure correction) by referring to an error position detected in inner code correction decoding.

FIG. 8 is a block diagram of an error correction decoder inside the DSP decoder 120 shown in FIG. 5, in which the row deinterleaver 302 is inserted into the last row of each sector from sector data of a code string read by a pickup from a disc. Call parity is collected and arranged at the end of the ECC block as before row interleaving.

The syndrome operator 304 generates the syndrome data of the row deinterleaved data provided from the deinterleaver 302 as much as the outer code parity number. When this syndrome operation is performed, the presence of an error is confirmed. That is, if the syndromes are all "0", it is determined that there is no error and the error correction is completed. If there is a syndrome, the error position polynomial is obtained at the Euclidean operator 306 using the modified Euclidean algorithm. Here, in addition to the Euclidean algorithm, the Berlekamp-Massey algorithm is also used. The error position detector 308 obtains the error position from the error position polynomial obtained by the Euclidean operator 306 through the Chien search algorithm, and calculates an inverse matrix for the error position using the equation 5 in the error corrector 310. Use the to correct the error.

If the result provided by the syndrome operator 304 instead of the Euclidean operator 306, the Chien searcher 308, or the error corrector 310 is in error (if the syndrome is not "0"), the direct solution of Petersen is used. Or an error corrector that corrects the error using a forney algorithm.

In the present invention, inner code correction and outer code correction, which are features of an appropriate code, may be repeatedly performed. Since the error call is known from the outer call correction and the second inner call correction, erasure correction is possible.

9 is a simulation result of the ECC block data structure for the purpose of understanding the present invention, and shows error input / output for a random error (+ 24% propagation), the horizontal axis is an input error, and the vertical axis is an output. Indicates an error. It can be seen that as the number of internal call parities increases, the ability to correct random errors is improved. In other words, when the input error (before ECC decoding) becomes large, the output error (after ECC decoding) becomes large, and the number of variable inner code parities (Npi, in the figure, is 4, 6, 8). It can be seen that the error correction capability can be adjusted according to the "

The present invention prevents the reduction of the correction ability due to the high density, and especially 15GB to use the blue laser Suitable for 20GB optical disk system.

The present invention divides and interleaves an internal code exceeding an error correction range to enable error position detection within a gal and long calculation range, and enhances error propagation and correction ability for small burst errors. In addition, since the number of internal call parity is variable, it is possible to adjust the overall error correction capability.

In the present invention, since the correction capability can be maintained even when the linear density is doubled, the size of the ECC block is doubled (64KB / 1 ECC block). When row deinterleaving is performed, error correction of the inner code and column deinterleaving are completed in the sector without separate column deinterleaving, thereby preventing the reduction of the correction capability of the outer code parity portion during physical interleaving / deinterleaving. The high rate of external call parity provides a strong advantage against burst errors.

The present invention can provide an ECC block data structure of a desired correction capability by allowing the number of multiplexed interleaved inner code parities for a multiplexed interleaved inner code not to exceed the range of error correction operations, thereby providing error correction. There is an effect of reducing delay time and improving burst and random error correction capability.

Claims (20)

(a) arranging a predetermined error correction code in two dimensions to collect a predetermined number of first data units which are basic recording units and generate a second data unit for error correction; And (b) generate an outer code parity for the arranged outer code, thermally interleave for an inner code exceeding a predetermined error correction operation range, and divide into an inner code within the error correction operation range; Generating multi-segmented interleaved inner code parity for the call to provide error corrected encoded data. 2. The error correction method of claim 1, wherein in the step (b), the error correction capability is adjusted by varying the number of the interleaved interleaved inner code parities. The method of claim 1 wherein the method is (c) performing row interleaving, arranging one row outer code parity in the last row of each first data unit. 4. The error correction of claim 3, wherein the column interleaving of the inner code performed when generating the inner code parity in step (b) is logical interleaving, and the row interleaving of the outer code performed in step (c) is physical interleaving. Way. The data unit of claim 1, wherein the first data unit adds 4096 bytes of user data to identification data, 6 bytes for cyclic redundancy check (CRC), and 14 bytes of reserved data, and 4 bytes for 4116 data bytes thus obtained. And a sector having 4120 bytes and 8 rows of 515 bytes by generating and adding an error detection code. 6. The method of claim 5, wherein said second data unit is an error correction code (ECC) block consisting of sixteen sectors. 4. The method of claim 1, wherein in step (b), 5-way interleaved RS (103 + C, 103, C + 1). Generate error correction encoded data of RS (144, 128, 17), where 103 + C is the total number of codewords in the row direction, 103 is the number of codewords in the inner code, and C is a variable inner code parity. Where C + 1 is 1 plus internal code parity, 144 is the total number of codewords in the column direction, 128 is the number of codewords in outer code, and 17 is 1 plus external code parity. Error correction method. The method of claim 7, wherein step (b), (b1) generating outer code parity for the outer call; And (b2) Modulo operation is performed on the inner arc of each row that exceeds the predetermined error correction operation range to generate the first inner arc parity for the inner arc of the position where the remainder is 0, and to the inner arc of the position where the remainder is 1. Generate a second inner arc parity for the second inner arc parity, generate a third inner arc parity for the inner position at rest 2, and generate a fourth inner arc parity for the inner position at rest 3, Generating a fifth inner arc parity for an inner arc at position four; And the first to fifth internal code parity are also interleaved, and error correction hatched data exceeding an error correction operation range can be error corrected. The method of claim 7, wherein the method is (c) modulating the error correction coded data, and inserting a synchronization code at a predetermined period; And the synchronization code is inserted every m bytes (m = 5 * (103 + C) / n, where n and m are integers). The method of claim 3, wherein the method (d) performing a row deinterleave where the last row of each first data unit in the second data unit is collected and arranged at the end of the outer code; And (e) error correcting a multi-segment column interleaved inner code within the error correction operation range using multi-segmented interleaved inner code parity, and error correcting an outer code using the outer code parity. Error correction method. In a high density disk system: A first data unit generator for generating a first data unit that is a basic recording unit; And A predetermined number of first data units are collected to generate a second data unit, generating an outer code parity for an outer call, and interleaving a column for an inner code that exceeds a predetermined error correction operation And a second data unit generator for dividing into an inner code within the plurality of inner codes and generating a multi-segmented interleaved inner code parity for the multi-segmented interleaved inner code to provide error-correction encoded data. 12. The error correcting apparatus of claim 11, wherein the second data unit generator adjusts an error correction capability by varying the number of the multipart interleaved inner code parities. 12. The apparatus of claim 11, wherein the second data unit generator is a 5-way interleaved RS (103 + C, 103, C + 1). Generate error correction encoded data of RS (144, 128, 17), where 103 + C is the total number of codewords in the row direction, 103 is the number of codewords in the inner code, and C is a variable inner code parity. Where C + 1 is 1 plus internal code parity, 144 is the total number of codewords in the column direction, 128 is the number of codewords in outer code, and 17 is 1 plus external code parity. Error correction device. The method of claim 11, And a row interleaver for arranging the outer code parity of one row in the last row of each first data unit provided from the second data generator. 15. The error correcting apparatus of claim 14, wherein the column interleaving of the inner code performed when generating the inner code parity in the second data unit generator is logical interleaving, and the row interleaving of the outer code performed in the row interleaver is physical interleaving. . The method of claim 14 wherein: A row deinterleaver for collecting the last row of each first data unit in the second data unit and arranging at the end of the outer code; And An error correction decoder for error correcting a multi-segment column interleaved inner code within the error correction operation range using multi-part interleaved inner code parity, and error correcting an outer code using the outer code parity. Correction device. In the second data unit structure for error correction generated by collecting a predetermined number of first data units which are basic recording units: A predetermined error correction code is arranged in two dimensions, an outer code parity is added to the outer code in the row direction, and a multi-part interleaved interleaved for the internal code exceeding a predetermined error correction arithmetic operation. An error correction structure, characterized in that multi-part interleaved inner-call parity is added to the call. 18. The apparatus of claim 17, wherein the first data unit adds 4096 bytes of user data to the identification information, 6 bytes for a cyclic redundancy check (CRC), and 14 bytes of reserved data, and 4 bytes for the 4116 data bytes thus obtained. And a sector having 4120 bytes and 8 rows of 515 bytes by generating and adding an error detection code. 19. The error correction structure of claim 18, wherein the second data unit is an error correction code (ECC) block consisting of 16 sectors. 18. The method of claim 17, wherein the 5-way interleaved RS (103 + C, 103, C + 1) Has the data structure of RS (144,128,17), where 103 + C is the total number of codewords in the row direction, 103 is the number of codewords in the inner code, C is the variable inner code parity, and C + 1 is 1 in internal parity parity, 144 is the total number of codewords in column direction, 128 is the number of codewords in outer code, and 17 is 1 in external parity parity. rescue.