KR20010005307A - Forming method for bit line of semiconductor device - Google Patents

Abstract

PURPOSE: A bit line formation method in semiconductor devices is provided to be capable of lowering the face resistance of bit lines and thus improving the operating speed and reliability of devices. CONSTITUTION: A bit line formation method includes forming the first interlayer insulating film(19) including a bit line contact(21) on a semiconductor substrate in which a MOSFET transistor is included. A polysilicon layer is selectively grown on the bit line contact, thus forming a bit line contact pad(23). The second interlayer insulating film is formed on the entire surface. Then, the second interlayer insulating film is etched using the bit line mask as an etch mask, thus forming a groove through which the bit lines contact pad is exposed. Next, a metal layer for bit line is formed on the entire structure. The metal layer for bit line is etched to fill the groove, thus forming a metal bit line(27b) connected to the bit line contact pad.

Description

Forming method for bit line of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to form a bit line contact, to form a bit line contact pad connected to the bit line contact, to secure a process margin, and to connect the bit line contact pad. The present invention relates to a bit line forming method of a semiconductor device for forming a metal bit line.

As semiconductor devices become more integrated, the gate electrode of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) is decreasing in width, but when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is decreased. There is a problem that the N times increased to decrease the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate by using the property of the polysilicon layer / oxide film interface exhibiting the most stable MOSFET characteristics.

In general, the most important function of the transistor constituting the semiconductor circuit is the current driving capability, and the channel width of the MOS FET is adjusted in consideration of this. The most widely used MOS FET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain region. Here, the sheet resistance of the gate electrode is about 30 to 70? /? The sheet resistance of the source / drain regions is about 70 to 150 Ω /? For N + and about 100 to 250 Ω /? For P +. In the case of a contact formed on a gate electrode or a source / drain region, the contact resistance is about 30 to 70? /? It is enough.

In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide layer may be formed only on the gate electrode and the source / drain regions by a salicide (self-aligned silicide) method or a selective metal layer deposition method. The current driving capability of the MOS FET was increased.

However, the bit line forming method of a semiconductor device according to the prior art has a bit line having a stacked structure of a polysilicon layer / metal silicide layer due to a high aspect ratio and decreasing the line width of the semiconductor device as the semiconductor device becomes highly integrated. Has a high sheet resistance (Rs), which causes a problem of lowering the operation characteristics of the device.

The present invention is to solve the above problems, forming a bit line contact, connected to the bit line contact, forming a bit line contact pad having a larger area than the bit line, and then using a damascene process The present invention provides a method for forming a bit line of a semiconductor device that forms a bit line and overcomes high sheet resistance and high aspect ratio.

1A to 1D are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with a first embodiment of the present invention.

1E is a top view of FIG. 1D.

2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with a second embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

11, 12: semiconductor substrate 13, 14: gate electrode

15, 16 mask insulating film 17, 18 insulating film spacer

19, 20: first interlayer insulating film 21, 22: bit line contact

23, 24: bit line contact pads 25, 26: second interlayer insulating film

27a, 28a: metal layer for bit lines 27b, 28b: metal bit line

A bit line forming method of a semiconductor device according to the present invention for achieving the above object,

Forming a first interlayer insulating film having a bit line contact on the semiconductor substrate including the MOS field effect transistor;

Forming a bit line contact pad by selectively growing a polysilicon layer on the bit line contact;

Forming a second interlayer insulating film over the entire surface;

Forming a groove exposing the bit line contact pad by etching the second interlayer insulating layer using a bit line mask as an etching mask;

Forming a bit line metal layer on the entire surface;

The first feature is that the bit line metal layer is etched to form a metal bit line embedded in the groove and connected to the bit line contact pad.

A bit line forming method of a semiconductor device according to the present invention for achieving the above object,

Forming a first interlayer insulating film having a bit line contact on the semiconductor substrate including the MOS field effect transistor;

Forming a polysilicon layer on the entire surface,

Forming a bit line contact pad connected to the bit line contact by etching the polysilicon layer by using a bit line contact pad mask that protects a portion intended as the bit line contact pad, using an etch mask;

Forming a second interlayer insulating film over the entire surface;

Forming a groove exposing the bit line contact pad by etching the second interlayer insulating layer using a bit line mask exposing a portion intended to be a bit line as an etching mask;

Forming a bit line metal layer on the entire surface;

The second feature is to form the metal bit line by etching the bit line metal layer to be embedded in the groove and connected to the bit line contact pad.

Hereinafter, a method of forming a bit line of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with a first embodiment of the present invention.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. An element isolation insulating film (not shown) is formed on the portion intended as the element isolation region.

Next, a gate insulating film (not shown) is formed on the semiconductor substrate 11, and a gate electrode 13 is formed on the semiconductor substrate 11. The mask insulating layer 15 is stacked on the gate electrode 13.

Next, low concentration impurities are implanted into both semiconductor substrates 11 of the gate electrode 13 to form an LDD region (not shown).

In addition, an insulating film spacer 17 is formed on sidewalls of the gate electrode 13 and the mask insulating film 15, and a high concentration of impurities are ion-implanted into both semiconductor substrates 11 of the insulating film spacer 17. A drain region (not shown) is formed.

Next, an interlayer insulating film 19 is formed over the entire surface, such as a BPSG film.

Next, the interlayer insulating layer 19 is etched using a bit line contact mask (not shown) that exposes a portion intended as a bit line contact to form an bit line contact hole (not shown).

Next, a bit line contact 21 filling the bit line contact hole by forming a conductive layer on the entire surface and etching the conductive layer by a full surface etching or a chemical mechanical polishing (CMP) process. To form. In this case, the conductive layer is formed of a polysilicon layer. (See Figure 1A)

Next, the bit line contact pad 23 is formed by epitaxially growing a polysilicon layer on the bit line contact 21. In this case, the bit line contact pad 23 is formed wider than the bit line contact 21.

Thereafter, the second interlayer insulating layer 25 is formed and planarized on the entire surface, and the second interlayer insulating layer 25 is formed of a material having a high etching selectivity with respect to the bit line contact pads 23. (See FIG. 1B)

Next, a groove (not shown) for etching the second interlayer insulating layer 25 to expose the bit line contact pad 23 by an etching process using a bit line mask exposing a portion intended to be a bit line as an etching mask. Form.

Then, the bit line metal layer 27a is formed on the entire surface. The bit line metal layer 27a is formed of a tungsten film or an aluminum film. (See FIG. 1C)

Thereafter, the bit line metal layer 27a is removed by an entire surface etching or CMP process to form a metal bit line 27b embedded in the groove and connected to the bit line contact pad 23. (See FIG. 1D)

FIG. 1E is a plan view of FIG. 1D formed by the above method, and shows that the bit line contact pad is formed wide to improve the process margin of the metal bit line formed in a subsequent process.

2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with a second embodiment of the present invention. After the process of FIG. 1A is performed, a polysilicon layer (not shown) is formed on the entire surface. And etching the polysilicon layer using a bit line contact pad mask that protects a portion intended as a bit line contact pad as an etch mask, thereby forming a bit line contact pad 24 connected to the bit line contact 22. A subsequent process as in the first embodiment is shown to form the metal bit line 28.

As described above, in the method of forming a bit line of a semiconductor device according to the present invention, a first interlayer insulating film having a bit line contact is formed on a semiconductor substrate on which a MOS field effect transistor is formed, and connected to the bit line contact. A bit line contact pad is formed, and a second interlayer insulating film is formed on the entire surface to be planarized to form a second interlayer insulating film pattern, which is a bit line exposing the bit line contact pad by a damascene process. After depositing the metal layer for etching, the metal layer for the bit line is etched to form a metal bit line to be connected to the bit line contact pad to reduce the sheet resistance of the bit line to improve the operation speed and reliability of the device and thereby There is an advantage to enable high integration.

Claims (8)

Forming a first interlayer insulating film having a bit line contact on the semiconductor substrate including the MOS field effect transistor; Forming a bit line contact pad by selectively growing a polysilicon layer on the bit line contact; Forming a second interlayer insulating film over the entire surface; Forming a groove exposing the bit line contact pad by etching the second interlayer insulating layer using a bit line mask as an etching mask; Forming a bit line metal layer on the entire surface; Etching the bit line metal layer to form a metal bit line embedded in the groove and connected to the bit line contact pad. The method of claim 1, And the second interlayer dielectric layer is formed of a material having a high etch selectivity with respect to the bit line contact pads. The method of claim 1, And the metal layer is formed of a tungsten film or an aluminum film. The method of claim 1, The metal bit line is a bit line forming method of a semiconductor device, characterized in that formed by etching the metal layer for the bit line by etching the entire surface or chemical mechanical polishing. Forming a first interlayer insulating film having a bit line contact on the semiconductor substrate including the MOS field effect transistor; Forming a polysilicon layer on the entire surface, Forming a bit line contact pad connected to the bit line contact by etching the polysilicon layer by using a bit line contact pad mask that protects a portion intended as the bit line contact pad, using an etch mask; Forming a second interlayer insulating film over the entire surface; Forming a groove exposing the bit line contact pad by etching the second interlayer insulating layer using a bit line mask exposing a portion intended to be a bit line as an etching mask; Forming a bit line metal layer on the entire surface; And forming a metal bit line embedded in the groove by etching the bit line metal layer to be connected to the bit line contact pad. The method of claim 5, And the second interlayer dielectric layer is formed of a material having a high etch selectivity with respect to the bit line contact pads. The method of claim 5, And the metal layer is formed of a tungsten film or an aluminum film. The method of claim 5, The metal bit line is a bit line forming method of a semiconductor device, characterized in that formed by etching the metal layer for the bit line by etching the entire surface or chemical mechanical polishing.