KR20000056067A - Method for forming semiconductor device antenna pattern for monitoring plasma damage - Google Patents

Abstract

PURPOSE: A method for forming an antenna pattern of a semiconductor device for monitoring plasma damage is to effectively perform the analysis of the characteristics while fabricating a TEG(Test element group) for analyzing a plasma damage. CONSTITUTION: A method for forming an antenna pattern of a semiconductor device for monitoring plasma damage comprises the steps of: forming an active region(20) of gate oxide in a semiconductor substrate; forming a source and a drain in the semiconductor substrate; forming a connection part(22) connected to the source and drain; and forming an antenna pattern having a charging path(26) and a gate(21) of polysilicon in a radial shape with respect to the connection part. A semiconductor device such as a transistor or a capacitor is placed at the center of antenna pattern or between the antenna patterns.

Description

Method for forming semiconductor device antenna pattern for monitoring plasma damage

The present invention relates to a plasma damage analysis method, and more particularly, to a method of forming an antenna pattern of a semiconductor device for a plasma damage monitor for laying out an antenna pattern so as to effectively analyze plasma damage.

At present, high integration of semiconductor devices has been advanced by the development of photo-lithography technology. The photolithography process is a process of transferring a geometric pattern on a mask to a thin layer of photoresist, that is, a resistor, covering a semiconductor wafer surface.

In addition, the high integration has been advanced by the development of an etching process, such as a plasma process, a reactive ion etching (RIE) process, and the like. In the etching process, charges, which cause defects in the gate insulating film, are accumulated in the floating gate, which seriously degrades the function of the gate insulating film. Therefore, the accumulation of the above charges causes a decrease in the reliability and characteristics of the semiconductor device.

Meanwhile, in order to manufacture a highly integrated semiconductor device and a high-speed semiconductor device, a multi-metal layer forming process is required, and in this case, a plasma process is applied, so that the use of the plasma process is gradually increasing. The multiple metal layer forming step is a step of forming a five or six metal layer.

As such, as the degree of integration of the semiconductor device increases, the line width of the device circuit becomes narrower. Accordingly, in order to etch the narrow line width, high density plasma etching, that is, high density plasma (HDP) etching is used.

As described above, high-density plasma is used to form a strong electric field between the gate and the substrate of the semiconductor device, thereby causing serious charge damage to the gate insulating film. As the damage caused in the high-density plasma process, damage occurs in the gate insulating film in the circuit in the device to shift the threshold voltage (Vth), the sub-threshold slope, the metal conductance (Gm), and the drain current. The degradation of (Idsat) and the shortening of the lifetime of the gate insulating film conductance (Gox) occur, thereby acting as a decisive factor in the malfunction of the semiconductor device.

This quantitative analysis method of plasma damage is by adding an Andena pattern to a semiconductor device, for example a transistor (capacitor), i. It is possible. In general, in the plasma process, the antenna pattern is referred to as an antenna because it serves as an antenna for collecting charges generated during the process.

FIG. 1 is a snake pattern antenna pattern used for measuring plasma damage of a conventional semiconductor device, and FIG. 2 is a comb antenna pattern.

In FIG. 1, reference numeral 10 in the drawing denotes an active region in which a gate insulating film, for example, gate oxide, is formed, and 11 denotes a poly layer constituting a gate and an antenna pattern. 12 is a connection for connecting wires from a source and a drain, and 13 is a longest, longest charging path in the antenna pattern. In Fig. 2, reference numeral 15 in the figure is the longest charge path in the antenna pattern. As shown, the charge path of the comb antenna is shorter than that of the snake antenna.

FIG. 3A is a graph illustrating a change in threshold voltage (Vth) of the snake-shaped antenna and the comb-shaped antenna shown in FIGS. 1 and 2, and FIG. 3B is a graph illustrating a change in saturation current.

In FIG. 3A, when comparing the threshold voltages of the two types of antennas with the threshold voltages of the reference MOS transistors, the antenna ratio is equal to 1000, and the layer is a poly antenna. As shown, the threshold voltage of the snake antenna is attenuated less than the threshold voltage of the comb antenna it can be seen that the effect of the snake antenna is small. In FIG. 3B, it can be seen that the saturation current of the snake-type antenna is attenuated smaller than that of the comb-shaped antenna, as shown in FIG. 3B.

On the other hand, when compared to the reference MOS transistor in a test pattern in which the antenna ratio is fixed to 1000 as described above, a small negative charge trap, that is, a positive shift occurs in the snake-type antenna. In the comb-type antenna, more positive charge traps, that is, negative shifts, are generated in the gate insulating layer. In addition, the saturation current is also smaller than the comb-shaped antenna comb antenna, indicating that the snake-shaped antenna is less efficient than the comb-shaped antenna.

As described above, snake-type and comb-type antennas are frequently used as antenna patterns for quantitative analysis. However, when the materials of these antennas are poly, the resistance value is considerably larger than that of metal. Due to the voltage drop in the antenna due to the distribution of, there was a problem that the function of charge accumulation during charge accumulation is reduced.

Accordingly, the present invention has been made in consideration of the above circumstances, and an antenna of a semiconductor device for a plasma damage monitor in which an antenna pattern is arranged to effectively perform characterization when fabricating a test element group (TEG) for analyzing plasma damage. The purpose is to provide a pattern forming method.

1 is a diagram showing a snake pattern antenna pattern used for measuring plasma damage of a conventional semiconductor device;

2 is a view showing a comb-shaped antenna pattern used for measuring plasma damage of a conventional semiconductor device;

3A is a graph illustrating a change in threshold voltage (Vth) of the snake-shaped antenna and the comb-shaped antenna shown in FIGS. 1 and 2;

3B is a graph illustrating a change in saturation current of the snake-shaped antenna and the comb-shaped antenna illustrated in FIGS. 1 and 2;

4 is a view showing a first embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention;

Figure 5a is a cross-sectional view of the line AA 'shown in Figure 4,

5B is a longitudinal cross-sectional view of the line B-B ′ shown in FIG. 4;

6 is a view showing a second embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention;

7 is a view showing a third embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention;

8 is a view showing a fourth embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention.

* Description of the symbols for the main parts of the drawings *

10,20: active region 11,21: poly layer

12,22: connection

13,15,26,33,34: longest charging path

27: field oxide region

28: spacer

29: insulating film for separating the lower layer and the metal wiring

30: wiring metal layer 31: source of transistor (drain)

32: drain (source) of transistor 35: shortest charge path

An antenna pattern forming method of a semiconductor device for a plasma damage monitor according to the present invention for achieving the above object is as follows. First, an active region of a gate insulating layer of a semiconductor device is formed in a first step, and a source and a drain of the semiconductor device are formed in the active area in a second step. In the third step, a connection part for connecting wires is formed from a source and a drain of the semiconductor device, and in the fourth step, a gate and an antenna pattern, which is a poly layer, is formed radially around the connection part.

According to the present invention configured as described above, the antenna pattern is designed to minimize the distance from the antenna end to the semiconductor element, that is, the transistor, and to place the semiconductor element in the center of the antenna pattern. In addition, by arranging and radiating a radial antenna pattern around the semiconductor device, a plurality of charges move to the gate end of the device in order to maximize attenuation efficiency of the oxide by finding a shorter path when the pattern is etched.

Hereinafter, an antenna pattern forming method of a semiconductor device for a plasma damage monitor according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a first embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention.

In FIG. 4, reference numeral 20 in the drawing denotes an active region in which a gate insulating film, for example, gate oxide, is formed, and 21 denotes a poly layer constituting a gate and an antenna pattern. 22 is a connection for connecting wires from a source and a drain, and 26 is a longest charging path in the antenna pattern.

FIG. 5A is a cross-sectional view of the line AA ′ shown in FIG. 4, and FIG. 5B is a longitudinal cross-sectional view of the line B-B ′ shown in FIG. 4. 5A and 5B, reference numeral 27 in the drawings denotes a field oxide region for isolation of a semiconductor device, for example, a transistor, a capacitor, and the like, and 28 denotes a spacer for forming a lightly doped drain (LDD). (spacer). 29 is an insulating film for separating the lower layer and the metal wiring, and 30 is a wiring metal layer.

6 is a view showing a second embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention. In Fig. 6, reference numeral 31 in the figure denotes a source (drain) of the transistor, and 32 indicates a drain (source) of the transistor. As shown, the + -shaped MOSFET device is disposed in the center of the semiconductor device, that is, the transistor, so that the charge path can be further reduced.

7 is a view showing a third embodiment of the antenna pattern of the semiconductor device for the plasma damage monitor according to the present invention. In Fig. 7, reference numeral 33 in the figure is the longest charge path in the antenna pattern. As shown, the antenna pattern is radially connected to minimize the charge path.

8 is a view showing a fourth embodiment of an antenna pattern of a semiconductor device for a plasma damage monitor according to the present invention. In Fig. 8, reference numeral 34 in the figure denotes the longest charge path in the antenna pattern, and 35 is the shortest charge path.

As described above, an antenna pattern is formed around the semiconductor element in order to effectively see plasma damage in the semiconductor element, for example, a transistor, a capacitor, or the like. In addition, the element may be formed between the antenna patterns, and as shown in the first to fourth embodiments, the antenna pattern may be formed radially.

The following is Table 1 comparing the charge path of the conventional antenna pattern, that is, the snake-shaped antenna pattern, the comb-shaped antenna pattern and the antenna pattern according to the embodiment of the present invention.

As shown in Table 1, it can be seen that the charge paths are significantly reduced in the first and second embodiments.

On the other hand, the present invention is not limited to the above-described specific embodiments and can be carried out by variously modified and modified within the scope and spirit of the present application.

According to the antenna pattern formation method of a semiconductor device for a plasma damage monitor according to the present invention, it is possible to design an antenna pattern of the type in which the distance from the antenna end to the semiconductor device, that is, the MOSFET device is minimized. Therefore, by placing the MOSFET element in the center of the antenna pattern and arranging the radial antenna pattern around each other, the MOSFET is moved to the gate end of the semiconductor element by finding a shorter path of charge when etching the pattern, thereby maximizing oxide attenuation efficiency. Let's do it.

Claims (4)

Forming an active region of the gate insulating film of the semiconductor device; Forming a source and a drain of the semiconductor device in the active region; Forming a connection portion connecting wires from a source and a drain of the semiconductor device; And forming a gate and an antenna pattern that are radially poly-layered around the connection part. The method of claim 1, And the semiconductor device is disposed in the center of the antenna pattern or between the antenna patterns. The method of claim 1, The antenna pattern forming method of a semiconductor device for a plasma damage monitor, characterized in that the antenna pattern is applied to a metal, a contact hole, vias, etc., in addition to the poly layer. The method of claim 1, The semiconductor device is an antenna pattern forming method of a semiconductor device for a plasma damage monitor, characterized in that consisting of a transistor or a capacitor.