KR20000052301A - Clamp circuit and method for controling clamping level thereof in video decoder - Google Patents

Abstract

PURPOSE: A clamp circuit of a video decoder and method for controlling clamp level thereof are provided to compensate the level shift of the reference level of the clamp level circuit. CONSTITUTION: A clamp circuit of a video decoder includes an alternative wave coupling capacitor(Cc), a clamp level controller(20), an amplifier(40), an analog/digital converter(50) and a control signal generator(60). The alternative wave coupling capacitor(Cc) couples an analog image signal. The clamp level controller(20) controls the horizontally synchronous signal generated at one end of the alternative wave coupling capacitor(Cc) with a reference clamp level. The amplifier(40) amplifies the output image signal from the clamp level controller. The analog/digital converter(50) converts the image signal amplified at the amplifier to a digital signal. The control signal generator(60) generates a control signal according to the compared result of the reference value to a digital image signal.

Description

Clamp circuit and method for controling clamping level about in video decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video decoder, and more particularly, to a video cassette recorder (hereinafter referred to as VCR), a laser disk player (hereinafter referred to as LDP) or a charge coupled device (hereinafter referred to as CCD), and the like. The present invention relates to a clamp circuit of a video decoder and a clamp level control method thereof for maintaining a constant DC level of a video signal when digitalizing an analog video signal output from the same video signal source.

In general, the video decoder plays a role of converting an analog video signal output from a video signal source such as a VCR, LDP or CCD into a digital signal so that the digital processor can process it. Accordingly, the decoder includes a programmable gain amplifier (hereinafter referred to as PGA) and an analog to digital converter (ADC). However, the DC level of the video signal is often different depending on the circuit driving method and characteristics of the devices generating the analog video signal. When the video signals having different DC levels are directly connected to the PGA or ADC in the decoder, In some cases, serious distortion or malfunction of the signal may occur.

In order to overcome this problem, AC coupling is performed using a charger without directly connecting the video signal to the input of the decoder so that it can operate normally even when the DC level of the input analog video signal is different. Then use clamp circuit to adjust DC level of coupled terminal to voltage that PGA or ADC can operate normally. The clamp circuit may raise or lower the voltage of the terminal to which the clamp circuit is connected according to a control signal by a predetermined value, or may maintain the DC voltage at a specific level.

On the other hand, the control signal for controlling the clamp circuit varies depending on the application of the video decoder. When decoding the output signal of the CCD, which is a typical imaging device, a separate clamp control signal is generated among the CCD control signals for driving the CCD. You can control the clamp circuit by using. The clamp control signal used in the CCD uses a signal path different from that of the video signal, and does not overlap at all with the effective pixel section even in timing, which is very convenient for controlling the clamp.

FIG. 1 is a diagram illustrating a clamp circuit according to the prior art of a video decoder for decoding an output signal of a CCD, including first and second comparators 150 and 156 and an automatic gain controller (hereinafter referred to as AGC) 152. And an ADC 154, a switch 160, and an integrator 158.

Referring to FIG. 1, when the clamp control signal C is enabled, the switch 160 is turned on to adjust the DC level of the input image signal Vin to the reference voltage Vref during this period. That is, in the section in which the clamp control signal CCS is enabled, a reference bottom voltage (or reference clamp level) having a black level is input to the input image signal Vin. However, this level may have some DC offset depending on the characteristics of the CCD and must be corrected. As such, in order to correct the DC offset of the reference bottom voltage, the second comparator 156 compares the level of the input image signal Vin with the reference voltage Vref during the period in which the clamp control signal CCS is enabled. Print the difference. The integrator 158 accumulates the difference between the input image signal Vin and the reference voltage Vref output from the second comparator 156, and outputs the accumulated value to the first comparator 150. That is, when the reference bottom level of the input image signal Vin is higher than the reference voltage Vref, the DC offset accumulated in the integrator 158 has a positive value, and the reference bottom level is lower than the reference voltage Vref. The offset accumulated in the integrator 158 has a negative value.

Since the first comparator 150 subtracts the DC offset of the input video signal Vin from the input video signal Vin, the first comparator 150 corrects the black level of the input video signal Vin to be the reference clamp level refb.

However, due to process dispersion, each part shown in FIG. 1 includes some offset. In this case, offsets of the first and second comparators 150 and 156 and the AGC 152 may be offset-corrected by the integrator 158. However, the offset of the reference clamp level refb or the offset of the ADC 154 is not corrected. However, if this offset is not taken into account, the video signal is eventually clamped to the wrong reference clamp level Vref, and therefore the output of the ADC 154 becomes inaccurate.

On the other hand, unlike a CCD, since a separate clamp control signal does not exist in an image device such as a VCR or an LDP, a signal for clamp control and its timing must be separated from the image signal itself. Analog video signal output from VCR or LDP uses several different standards for each country depending on the modulation method of the signal (NTSC, PAL, SECAM), but it can be divided into two types depending on the type. The first method is to separate the composite video signal, the luminance signal (Y), and the color signal (Chrominance: C), which are transmitted from one signal line by mixing the luminance and color components, and transmit them to different transmission lines. . In any case, the reference of the clamp is the horizontal sync H_sync section present in the luminance signal Y.

The original purpose of the H_sync section is a signal section to match the horizontal sync when a video signal is scanned by a display device such as a TV or a monitor. The signal level at this time is set as a level based on the video signal. Doing. The same is true of the TV signal when it finally appears in the CRT. The decoder can adjust the DC offset of the entire video signal by setting the analog signal level during the horizontal sync (H_sync) period to the reference bottom voltage (or reference clamp level) of the ADC.

However, since the horizontal sync signal H_sync is not separately separated from the actual video signal, but is mixed with the video signal and transmitted, the horizontal sync signal H_sync is at some point in view of a decoder that only receives the signal unilaterally. Starting out, you can't tell how much level you're going to keep. Moreover, depending on the apparatus, there is a problem in that it is difficult to synchronize the operation of the clamp circuit to the horizontal synchronous signal H_sync because the point of time or the level is not constant and changes from time to time within a certain range.

An object of the present invention is to provide a clamp circuit of a video decoder capable of detecting a horizontal sync signal from an input video signal and setting the detected horizontal sync signal to a reference clamp level of the video decoder.

Another object of the present invention is to provide a clamp level control method performed in the clamp circuit.

Another technical problem to be achieved by the present invention is to provide a clamp circuit of a video decoder for correcting a reference clamp level shift due to process dispersion when a clamp control signal is separately input.

1 shows a clamp circuit according to the prior art of a video decoder for decoding an output signal of a CCD.

2 is a circuit diagram illustrating a first embodiment of a clamp circuit of a video decoder according to the present invention.

3 is a circuit diagram of a preferred embodiment of the present invention of the control signal generator 60 shown in FIG.

4 is a flowchart illustrating a clamping level control method of a video decoder according to the present invention.

5A to 5C are waveform diagrams for explaining generation of the control signal CS when the clamp level of the AC-coupled video signal is set to an appropriate level.

6 (a) to 6 (c) are waveform diagrams for explaining generation of the control signal CS when the clamp level of the AC-coupled video signal is set very low.

7 is a circuit diagram illustrating a second embodiment of a clamp circuit of a video decoder according to the present invention.

In order to achieve the above object, in the video decoder for converting an analog video signal into a digital video signal, the clamp circuit of the video decoder according to the present invention for clamping the DC level of the analog video signal to the reference clamp level is an analog video signal input to one side. AC coupling capacitor for AC coupling, clamp level control means for controlling the horizontal synchronous level of the AC-coupled video signal generated to the other side of the AC coupling capacitor in response to the control signal to the reference clamp level, clamp level control means An amplifier for amplifying the video signal output from the digital signal, an analog / digital converter for converting the amplified video signal from the amplifier into a digital video signal, and comparing the magnitude of the first reference value with the digital video signal, Is greater than a first reference value, the dessay It is, or the digital video signal is less than the first reference value equal to preferably includes a control signal generating means for generating a control signal that is enabled for a predetermined time.

In order to achieve the above object, in the video decoder for converting an analog video signal into a digital video signal, the clamp level control method of the video decoder according to the present invention, which clamps the DC level of the analog video signal to a reference clamp level, sets the counter value to zero. (A) setting to (zero), alternatingly coupling an analog video signal, and generating a digital video signal while sinking at a reference potential by a predetermined amount of current from the AC-coupled video signal, the level of the digital video signal being the first If it is determined that the reference value is greater than the reference value, and if it is determined that it is large, in step (b) and step (b), if the level of the digital video signal is smaller than the first reference value, increasing the counter value by one (c), (D) controlling the DC level of the AC-coupled video signal to the reference clamp level, determining whether the counter value is the second reference value, and determining the counter value. If it is determined that the counter value is the second reference value in steps (e) and (e) proceeding to step (c) if it is not the second reference value, the reference potential is increased by a predetermined amount of current from the AC-coupled video signal for a predetermined period. It is preferable that step (f) proceeds to step (a) to continue the clamp level control by determining whether to terminate the clamp level control after the step (f) of sinking and after a predetermined period of time.

In order to achieve the above another object, in a video decoder for converting an analog video signal into a digital video signal, the clamp circuit of the video decoder according to the present invention for clamping the DC level of the analog video signal to a reference clamp level stores the analog video signal and accumulates it. A first comparator that receives the corrected DC offset, corrects the DC level of the analog video signal according to the accumulated DC offset, and outputs the offset-corrected video signal, accepts the offset-corrected video signal and the reference clamp level, and the clamp control signal Obtains the difference between the corrected video signal and the reference clamp level during the enabled period, accumulates the difference, and converts the accumulated value as a accumulated DC offset. Analog-to-Digital Converters and Clamps Generate Signals The average value is obtained by accumulating the system offset of the analog / digital converter or the reference clamp level during the period when the control signal is enabled, and the average value is subtracted from the digital video signal generated from the analog / digital converter during the period when the clamp control signal is disabled. It is preferable to include a system offset correction unit for outputting a digital video signal of which the system offset is corrected.

Now, a clamp circuit of a video decoder and a clamp level control method thereof according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating a first embodiment of a clamp circuit of a video decoder according to the present invention. The clamp circuit of the video decoder according to the invention comprises a coupling capacitor (Cc), a clamp level controller (20), a selector comprising a buffer (10), first and second switches (12 and 14) and a current source (I). 30, an amplifier 40, an analog-to-digital converter 50, and a control signal generator 60.

The clamp circuit of the video decoder according to the first embodiment of the present invention shown in FIG. 2 is an effective clamp circuit for an imaging apparatus in which a separate clamp control signal does not exist, such as a VCR or an LDP.

Referring to FIG. 2, an analog video signal input to the input terminal VIN is AC-coupled by an AC coupling capacitor Cc. The clamp level controller 20 controls the level of the horizontal synchronization H_sync of the AC coupled image signal generated to the other side of the AC coupling capacitor Cc in response to the control signal CS to the reference clamp level refb. do.

In more detail, the buffer 10 of the clamp level controller 20 buffers the reference clamp level refb. The first switch 12 is connected between the buffer 10 and the other side of the AC coupling capacitor Cc, and the AC coupling capacitor Cc in response to the control signal CS generated by the control signal generator 60. Switch to control the level of the horizontal synchronization H_sync of the AC signal coupled to the reference clamp level refb.

In addition, one side of the current source I is connected to the reference potential Vss so as to sink a predetermined current to the reference potential Vss. The second switch 12 is connected between the other side of the current source I and the other side of the AC coupling capacitor Cc and receives a predetermined current from the AC signal coupled in response to the inverted control signal CSB. Switch to sink to (Vss)

The amplifier 40 amplifies the clamp level controlled video signal by the clamp level controller 20, and the ADC 50 converts the signal output from the amplifier 40 into a digital video signal to generate the output terminal OUT and the control signal. Output to the unit 60.

The control signal generator 60 inputs the first reference value REF1 and the digital video signal and compares the magnitudes thereof. When the result of the comparison is greater than the first reference value REF1, the control signal generator 60 is disabled. If less than or equal to the first reference value REF1, the control signal CS is enabled for a predetermined time. Here, the first reference value REF1 is a value for detecting a horizontal sync H_sync section of an input analog video signal. That is, when the value obtained by digitally converting the input analog video signal is smaller than the first reference value REF1, the section is determined as horizontal synchronization REF1. As a result, the control signal generator 60 may detect the horizontal sync H_sync section of the analog video signal by using the first reference value REF1.

As a result of comparing the first reference value REF1 and the magnitude of the digital video signal, the control signal generator 60 generates a control signal CS that is disabled when the digital video signal is larger than the first reference value REF1. Accordingly, the clamp level control unit 20 is the first switch 12 is turned off, the second switch 14 is turned on to sink a predetermined current (for example, 8uA) to the reference potential (Vss) from the AC-coupled video signal. Thereby gradually decreasing the level of the AC-coupled video signal.

On the other hand, the control signal generator 60 generates a control signal CS that is enabled for a predetermined time when the digital video signal is less than or equal to the first reference value REF1. Accordingly, the clamp level controller 20 controls the first switch 12 to be turned on for a predetermined time and the second switch 14 to be turned off to control the level of the AC signal coupled to the reference clamp level refb. After a predetermined time, the control signal generator 60 disables the control signal CS again to turn off the first switch 12, and turns on the second switch 14 to turn on the clamp level controller 20. Controls to sink a predetermined current (e.g., 8uA) at the reference potential (Vss) from the AC-coupled video signal. On the other hand, since the level of the analog video signal is set to the reference clamp level refb when the first switch 12 is turned on, the ADC 60 continues to recognize that only the reference clamp level refb is input. lock) state. Therefore, the control signal generator 60 enables the control signal CS and then disables the control signal CS after a predetermined time, thereby preventing the clamp circuit from falling into the deadlock state.

As described above, when the digital video signal is less than or equal to the first reference value REF1, the second switch 14 is turned off only for a predetermined time and is otherwise turned on and is always turned on and then is selected from the AC-coupled video signal. The current (eg 8 uA) is sinked to the reference potential (Vss). In this case, if the amount of sinking current is too large, an offset of the video signal may change in the video signal section shown on the screen, and distortion may occur in the luminance signal of the entire screen. In addition, if the amount of current is set too small, there is a problem in that it takes a long time for the H_sync level to reach the reference clamp level refb when the offset of the entire video signal is very large. Therefore, the amount of current to be sinked must be appropriately selected. For example, when the actual NTSC signal is applied with an offset of 1V, if the amount of current to be sinked is 8uA, about two frames are required for clamping. This is an initial time required after the display device is powered on, and therefore cannot be easily felt by the human eye.

3 is a circuit diagram of a preferred embodiment of the present invention of the control signal generator 60 shown in FIG. The control signal generator 60 according to the present invention includes a first comparator 80, a clock counter 82, and a second comparator 84.

The first comparator 80 illustrated in FIG. 3 receives the n-bit digital video signal output from the ADC 50 and the first reference value REF1, compares the magnitude thereof, and compares the digital video signal with the first predetermined value. If less than REF1, it is disabled (hereinafter referred to as 'low' logic level), and if the digital video signal is greater than or equal to the first predetermined value REF1, it is enabled (hereinafter referred to as 'high' logic level). The comparison signal N1 is output.

The clock counter 82 receives the comparison signal N1 output from the first comparator 80 as an enable terminal EN. When the comparison signal N1 is at a 'low' logic level, the clock counter 82 is disabled and the comparison signal N1 is disabled. If the logic level is 'high', it is enabled to count the clock signal CK and output to the second comparator 84 as the counted result count value CNT.

The second comparator 84 generates a control signal CS that is disabled when the comparison signal N1 output from the first comparator 80 is 'low' logic level, and the comparison signal N1 is 'high' logic. At the level, the control signal CS is enabled or disabled according to the count value CNT output from the clock counter 82. That is, in response to the comparison signal N1 of the 'high' logic level, the second comparator 84 compares the counter value CNT output from the clock counter 82 with the second predetermined value, and compares the counter. If the value CNT is smaller than the second reference value REF2, the control signal CS having the 'low' logic level is obtained. If the counter value CNT is greater than or equal to the second reference value REF2, the control signal CS having the 'low' logic level is returned. Occurs.

That is, the second comparing unit 84 enables the control signal CS only until the counter value CNT output from the clock counter 82 becomes the second reference value REF2.

FIG. 4 is a flowchart illustrating a clamping level control method of a video decoder according to the present invention, which initializes a counter value CNT, determines whether an n-bit digital video signal is greater than a first reference value REF1, and determines According to the result, the levels of the AC-coupled video signal are sinked (steps 100 to 110) and the level of the AC-coupled video signal until the counter value CNT becomes a second predetermined value. And then sinking the levels of the AC-coupled video signal (steps 115 to 140).

2, 3 and 4, the clamp level control operation of the video decoder according to the present invention will be described in detail.

The circuit shown in FIG. 2 has three operating conditions according to the state of the video signal AC-coupled by the AC coupling capacitor Cc. In the first case, the clamp level of the AC-coupled video signal is set too high so that the entire video signal including the horizontal sync (H_sync) is higher than the reference clamp level (refb) of the decoder. In the second case, the clamp level is set too low. The entire video signal including the horizontal sync (H_sync) is set lower than the reference clamp level (refb) of the decoder, and the third case is set to an appropriate clamp level so that the reference clamp level (refb) and the crossing ( crssing) occurs.

First, the control signal generator 60 resets the clock counter 82, generates a control signal CS having a 'low' logic level, turns off the first switch 12, and then switches off the second switch ( 14), the DC level of the AC-coupled video signal is sinked by the current source I to the reference potential Vss by a predetermined amount of current (step 100). The ADC 50 converts the AC-coupled video signal into a digital signal, and then determines whether the value of the digital video signal is smaller than the first reference value REF1. If it is determined that the value is not small, the ADC 50 proceeds to step 100 (step 105). step). When the value of the digital video signal is less than the first reference value REF1 in step 105, the first comparator 80 illustrated in FIG. 2 generates a comparison signal N1 having a 'low' logic level. The clock counter 82 is disabled by the 'low' logic level comparison signal N1, and the second comparator 84 generates the control signal CS having the 'low' logic level. Accordingly, the first switch 12 is turned off and the second switch 14 is turned on to continuously sink the DC level of the AC-coupled video signal by the current source I to the reference potential Vss by a predetermined amount of current.

In this case, when the first reference value REF1 is set to, for example, 8, when the level of the digital signal is 8 or less, the first reference value REF1 is recognized as the horizontal synchronization H_sync section. In general, in the case of an NTSC video signal, the level of H_sync is about one quarter of the full scale range of the video signal. In other words, when converting an analog video signal into 10-bit digital data, the level of H_sync is up to 255. However, when 255 is set as a reference, the color burst signal that is ideally large when the color signal is input is horizontally synchronized. There may be a case of misrecognition as the (H_sync) section. As such, the circuit is complicated by adding a low pass filter to avoid clamp control in the color burst section. Therefore, it is advantageous to set the level for recognizing the horizontal sync H_sync to a value as small as possible.

That is, when it is determined in step 105 that the level of the digital video signal is greater than 8, it is determined that the clamping level of the AC-coupled video signal is set high or the color signal is input, as in the first case. The DC level of the signal is sinked to the reference potential Vss through the current source I, thereby lowering the DC level of the AC-coupled video signal. At this time, the sinking current is a current that continues to flow while the circuit shown in FIG. 2 operates as described above, and should be set to an appropriate amount.

In step 105, when the level of the digital video signal is determined to be equal to or less than the first reference value REF1, the first comparator 80 of FIG. 3 generates a signal having a high logic level, and the clock counter 82 Enabled by the high 'logical level comparison signal N1, the clock signal CK is counted to generate a first count value (step 110). Here, the digital image signal being smaller than the first reference value REF1 corresponds to the second or third case described above. That is, the DC level of the input analog video signal VIN is set too low so that the entire video signal including the horizontal sync H_sync is set lower than the reference clamp level refb of the decoder or the input analog video signal VIN. This is the case where the reference clamp level refb and the crossing occur between the horizontal synchronization H_sync due to the proper DC level.

After operation 110, the second comparator 84 generates a control signal CS having a high logic level based on the comparison signal N1 having a high logic level generated by the first comparator 80. The switch 12 is turned on and the second switch 14 is turned off to control the DC level of the AC-coupled video signal to the reference clamp level refb (step 115). After step 115, the second comparator 84 compares whether the counter value CNT output from the clock counter 82 is smaller than the second reference value REF2 (eg, 16 clocks) (step 120). If it is determined that the value CNT is smaller than the second reference value REF2, the control signal CS of the 'high' logic level is continuously generated. Steps 110 through 120 are repeated until the counter value CNT of the clock counter 82 reaches the second reference value REF2.

That is, when the value of the digital video signal is smaller than the first reference value REF1, the digital image signal is recognized as the horizontal sync H_sync section, and the first switch 12 is turned on to control the clamp level to the reference clamp level. Therefore, when the value of the digital video signal is less than or equal to the first reference value REF1, the DC level of the input video signal is analog-digital converted in accordance with the reference clamp level refb.

On the other hand, if the first switch 12 is continuously turned on, the clamp circuit enters a dead lock state as described above. In order to prevent such a phenomenon from occurring, the first switch 12 should be turned off after a predetermined time after the first switch 12 is turned on. That is, in operation 120, it is determined whether the counter value CNT generated by the clock counter 82 becomes the second reference value REF2. When the counter value CNT becomes the second reference value REF2, the second comparator ( 84 controls the control signal CS to be at a 'low' logic level to prevent falling into the deadlock state. For example, if the second reference value REF2 is set to 16, the second comparator 84 sets the control signal CS to the 'high' logic level only while the clock counter 82 is clocked 16 times. Enable.

When the counter value CNT reaches the second reference value REF2 in operation 120, the second comparator 84 generates a control signal CS having a 'low' logic level to turn off the first switch 12. , The second switch 14 is turned on. The video signal AC-coupled by the turned on second switch 14 is sinked to the reference potential Vss by a predetermined amount of current (step 125). After step 125, it is determined whether the counter value CNT is the third reference value (step 130), and if the counter value CNT has not yet reached the third reference value REF3, the clock counter 82 generates a clock signal ( CK) is continuously counted (step 135), and the second comparator 84 continuously generates the control signal CS of the 'low' logic level. Here, the third reference value REF3 is an operation cycle of the clamp circuit. In the normal NTSC video signal, when the clock signal is 27MHz, the H_sync section corresponds to 64 clocks. That is, after clamping the output video signal to the reference clamp level once, it is possible to clamp again for 64 clocks. no need. In addition, since the color signal is input thereafter, it may be set to, for example, 256 clocks in consideration of the need not to clamp during the section in which the color signal is input.

In operation 130, when the counter value CNT of the clock counter 82 reaches the third predetermined value, it is determined whether the clamp level control is to be terminated. In order to continue the clamping control, the operation proceeds to operation 100 (140). step).

5 (a) to 5 (c) show the control signal CS when the clamp level of the AC-coupled video signal is set to an appropriate level so that the reference clamp level refb and the crossing occur in the horizontal synchronization section H_sync. These are waveform diagrams for explaining the occurrence of. FIG. 5A illustrates an AC coupled video signal, FIG. 5B illustrates a comparison signal N1 output from the first comparator 80, and FIG. 5C illustrates a second comparator 84. Are waveform diagrams each showing a control signal CS generated in the.

Referring to FIGS. 5A to 5C, the AC-coupled video signal illustrated in FIG. 5A generates a reference clamp level refb and zero crossing in a horizontal synchronization H_sync period. That is, since the digital image signal output from the ADC 60 is equal to the first reference value refb in the section where zero crossing occurs, the comparison signal as shown in FIG. 5B is generated. The clock counter 82 starts counting the clock signal CK by the comparison signal N1 at the 'high' logic level shown in FIG. The second comparator 84 enables the control signal CS to the 'high' logic level by the comparison signal N1 of the 'high' logic level, and then adjusts the second reference value REF2 and the counter value CNT. In comparison, when the counter value CNT reaches the second reference value REF2 as shown in FIG. 5C, the control signal CS is disabled to a 'low' logic level.

6 (a) to 6 (c) are waveform diagrams for explaining generation of the control signal CS when the clamp level of the AC-coupled video signal is set very low. FIG. 6 (a) shows an AC coupled video signal with a very low DC level, FIG. 6 (b) shows a comparison signal N1 output from the first comparator 80, and FIG. The waveform diagrams show the control signals CS generated by the second comparator 84, respectively.

6 (a) to 6 (c), the digital image data output from the ADC 60 in a section in which the AC-coupled video signal shown in FIG. 6 (a) is lower than the reference clamp level refb is generated. It becomes smaller than one reference value REF1 to generate a comparison signal as shown in Fig. 6B. The clock counter 82 starts counting the clock signal CK by the comparison signal N1 enabled at the 'high' logic level shown in FIG. 6 (b). The second comparator 84 enables the control signal CS to the 'high' logic level by the comparison signal N1 of the 'high' logic level, and then adjusts the second reference value REF2 and the counter value CNT. In comparison, when the counter value CNT reaches the second reference value REF2 as shown in FIG. 6C, the control signal CS is disabled to a 'low' logic level.

Since the clamp circuit described above detects the horizontal sync (H_sync) section required for the clamp control by itself, it is possible to effectively control the clamp level of the video signal in the video device that does not have a separate clamp control signal.

7 is a circuit diagram illustrating a second embodiment of a clamp circuit of a video decoder according to the present invention. The clamp circuit according to the second embodiment of the present invention includes a first comparator 200, an AGC 202, an ADC 204, a DC offset detector 220, and a system offset corrector 210.

The circuit according to the second embodiment of the present invention shown in FIG. 7 is an effective clamp circuit when a clamp control signal for controlling the clamp is generated separately, such as an imaging apparatus using a CCD. That is, as described above, the reference clamp level having the black level is input to the input image signal Vin during the period in which the clamp control signal CCS is enabled in the imaging apparatus using the CCD. However, this level may have some DC offset depending on the characteristics of the CCD and must be corrected.

Referring to FIG. 7, the first comparator 200 receives an analog video signal VIN inputted to an input terminal VIN and a DC offset Io accumulated from a DC offset detector 220, and analogizes as much as the accumulated DC offset. The DCC level of the video signal is corrected, and the AGC 202 generates the offset-corrected video signal N2 by gain-adjusting the signal generated by the first comparator 200.

The DC offset detector 220 receives the offset-corrected image signal and the reference clamp level refb and accumulates the difference between the corrected image signal and the reference clamp level during the period in which the clamp control signal CCS is enabled. The value is generated as the accumulated direct current offset Io. In more detail, the DC offset detector 220 includes an integrator 208 and a second comparator 206.

The second comparator 206 receives the offset-corrected image signal N2 and the reference clamp level refb, obtains the difference between the offset-corrected image signal N2 and the reference clamp level refb, and outputs the difference. The integrator 208 accumulates the difference between the corrected image signal output from the second comparator 206 and the reference clamp level during the period in which the clamp control signal CCS is enabled, and accumulates the accumulated DC offset ( Occurs as Io). By the integrator 208, the input image signal Vin having a black level is corrected to be clamped to the reference clamp level refb during the period in which the control signal CCS is enabled.

The ADC 204 digitally converts the gain-adjusted signal in the AGC 202 to generate a digital video signal.

The system offset correction unit 210 accumulates the system offset So generated from the ADC 204 during the period in which the clamp control signal CCS is enabled to obtain the average value AVG of the system offset So, and controls the clamp. The average value AGC is subtracted from the digital image signal generated from the ADC 204 during the period where the signal CCS is disabled to output the digital image signal having the system offset So corrected. That is, due to process dispersion, each part of the clamp circuit shown in FIG. 7 includes a certain offset. In this case, the offsets of the first and second comparators 200 and 206 and the AGC 202 may be offset corrected by the integrator 208, and the offset of the ADC 204 and the offset of the reference clamp level refb are determined by the system. It may be corrected through the offset correction unit 210. Preferably, the system offset corrector 210 includes an accumulator 214, an average value generator 216, and a subtractor 212.

The accumulator 214 accumulates the system offset generated from the analog-to-digital converter during the period in which the clamp control signal CCS is enabled. The average value generator 216 obtains an average value AVG of the accumulated system offsets output from the accumulator 214 during the period in which the clamp control signal CCS is enabled, and during the period in which the clamp control signal CCS is disabled. The average value is latched. The subtractor 212 subtracts the average value AVG from the digital video signal generated from the ADC 204 and outputs a digital video signal having a system offset corrected.

That is, during the period in which the clamp control signal CCS is enabled, the AGC 202 outputs the black level of which the DC offset is corrected, and the digitally converted value should be 0 (in this case, the digital conversion value of the black level is Assume 0). However, if the reference clamp level refb includes an offset or if the ADC 204 contains an offset, the value obtained by digitally converting the black level generated in the AGC 202 does not become zero and has an offset value. Accordingly, the average value AVG is obtained by accumulating the offset value output from the ADC 204 during the period in which the clamp control signal CCS is enabled. Since the obtained average value AVG is subtracted from the digital video signal generated by the ADC 204, the system offset can be corrected.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the clamp control circuit and the method of the video decoder according to the present invention detect the clamp control section by itself and correct the DC offset of the input video signal even when the video signal without the separate clamp control signal is input. There is an effect that can be done, it is possible to correct the shift of the reference clamp level that is the reference of the clamp due to the process dispersion.

Claims (8)

A video decoder for converting an analog video signal into a digital video signal, wherein the clamp circuit of the video decoder clamps the DC level of the analog video signal to a reference clamp level. An AC coupling capacitor configured to AC-couple the analog video signal input to one side; Clamp level control means for controlling a horizontal synchronous level of an AC coupled video signal generated to the other side of the AC coupling capacitor in response to a control signal to a reference clamp level; An amplifier for amplifying the video signal output from the clamp level control means; An analog / digital converter for converting the video signal amplified by the amplifier into the digital video signal; And A first reference value and the digital video signal are inputted to compare their magnitudes, and as a result of the comparison, the digital video signal is disabled when the digital video signal is greater than the first reference value, and predetermined when the digital video signal is less than or equal to the first reference value. And control signal generating means for generating said control signal enabled for a time period. The method of claim 1, wherein the clamp level control means A buffer buffering the reference clamp level; A first switch connected between the buffer and the other side of the AC coupling capacitor, the first switch switching the horizontal synchronization level of the AC coupled image signal to the reference clamp level in response to the control signal; A current source having one side connected to the reference potential to sink a predetermined current to the reference potential; And A second switch connected between the other side of the current source and the other side of the AC coupling capacitor and switching to sink the predetermined current to the reference potential from the AC coupled image signal in response to an inverted control signal; Clamp circuit of a video decoder, characterized in that. The method of claim 1, wherein the control signal generating means A comparator that receives the digital video signal and a first reference value, compares the magnitude thereof, and outputs a comparison signal that is disabled when the digital video signal is smaller than the first reference value and is otherwise enabled; A clock counter that counts the clock signal in response to the comparison signal; And And a second comparator for generating the control signal which is enabled when the counter value is less than the second reference value and is otherwise disabled by comparing the counter value counted by the clock counter with the second reference value. Clamp circuit of the video decoder. A video decoder for converting an analog video signal into a digital video signal, wherein the clamp circuit of the video decoder clamps the DC level of the analog video signal to a reference clamp level. A first comparator that receives the analog video signal and the accumulated DC offset, corrects the DC level of the analog video signal according to the accumulated DC offset, and outputs an offset-corrected video signal; Accepts the offset-corrected video signal and the reference clamp level, obtains a difference between the corrected video signal and the reference clamp level during a period in which a clamp control signal is enabled, accumulates the difference value, and accumulates the accumulated value; A DC offset detector generated as a DC offset; An analog / digital converter for digitally converting the offset-corrected video signal to generate a digital video signal; And The average value is obtained by accumulating the system offset of the analog / digital converter or the reference clamp level during the period when the clamp control signal is enabled, and the digital generated from the analog / digital converter during the period when the clamp control signal is disabled. And a system offset correction unit for subtracting the average value from the image signal and outputting the digital image signal with the system offset corrected. The method of claim 4, wherein the direct current offset detector A second comparator that receives the offset-corrected video signal and the reference clamp level, obtains a difference between the corrected video signal and the reference clamp level, and outputs the difference; And And accumulating the difference between the corrected video signal output from the second comparator and the reference clamp level during the period in which the clamp control signal is enabled, and having an integrator generating the accumulated value as the accumulated direct current offset. Clamp circuit in a video decoder characterized by. The method of claim 4, wherein the system offset correction unit An accumulator that accumulates a system offset generated from the analog-to-digital converter during the period in which the clamp control signal is enabled; An average value generator for obtaining an average value of the accumulated system offset output from the accumulator during the period in which the clamp control signal is enabled, and latching the average value during the period in which the clamp control signal is disabled; And And a subtractor configured to subtract the average value from the digital video signal generated from the analog / digital converter to output a digital video signal with the system offset corrected. A video decoder for converting an analog video signal into a digital video signal, the clamp level control method of the video decoder to clamp the DC level of the analog video signal to a reference clamp level, (a) generating a digital video signal by setting a counter value to 0 (zero), AC-coupling the analog video signal, and sinking the AC video signal at a reference potential by a predetermined amount of current from the AC-coupled video signal; (b) determining whether the level of the digital video signal is greater than a first reference value, and if determined to be large, proceeding to step (a); (c) incrementing the counter value by one if the level of the digital video signal is less than the first reference value in step (b); (d) controlling the DC level of the AC-coupled video signal to a reference clamp level; (e) determining whether the counter value is the second reference value, and if the counter value is not the second reference value, proceeding to step (c); (f) if it is determined in step (e) that the counter value becomes the second reference value, sinking the reference potential by the predetermined amount of current from the AC-coupled video signal for a predetermined period; And and (g) proceeding to step (a) to determine whether to stop the clamp level control after the predetermined period has elapsed and to continue the clamp level control. The method of claim 4, wherein step (f) (f1) sinking at the reference potential by the predetermined current amount from the AC-coupled video signal if the counter value is the second predetermined value in step (d); (f2) determining whether the counter value is a third reference value; (f3) if it is determined in step (f2) that the counter value is not equal to the third reference value, increasing the counter value by one and proceeding to step (f1); And and (f4) if it is determined in step (f2) that the counter value reaches the third predetermined value, the method proceeds to step (g).