KR20000044160A - Timing recovery circuit of digital television receiving system - Google Patents

Abstract

PURPOSE: A timing recovery circuit of a digital television receiving system is provided to recover accurately timing by performing simultaneously a synchronous method and an asynchronous method. CONSTITUTION: A timing recovery circuit of a digital television receiving system comprises an analog/digital conversion portion(50), a timing recovery portion(60), a digital tracking portion(70), and a digital phase control portion(80). The analog/digital conversion portion converts a received complicate base band analog signal to a complicate base band data signal. The timing recovery portion receives the complicate base band data signal and recovers an asynchronous timing. The digital tracking portion receives the recovered data signal and detects a tracking error. The digital phase control portion provides a sampling signal synchronized with the timing of the received signal to the analog/digital conversion portion and a phase-controlled tracking error signal to the digital tracking portion.

Description

Timing Recovery Circuit of Digital Television Receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing recovery circuit of a digital television receiver, and more particularly, to a timing recovery circuit capable of accurate and high speed recovery by simultaneously performing asynchronous timing recovery and synchronous timing recovery by digital tracking control. It is about.

Digital television or High-Definition TeleVision (HDTV) broadcasting provides viewers with higher quality images by transmitting video and audio data digitally than traditional analog television broadcasting.

In the United States, VSB (Vestigial SideBand) digital transmission and reception was developed for D-TV broadcasting, and commercialization of terrestrial broadcasting and cable broadcasting began.

With the commercialization of such digital television broadcasting, the development of a receiving apparatus is being actively performed. In the digital television receiver, accurate timing recovery synchronized with the transmitting side is required for accurate data recovery from the received signal.

1 shows a synchronous timing recovery circuit of a conventional digital television receiver. In FIG. 1, the synchronous timing recovery circuit includes an analog-digital converter 11, a timing recovery unit 12, and an analog phase controller 13. 10 is a tuner part. In the conventional synchronous timing recovery circuit, the composite baseband analog signal received by the tuner unit 10 is sampled in response to the sampling signal by the analog-to-digital converter 110 to convert the composite baseband data signal into a composite baseband data signal and output the result. ), A segment synchronizing signal is extracted from the complex base band data signal and synchronized with the extracted segment synchronizing signal, and the analog phase controller 13 generates a sampling signal and provides it to the analog-to-digital converter 11.

Such a conventional synchronous timing recovery circuit enables accurate timing recovery by synchronizing with the timing of the received signal. However, there is a problem in that it takes a long time until the timing recovery is stabilized, so that the timing recovery speed is slow and timing jitter caused by instantaneous channel change and noise cannot be tracked.

2 shows an asynchronous timing recovery circuit of a conventional digital television receiver. The conventional asynchronous timing recovery circuit includes an analog to digital converter 11, a crystal oscillator 14, asynchronous timing recovery unit 15. The asynchronous timing recovery unit 15 includes a timing recovery unit 15a and a digital phase controller 15b. That is, in the conventional asynchronous timing recovery circuit, the analog-to-digital converter 11 samples asynchronously with the timing of the input signal in response to the sampling signal provided from the crystal oscillator 14, and the data is recovered by the timing recovery unit 15. Its timing is restored asynchronously by its digital phase control.

Such an asynchronous timing recovery circuit can restore the timing at a high speed, but since the synchronization signal contained in the received signal cannot be utilized, the accuracy of timing recovery is inferior.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing recovery circuit of a digital television receiver capable of recovering timing at high speed and accuracy by simultaneously synchronizing with digital tracking control and asynchronous with data interpolation in order to solve the problems of the prior art. To provide.

1 is a diagram showing a synchronous timing recovery circuit of a conventional digital television receiver.

2 shows an asynchronous timing recovery circuit of a conventional digital television receiver.

3 is a diagram showing the configuration of a digital television receiver.

4 shows a data frame structure of a digital television signal;

5 shows the structure of the field sync segment of FIG.

6 is a diagram showing the configuration of a timing recovery circuit according to the present invention;

7 is a view showing a detailed configuration of FIG.

<Description of the symbols for the main parts of the drawings>

40: tuner unit 50: analog to digital converter

60: asynchronous timing recovery unit 61; Interpolator

62: matching filter 63: timing error detector

64: loop filter 65: resampler

66: numerically controlled oscillator 70: digital tracking control unit

71: simulation field synchronous generator 72: advance correlator

73, 76: band filter 74, 77: square low detector

75: perceptual correlator 78: subtractor

80 digital phase controller 81 crystal oscillator

82: loop filter 83: numerically controlled oscillator

In order to achieve the above object of the present invention, the circuit of the present invention includes an analog-to-digital converter for converting a received complex baseband analog signal into a complex baseband data signal in response to a sampling signal, and An asynchronous timing recovery unit for restoring asynchronous timing, a digital tracking control unit for inputting the timing-restored data signal to detect a tracking error signal by timing tracking of a synchronization signal, and a signal received in response to the detected tracking error signal And a digital phase control unit for providing a sampling signal synchronized to the timing of the analog-to-digital conversion unit and providing a phase-controlled tracking error signal to the digital tracking control unit.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

3 shows the configuration of a digital television receiver. In Fig. 3, the digital television receiver includes a tuner 20, an intermediate frequency filter and a sync detector 22, an NTSC cancellation filter 24, an equalizer 26, a phase tracker 28, a trellis decoder. 30, a data deinterleaver 32, a Reed-Solomon decoder 4, a data derandomizer 36, and a synchronization and timing circuit 38. Here, the trellis decoder 30, the data deinterleaver 32, the Reed-Solomon decoder 34, and the data derandomizer 36 constitute a VSB demodulator.

The tuner 20 receives a 6 MHz signal (UHF or VHF) from the antenna. It is a high side injection double conversion type with a primary frequency of 920MHz. Image frequency above 1 GHz, fixed front end filter facilitates removal. The first intermediate frequency selection is high enough to prevent the input band pass filter from leaking from the local oscillator (978-1723 MHz) to the tuner front end and interfering with other UHF channels (460-806 MHz). It is low enough for the second harmonics of the UHF channels to fall above. The tuner has a band pass filter that limits the 50-180 MHz frequency range, removing all non-TV signals that fall within the tuner's image frequency range (920 MHz). The first mixer is driven by a synthesized low phase noise local oscillator of at least the first IF. The first local oscillator and the input band pass filter are controlled by a microprocessor. The tuner is capable of tuning all UHF, VHF broadcast bands, standard, IRC and HRC cable bands. At the front of the IF amplifier at 920 MHz, the delay AGC of the primary IF signal is performed. The second mixer is driven by a second local oscillator which is a 876 MHz voltage controlled SAW oscillator. The second local oscillator is controlled by the FPLL sync detector. The 44 MHz second IF signal is applied to the IF amplifier.

The second intermediate frequency signal of 44 MHz thus processed is output from the tuner and applied to the intermediate frequency filter and the synchronization detector 22.

Carrier recovery is performed with small pilot carriers by the FPLL circuit. The third local oscillator is a fixed reference oscillator. Frequency drafts or variations are compensated for in the second local oscillator. The control of the second local oscillator is made by the FPLL sync detector. The frequency loop provides a frequency pull-in region of ± 100 kHz, and the phase locking loop has a narrow band of less than 2 kHz. During frequency acquisition, the frequency loop uses in-phase (I) and quadrature phase (Q) pilot signals. An AFC low pass filter works on the bead signal generated by the frequency difference between the VCO and the input pilot. Most high frequency signals are removed from the AFC filter. Only the pilot bit signal remains. The beetle signal is limited to a square wave while passing through the limiter, and multiplied by the quadrature signal to generate an error signal. The polarity of the error signal is determined depending on whether the frequency of the VCO signal is above or below the frequency of the intermediate frequency signal. The error signal is filtered through the APC low pass filter, integrated and output as a DC signal. The DC signal controls the tuner's second local oscillator to reduce the frequency difference. When the frequency difference approaches zero, the APC loop phase locks the input intermediate frequency to the third local oscillation frequency.

Repetitive data segment synchronization is detected between random data synchronously detected by the narrowband filter. From the data segment synchronization, a 10.76 MHz symbol clock is generated with the coherence AGC signal. The 10.76 MHz I-channel composite baseband data signal (synchronization and data) from the synchronous detector is converted into a digital signal through an A / D converter. Data segment sync detectors, including four symbol sync correlators, detect two-level syncs that occur at specific repetition rates.

4 shows a data frame structure of a digital television signal. One data frame consists of two data fields consisting of 313 segments. Each data field contains one field sync segment. The field sync segment of the two data fields contains information for distinguishing odd and even fields.

5 shows a field sync segment structure of a digital television signal. The field sync segment consists of segment sync of 4 symbols, PN sequence of 511 symbols, PN sequence of 3 63 symbols, VSB mode of 24 symbols, and unused sequence of 104 symbols. Therefore, the field sync signal is composed of 511 symbols of PN sequence and three 63 symbols of PN sequence, and is composed of a total of 700 symbols. The difference between the odd field and the even field has a structure in which the center sequence of the three PN63 sequences is inverted from each other.

Fig. 6 shows a preferred embodiment of the timing recovery circuit of the digital television receiver according to the present invention. 5 includes an analog to digital converter 50, an asynchronous timing recovery unit 60, a digital tracking control unit 70, and a digital phase control unit 80. 40 is a tuner part.

7 shows a detailed configuration of FIG. 6. The asynchronous timing recovery unit 60 receives an interpolator for generating a synchronous sample value by interpolating the digital signal in response to a preset interpolation coefficient, that is, an interpolator 61 and the interpolated synchronous sample value. Matching filter 62 for generating a timing-corrected signal in which the ratio between the mean value of the square and the provided average value of the noise components is maximum, a timing error detector 63 for detecting an error component of the timing-corrected signal, and detected timing A loop filter 64 for filtering errors, a resampler 65 for resampling the filtered signal, and a numerically controlled oscillator 66 for controlling the interpolation coefficient of the interpolator in response to the resampled signal. do.

The digital tracking control unit 70 is a simulated field synchronizing signal generator 71 for generating a progressive and perceptual field synchronizing signal in response to the phase controlled tracking error signal, and the correlation between the progressive field synchronizing signal and the timing-restored data signal. A first square low for detecting an envelope by inputting an advance correlator 72 for detecting a signal, a first band filter 73 for band filtering an output of the advance correlator 72, and an output of the first band filter 73. A detector 74, a perceptual correlator 75 for detecting a correlation between the perceptual field synchronization signal and the timing-restored data signal, a second band filter 76 for band filtering the output of the perceptual correlator, and the second band filter A second square row detector 77 for detecting an envelope by inputting the output of 76; a subtractor 78 for generating a difference between the outputs of the first and second detectors 74, 77 as the tracking error signal; It includes.

The digital phase control unit 80 generates a crystal oscillator 81 for generating a fundamental frequency signal, a loop filter 82 for filtering the input timing error, and generates a sampling signal from the fundamental frequency signal in response to the filtered signal. And a numerically controlled oscillator 83 to be output.

Effects of the present invention configured as described above are as follows.

The analog-to-digital converter 50 inputs the complex baseband analog signal received and demodulated by the tuner unit 40 and samples the sampling signal provided from the digital phase controller 80 to output the complex baseband data signal. Therefore, if the sampling signal synchronized with the analog signal provided from the tuner unit 40 is not sampled, the correct symbol level is not sampled. In other words, if the sampling signal cannot follow the timing error of an analog signal including timing jitter due to a momentary channel change or noise, accurate symbol sampling is not performed.

The asynchronous timing recovery unit 60 inputs the data signal and interpolates in response to the interpolation coefficient to generate a timing-corrected signal in which the ratio of the squared mean value of the signal component to the provided mean value of the noise component is maximized. An error component of the timing corrected signal is detected, loop filtering the detected timing error, and resampled the filtered signal. Generate interpolation coefficients of the interpolator in response to the resampled signal.

The digital tracking controller 70 tracks the timing of the timing corrected data signal and generates a timing error Y (τ). Generate progressive and perceptual field synchronization signals in response to the phase controlled tracking error signal, detect correlation between the advance field synchronization signal and the timing corrected data signal, band filter the detected signal, and detect an envelope; . Correlation between the perceptual field synchronization signal and the timing corrected data signal is detected, band filtered, and an envelope is detected. The difference between the outputs of the first and second detectors is generated as a tracking error signal.

The digital phase control unit 80 inputs the tracking error signal to perform a loop filtering and generates a numerically controlled sampling signal using the fundamental frequency signal of the crystal oscillator in response to the filtered signal, and generates a phase controlled tracking error signal.

As described above, in the present invention, the timing is restored asynchronously by data interpolation, and the timing of the sampled signal of the analog-to-digital converter is synchronized with the timing of the input signal through the tracking control of the timing-restored signal. Can be achieved.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (4)

An analog-to-digital converter for converting the received composite baseband analog signal into a composite baseband data signal in response to the sampling signal; An asynchronous timing recovery unit for restoring asynchronous timing by inputting the complex baseband data signal; A digital tracking controller configured to input the timing-restored data signal to detect a tracking error signal by timing tracking of a synchronization signal; And a digital phase controller for providing a sampling signal synchronized with the timing of the received signal in response to the detected tracking error signal to the analog-to-digital converter, and for providing a phase controlled tracking error signal to the digital tracking controller. Asynchronous timing recovery circuit characterized by. The method of claim 1, wherein the asynchronous timing recovery unit An interpolator for generating a synchronous sample value by interpolating the data signal in response to a preset interpolation coefficient; A matched filter for receiving the interpolated synchronous sample value and generating a timing corrected data signal having a maximum ratio between a square mean value of a signal component and a provided mean value of a noise component; A timing error detector for detecting an error component of the timing corrected data signal; A loop filter for filtering the detected timing error; A resampler for resampling the filtered signal; And a numerically controlled oscillator for controlling the interpolation coefficient of the interpolator in response to the resampled signal. The method of claim 1, wherein the digital tracking control unit A simulated field sync signal generator for generating progressive and perceptual field sync signals in response to the phase controlled tracking error signal; An advance correlator for detecting a correlation between the advance field sync signal and the reconstructed data signal; A first band filter for band filtering the output of the advance correlator; A first square low detector configured to detect an envelope by inputting an output of the first band filter; A perceptual correlator for detecting a correlation between the perceptual field synchronization signal and the timing-restored data signal; A second band filter for band filtering the output of the perceptual correlator; A second square row detector inputting an output of the first band filter to detect an envelope; And And a subtractor for generating a difference between the outputs of the first and second detectors as the tracking error signal. The method of claim 1, wherein the digital phase control unit A crystal oscillator for generating a fundamental frequency signal; A loop filter for filtering the input timing error; And And a numerically controlled oscillator for generating and outputting a sampling signal from the fundamental frequency signal in response to the filtered signal.