KR20000044926A - Method for forming via hole of semiconductor device - Google Patents
Method for forming via hole of semiconductor device Download PDFInfo
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- KR20000044926A KR20000044926A KR1019980061429A KR19980061429A KR20000044926A KR 20000044926 A KR20000044926 A KR 20000044926A KR 1019980061429 A KR1019980061429 A KR 1019980061429A KR 19980061429 A KR19980061429 A KR 19980061429A KR 20000044926 A KR20000044926 A KR 20000044926A
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- via hole
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000001312 dry etching Methods 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 25
- 239000010410 layer Substances 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 8
- 229920000642 polymer Polymers 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 239000000654 additive Substances 0.000 abstract description 5
- 230000000996 additive effect Effects 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract 2
- 238000005336 cracking Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 15
- 238000001039 wet etching Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 비아홀 형성 방법에 관한 것으로, 특히 반도체 소자의 금속 배선 콘택 공정시 와인 글라스(wine glass) 모양의 비아홀 형성 공정을 개선하여 감광막 패턴의 들뜸 현상을 방지하므로써, 후속 건식 식각시 노출된 부위의 어택(attack) 방지 및 공정의 안정화로 반도체 소자의 전기적 특성 및 수율을 향상시킬 수 있는 반도체 소자의 비아홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a via hole of a semiconductor device, and in particular, to improve the formation of a wine glass via hole during a metal wiring contact process of a semiconductor device, thereby preventing the photosensitive film pattern from being lifted, thereby exposing the substrate to subsequent dry etching. The present invention relates to a method of forming a via hole of a semiconductor device capable of improving the electrical properties and yield of the semiconductor device by preventing attack of the damaged portions and stabilizing the process.
일반적으로, 반도체 소자의 제조 공정중 소자와 소자간 또는 배선과 배선간을 전기적으로 연결시키기 위해 금속 배선 콘택 공정을 실시한다. 반도체 소자가 고집적화 되어감에 비아홀에서의 금속 스텝 커버리지(metal step coverage)를 향상시키기 위해, 비아홀을 와인 글라스 모양으로 형성한다.In general, a metal wiring contact process is performed in order to electrically connect an element and an element or a wiring and an interconnection in a semiconductor device manufacturing process. In order to improve metal step coverage in the via holes as the semiconductor devices are highly integrated, the via holes are formed in a wine glass shape.
도 1a 내지 도 1c는 종래 반도체 소자의 비아홀 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a method of forming via holes in a conventional semiconductor device.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11)상에 하부 금속 배선(12)이 형성되고, 하부 금속 배선(12)상에 층간 절연막(14)이 형성된다. 층간 절연막(14)상에 감광막 패턴(15)이 형성된다. 하부 금속 배선(12)의 상부에는 반사방지막(13)이 형성된다.Referring to FIG. 1A, a lower metal interconnection 12 is formed on a substrate 11 having a structure in which various elements for forming a semiconductor device are formed, and an interlayer insulating layer 14 is formed on the lower metal interconnection 12. . The photosensitive film pattern 15 is formed on the interlayer insulating film 14. An antireflection film 13 is formed on the lower metal wire 12.
도 1b를 참조하면, 감광막 패턴(15)을 식각 마스크로 한 습식 식각 공정으로 층간 절연막(14)을 일정 깊이 식각 하여 접시 모양의 홈(16)을 형성한다. 습식 식각 공정은 묽은 불산 용액(buffered oxide etchant; BOE)을 이용한다.Referring to FIG. 1B, a dish-shaped groove 16 is formed by etching the interlayer insulating layer 14 to a predetermined depth by a wet etching process using the photoresist pattern 15 as an etching mask. The wet etch process uses a dilute hydrofluoric acid solution (buffered oxide etchant (BOE).
도 1c를 참조하면, 감광막 패턴(15)을 다시 식각 마스크로 한 건식 식각 공정으로 하부 금속 배선(12)이 노출될 때까지 층간 절연막(14)을 식각 하여 와인 글라스 모양의 비아홀(17)을 형성한다.Referring to FIG. 1C, a wine glass via hole 17 is formed by etching the interlayer insulating layer 14 until the lower metal wiring 12 is exposed by a dry etching process using the photoresist pattern 15 as an etching mask. do.
상기한 종래 방법은 반도체 소자의 고집적화로 인해 비아홀(17)과 이에 이웃하여 형성되는 다른 비아홀 사이의 간격이 좁아질 경우, 습식 식각시 측면을 많이 치고 들어가 감광막 패턴(15)의 들뜸(lifting) 현상이 발생한다. 또한 감광막 패턴(15)을 DUV 감광물질로 형성할 경우 베이킹(baking) 공정에서 깨어지는 현상이 발생된다. 이와 같이 들뜸 현상 및 깨어짐 현상으로 인하여 0.15㎛ 이하의 반도체 소자인 경우에는 큰 문제점으로 대두되며, 또한 이러한 현상은 반도체 소자의 전기적 특성 및 수율을 저하시키는 요인으로 작용하게 된다.According to the conventional method, when the gap between the via hole 17 and another via hole formed adjacent thereto is narrowed due to the high integration of the semiconductor device, the phenomenon of lifting the photoresist pattern 15 by hitting the side during wet etching is increased. This happens. In addition, when the photosensitive film pattern 15 is formed of a DUV photosensitive material, a phenomenon of breaking occurs in a baking process. As a result, the semiconductor device having a size of 0.15 μm or less due to the lifting phenomenon and the breaking phenomenon becomes a big problem, and this phenomenon also acts as a factor that lowers the electrical characteristics and yield of the semiconductor device.
따라서, 본 발명은 반도체 소자의 금속 배선 콘택 공정시 와인 글라스(wine glass) 모양의 비아홀 형성 공정을 개선하여 감광막 패턴의 들뜸 현상을 방지하므로써, 후속 건식 식각시 노출된 부위의 어택(attack) 방지 및 공정의 안정화로 반도체 소자의 전기적 특성 및 수율을 향상시킬 수 있는 반도체 소자의 비아홀 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention improves the process of forming a wine glass via hole during the metal wiring contact process of the semiconductor device, thereby preventing the photosensitive film pattern from being lifted, thereby preventing attack of the exposed part during subsequent dry etching. It is an object of the present invention to provide a method for forming a via hole of a semiconductor device capable of improving electrical characteristics and yield of a semiconductor device by stabilizing a process.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 비아홀 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 하부 금속 배선을 형성하는 단계; 상기 하부 금속 배선 상에 층간 절연막이 형성하고, 상기 층간 절연막 상에 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 식각 마스크로 한 1차 건식 식각 공정으로 하부 금속 배선이 노출될 때까지 층간 절연막을 식각 하여 수직 비아홀을 형성하는 단계; 및 상기 감광막 패턴을 제거한 후, 2차 건식 식각 공정으로 상기 수직 비아홀이 형성된 층간 절연막을 식각 하여 경사진 비아홀을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method of forming a via hole of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a lower metal wiring on a substrate having a structure in which a number of elements for forming a semiconductor device; Forming an interlayer insulating film on the lower metal interconnection and forming a photoresist pattern on the interlayer insulating film; Forming a vertical via hole by etching the interlayer insulating layer through a first dry etching process using the photoresist pattern as an etching mask until the lower metal wiring is exposed; And removing the photoresist pattern, and etching the interlayer insulating layer on which the vertical via holes are formed by a second dry etching process to form inclined via holes.
도 1a 내지 도 1c는 종래 반도체 소자의 비아홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a via hole in a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 비아홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.2A to 2C are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 기판 12, 22: 하부 금속 배선11, 21: substrate 12, 22: lower metal wiring
13, 23: 반사방지막 14, 24: 층간 절연막13, 23: antireflection film 14, 24: interlayer insulating film
15, 25: 감광막 패턴 16: 홈15, 25: photoresist pattern 16: groove
26: 수직 비아홀 17, 27: 비아홀26: vertical via hole 17, 27: via hole
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 비아홀 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2C are cross-sectional views of devices for describing a method of forming via holes in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(21)상에 하부 금속 배선(22)이 형성되고, 하부 금속 배선(22)상에 층간 절연막(24)이 형성된다. 층간 절연막(24)상에 감광막 패턴(25)이 형성된다. 하부 금속 배선(22)의 상부에는 반사방지막(23)이 형성된다.Referring to FIG. 2A, a lower metal interconnection 22 is formed on a substrate 21 having various elements for forming a semiconductor device, and an interlayer insulating layer 24 is formed on the lower metal interconnection 22. . The photosensitive film pattern 25 is formed on the interlayer insulating film 24. An antireflection film 23 is formed on the lower metal wire 22.
상기에서, 층간 절연막(24)은 보로포스포 실리케이트 글라스(BPSG), 스핀 온 글라스(SOG) 또는 포스포러스 실리케이트 글라스(PSG)가 사용된다.In the above, the interlayer insulating film 24 is made of borophospho silicate glass (BPSG), spin on glass (SOG) or phosphorus silicate glass (PSG).
도 2b를 참조하면, 감광막 패턴(25)을 식각 마스크로 한 1차 건식 식각 공정으로 하부 금속 배선(22)이 노출될 때까지 층간 절연막(24) 및 반사방지막(23)을 식각 하여 수직 비아홀(26)을 형성한다.Referring to FIG. 2B, the interlayer insulating film 24 and the anti-reflection film 23 are etched by the first dry etching process using the photoresist pattern 25 as an etching mask until the lower metal wiring 22 is exposed. 26).
상기에서, 1차 건식 식각 공정은 CF4, C2F6, C3F8, C4F8, CHF3등과 같은 식각 기체에 CO, O2, Ar, He 등의 기체를 첨가하여 상기한 바와 같이 하부 금속 배선(22)이 노출될 때까지 실시하거나, 아니면 층간 절연막(24)만 식각 하여 반사방지막(23)을 식각하지 않을 수도 있다. 1차 건식 식각 공정에서 첨가 기체인 CO, O2등은 비아 콘택의 경사와 하부 금속 배선(22)상의 반사방지막(23)의 식각을 조절하는 역할을 하며, 첨가 기체인 Ar, He 등과 같은 불활성 기체는 비아 콘택 식각 공정에서 발생할 수 있는 금속성 폴리머(metallic polymer)의 양을 감소시키는 역할을 한다.In the above, the first dry etching process is described by adding a gas such as CO, O 2 , Ar, He, etc. to the etching gas such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , CHF 3 , etc. As described above, the anti-reflection film 23 may not be etched until the lower metal wires 22 are exposed, or only the interlayer insulating film 24 is etched. In the first dry etching process, CO and O 2 , which are additive gases, control the inclination of the via contact and the etching of the anti-reflection film 23 on the lower metal wiring 22, and inert such as Ar and He, which are additive gases. The gas serves to reduce the amount of metallic polymer that can occur in the via contact etching process.
도 2c를 참조하면, 감광막 패턴(25)을 제거한 후, 식각 마스크 없이 2차 건식 식각 공정으로 수직 비아홀(26)이 형성된 층간 절연막(24)을 일정 시간 식각 하여 경사진 비아홀(27)을 형성한다. 경사진 비아홀(27)을 형성한 후에 잔존하는 금속성 폴리머를 CF4/O2/Ar 플라즈마를 이용하여 제거한다.Referring to FIG. 2C, after removing the photoresist pattern 25, an inclined via hole 27 is formed by etching the interlayer insulating layer 24 having the vertical via hole 26 formed therein by a secondary dry etching process without an etching mask. . After forming the inclined via hole 27, the remaining metallic polymer is removed using a CF 4 / O 2 / Ar plasma.
상기에서, 감광막 패턴(25)은 O2플라즈마에 Ar, He 기체를 첨가하여 제거한다. 2차 건식 식각 공정은 1차 건식 식각 공정과 마찬가지로 CF4, C2F6, C3F8, C4F8, CHF3등과 같은 식각 기체에 CO, O2, Ar, He 등의 기체를 첨가하여 실시한다. 2차 건식 식각 공정에서 첨가 기체인 CO, O2등은 비아 콘택의 경사와 하부 금속 배선(22)상의 반사방지막(23)의 식각을 조절하는 역할을 하며, 첨가 기체인 Ar, He 등과 같은 불활성 기체는 비아 콘택 식각 공정에서 발생할 수 있는 금속성 폴리머(metallic polymer)의 양을 감소시키는 역할을 한다. 1차 건식 식각 공정시 반사방지막(23)을 식각하지 않았을 경우에는 콘택 저항의 증가를 방지하기 위해 2차 건식 식각 공정시에 반드시 하부 금속 배선(22)이 노출되도록 반사방지막(23)을 제거하여야 한다.In the above, the photoresist layer pattern 25 is removed by adding Ar and He gases to the O 2 plasma. Like the first dry etching process, the second dry etching process uses a gas such as CO, O 2 , Ar, or He in an etching gas such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , or CHF 3 . It is carried out by addition. In the second dry etching process, CO and O 2 , which are additive gases, control the inclination of the via contact and the etching of the anti-reflection film 23 on the lower metal wiring 22, and inert such as Ar and He, which are additive gases. The gas serves to reduce the amount of metallic polymer that can occur in the via contact etching process. If the anti-reflection film 23 is not etched during the first dry etching process, the anti-reflection film 23 must be removed so that the lower metal wiring 22 is exposed during the second dry etching process to prevent an increase in contact resistance. do.
한편, 1차 건식 식각 공정, 감광막 패턴(25) 제거 공정 및 2차 건식 식각 공정은 생산성 향상과 공정 소요 시간 측면에서 유리하도록 식각 장비에서 인-시튜(in-situ)로 이루어진다.Meanwhile, the first dry etching process, the photoresist pattern 25 removing process, and the second dry etching process are formed in-situ in the etching equipment to improve productivity and process time.
상기한 본 발명은 기존의 습식 식각 및 건식 식각으로 와인 글라스 모양의 비아홀을 형성하는 것을 건식 식각만을 적용하여 와인 글라스 모양과 비슷한 경사진 비아홀을 형성하는 기술로서, 먼저 감광막 패턴을 식각 마스크로 하여 CF4, C2F6, C3F8, C4F8, CHF3등과 같은 식각 기체에 CO, O2, Ar, He 등의 기체를 첨가하여 1차 건식 식각 공정을 실시하고, 이로 인하여 수직 비아홀이 형성되고, O2플라즈마에 Ar, He 기체를 첨가하여 감광막 패턴을 제거한 후, 다시 CF4, C2F6, C3F8, C4F8, CHF3등과 같은 식각 기체에 CO, O2, Ar, He 등의 기체를 첨가하여 2차 건식 식각 공정을 실시하고, 이로 인하여 수직 비아홀이 경사진 비아홀로 되게 한다.The present invention described above is a technique of forming an inclined via hole similar to a wine glass by applying only dry etching to forming a wine glass via hole by conventional wet etching and dry etching. First, the photoresist pattern is used as an etching mask. 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , CHF 3 and the like to add a gas such as CO, O 2 , Ar, He, etc. to perform the first dry etching process, thereby vertical Via holes are formed, the Ar and He gases are added to the O 2 plasma to remove the photoresist pattern, and then CO, CO, etc. are added to the etching gas such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 , and CHF 3 . A second dry etching process is performed by adding a gas such as O 2 , Ar, or He, thereby causing the vertical via hole to be an inclined via hole.
상술한 바와 같이, 본 발명은 감광막 패턴을 식각 마스크로 한 1차 건식 식각 공정으로 수직 비아홀을 형성하고, 감광막 패턴을 제거한 후 2차 건식 식각 공정으로 수직 비아홀을 경사지게 하므로써, 기존의 감광막 패턴의 깨어짐 현상 및 들뜸 현상을 방지할 수 있을 뿐만 아니라, 기존의 건식 식각 공정시 노출된 부위의 어택(attack) 방지 및 공정의 안정화로 반도체 소자의 전기적 특성 및 수율을 향상시킬 수 있으며, 기존의 습식 식각과 건식 식각을 함께 하는 경우에 비해 공정 단순화 측면과 생산성 향상 측면에서 유리하다.As described above, the present invention forms a vertical via hole in the first dry etching process using the photoresist pattern as an etch mask, removes the photoresist pattern, and then inclines the vertical via hole in the second dry etching process, thereby breaking the existing photoresist pattern. In addition to preventing the phenomenon and the lifting phenomenon, it is possible to improve the electrical properties and yield of semiconductor devices by preventing the attack of the exposed areas and stabilization of the process during the conventional dry etching process, and the conventional wet etching process Compared with dry etching, it is advantageous in terms of process simplification and productivity.
Claims (7)
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| KR1019980061429A KR20000044926A (en) | 1998-12-30 | 1998-12-30 | Method for forming via hole of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980061429A KR20000044926A (en) | 1998-12-30 | 1998-12-30 | Method for forming via hole of semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100781445B1 (en) | 2006-08-31 | 2007-12-03 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal layer in semiconductor device |
| KR101027558B1 (en) * | 2003-07-16 | 2011-04-08 | 매그나칩 반도체 유한회사 | Method for forming metal wires in a semiconductor device |
| CN102903671A (en) * | 2012-10-12 | 2013-01-30 | 江阴长电先进封装有限公司 | Method for forming novel chip back-side TSV (through silicon via) structure |
| CN106829848A (en) * | 2017-03-18 | 2017-06-13 | 安徽北方芯动联科微系统技术有限公司 | MEMS chip and its manufacture method with back side circular arc seamed edge |
| CN111584423A (en) * | 2020-05-20 | 2020-08-25 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
-
1998
- 1998-12-30 KR KR1019980061429A patent/KR20000044926A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101027558B1 (en) * | 2003-07-16 | 2011-04-08 | 매그나칩 반도체 유한회사 | Method for forming metal wires in a semiconductor device |
| KR100781445B1 (en) | 2006-08-31 | 2007-12-03 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal layer in semiconductor device |
| CN102903671A (en) * | 2012-10-12 | 2013-01-30 | 江阴长电先进封装有限公司 | Method for forming novel chip back-side TSV (through silicon via) structure |
| CN106829848A (en) * | 2017-03-18 | 2017-06-13 | 安徽北方芯动联科微系统技术有限公司 | MEMS chip and its manufacture method with back side circular arc seamed edge |
| CN111584423A (en) * | 2020-05-20 | 2020-08-25 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN111584423B (en) * | 2020-05-20 | 2022-11-25 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
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