KR20000041386A - Mos transistor manufacturing method - Google Patents
Mos transistor manufacturing method Download PDFInfo
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- KR20000041386A KR20000041386A KR1019980057245A KR19980057245A KR20000041386A KR 20000041386 A KR20000041386 A KR 20000041386A KR 1019980057245 A KR1019980057245 A KR 1019980057245A KR 19980057245 A KR19980057245 A KR 19980057245A KR 20000041386 A KR20000041386 A KR 20000041386A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 5
- 230000007547 defect Effects 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 4
- 238000000151 deposition Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 모스 트랜지스터 제조방법에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing a MOS transistor.
모스 트랜지스터는 거의 모든 반도체 소자의 가장 기본적인 구성 요소로서, 반도체 소자의 고집적화와 더불어 미세화에 따른 제반 전기적 특성 문제가 큰 이슈(issue)로 대두되고 있다.The MOS transistor is the most basic component of almost all semiconductor devices. As a result, high integration of semiconductor devices and various electrical characteristics due to miniaturization have emerged as major issues.
첨부된 도면 도 1a 내지 도 1d는 종래기술에 따른 모스 트랜지스터 제조 공정도로서, 이하 이를 참조하여 종래의 공정을 살펴본다.1A to 1D are MOS transistor manufacturing process diagrams according to the prior art, and a description will now be made of a conventional process with reference to this.
우선, 도 1a에 도시된 바와 같이 실리콘 기판(1) 상에 소자분리막(2)을 형성하여 활성영역을 디파인하고, 게이트 산화막(3)을 매개로 하는 게이트 전극 패턴(4)을 형성한다.First, as shown in FIG. 1A, an isolation layer 2 is formed on a silicon substrate 1 to define an active region, and a gate electrode pattern 4 is formed through the gate oxide layer 3.
다음으로, 도 1b에 도시된 바와 같이 전체구조 상부에 산화막(5)을 800Å 정도의 두께로 증착한다.Next, as shown in FIG. 1B, an oxide film 5 is deposited on the entire structure to a thickness of about 800 kPa.
계속하여, 도 1c에 도시된 바와 같이 산화막(5)을 전면 건식 식각하여 게이트 전극 패턴(4) 측벽에 산화막 스페이서(5a)를 형성한다. 이때, 전면 건식 식각을 수행함에 있어서, 식각 레지듀(residue)를 잔류를 방지하기 위하여 과도식각 타겟을 100% 정도로 설정하여 수행하게 된다.Subsequently, as shown in FIG. 1C, the oxide film 5 is entirely dry-etched to form the oxide film spacer 5a on the sidewall of the gate electrode pattern 4. At this time, in performing the dry dry etching, the transient etching target is set to about 100% in order to prevent the etching residue from remaining.
이어서, 도 1d에 도시된 바와 같이 이온주입된 소오스/드레인 이온주입을 실시하고, 이온주입된 도펀트를 활성화시키기 위해 열처리를 실시함으로써 소오스/드레인(6)을 형성한다.Subsequently, the source / drain 6 is implanted by ion implantation as shown in FIG. 1D, and heat treatment is performed to activate the ion implanted dopant.
이러한 공정을 통해 형성되는 모스 트랜지스터는 첨부된 도면 도 2에 도시된 바와 같이 게이트 스페이서(23)가 실리콘 기판(20)과 이루는 각도는 85° 이상을 보이며, 이를 이온주입 마스크로 사용하여 주입된 높은 농도의 도펀트들이 실리콘 기판(20)으로 주입될 때, 게이트 스페이서(23) 아래 부분에 형성되는 이온주입으로 인한 비정질층(소오스/드레인(24))의 양상이 거의 수직한 모양으로 형성되게 된다. 이렇게 형성되는 비정질층(24)은 열처리에 의해 재결정화 되는데, 이때 수직하게 변화되는 비정질층(24)의 모서리 부분에서는 실리콘 기판(20)의 결정면과 나란한 (100)면의 결정화 속도에 비해 실리콘 기판(20)과 거의 수직하게 형성되는 면들인 (122)면, (111)면, (211)면 등의 결정화 속도가 늦기 때문에 결정면들이 정확하게 맞지 않는 현상이 발생하여 많은 응력을 발생시킨다. 이러한 현상을 오정합된 낫치 효과(mismatched notch effect)라 하며, 이 결과로 이 부위에서는 과도하게 발생하는 응력으로 인해 다른 부위에서 보다 더욱 많은 이온주입 결함(25)이 유발되어 모스 트랜지스터의 접합 누설전류를 증가시키는 등 전기적 특성을 저하시키는 요인으로 작용하는 문제점이 있었다.As shown in FIG. 2, the MOS transistor formed through such a process has an angle formed by the gate spacer 23 with the silicon substrate 20 to be greater than or equal to 85 °, and is implanted using the MOS transistor as an ion implantation mask. When concentration dopants are implanted into the silicon substrate 20, an aspect of the amorphous layer (source / drain 24) due to ion implantation formed under the gate spacer 23 is formed in a substantially vertical shape. The amorphous layer 24 formed as described above is recrystallized by heat treatment. At this time, at the corners of the amorphous layer 24 that are vertically changed, the silicon substrate 20 is parallel to the crystallization rate of the (100) plane parallel to the crystal plane of the silicon substrate 20. Since the crystallization rate of the (122) plane, the (111) plane, and the (211) plane, which are planes which are formed almost perpendicular to the (20), is slow, crystal planes do not exactly fit, and a lot of stress is generated. This phenomenon is called mismatched notch effect, and as a result, excessive stress in this region causes more ion implantation defects (25) than in other regions, resulting in the junction leakage current of the MOS transistor. There was a problem that acts as a factor to decrease the electrical characteristics, such as increasing.
첨부된 도면 도 3은 종래기술에 따라 형성된 모스 트랜지스터의 주사전자현미경(SEM) 사진도로서, 앞서 설명한 바와 같은 오정합된 낫치 효과로 인해 소오스/드레인의 모서리 부분에서 급격한 각도 변화를 유발하는 낫치가 형성되어 이온주입 결함(화살표로 표시됨)을 유발함을 나타내고 있다.FIG. 3 is a scanning electron microscope (SEM) photograph of a MOS transistor formed according to the prior art, in which a hatch causing a sharp angle change at the corner of the source / drain due to the mismatched natch effect as described above. Formed to cause ion implantation defects (indicated by arrows).
본 발명은 소오스/드레인 모서리 부분에서 완만한 프로파일을 확보하여 이온주입 결함을 줄일 수 있는 모스 트랜지스터 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS transistor manufacturing method capable of reducing ion implantation defects by securing a gentle profile at source / drain edges.
도 1a 내지 도 1d는 종래기술에 따른 모스 트랜지스터 제조 공정도.1A to 1D are MOS transistor manufacturing process diagrams according to the prior art.
도 2는 종래기술에 따라 제조된 모스 트랜지스터의 단면도.2 is a cross-sectional view of a MOS transistor manufactured according to the prior art.
도 3은 종래기술에 따라 형성된 모스 트랜지스터의 주사전자현미경(SEM) 사진도.3 is a scanning electron microscope (SEM) photograph of a MOS transistor formed according to the prior art.
도 4는 본 발명의 일 실시예에 따라 형성된 모스 트랜지스터의 단면도.4 is a cross-sectional view of a MOS transistor formed according to an embodiment of the present invention.
도 5는 본 발명의 일 실시예에 따라 형성된 모스 트랜지스터의 주사전자현미경(SEM) 사진도.5 is a scanning electron microscope (SEM) photograph of a MOS transistor formed in accordance with an embodiment of the present invention.
도 6은 채널 길이에 따른 채널의 펀치쓰루 전압(BVDSS)의 변화를 도시한 그래프.FIG. 6 is a graph illustrating a change in punchthrough voltage BVDSS of a channel according to a channel length. FIG.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
40 : 실리콘 기판 41 : 게이트 산화막40: silicon substrate 41: gate oxide film
42 : 게이트 전극 43 : 측벽 스페이서42 gate electrode 43 sidewall spacer
44 : 소오스/드레인44: source / drain
본 발명은 소오스/드레인의 모서리 부분이 완만한 곡선을 나타내도록 하는 게이트 측벽 스페이서 형성 조건을 제안한다. 즉, 800∼1200Å의 두께로 절연막을 형성하고, 저스트 에치 후 10%∼30%의 범위에서 식각 타겟을 설정하여 과도 식각한다.The present invention proposes a gate sidewall spacer formation condition such that the corner portions of the source / drain exhibit a gentle curve. That is, an insulating film is formed in the thickness of 800-1200 GPa, and over etching is performed by setting an etching target in 10 to 30% of range after just etching.
따라서, 상기 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 특징적인 모스 트랜지스터 제조방법은, 게이트 전극 패턴이 형성된 반도체 기판 전체구조 상부에 800∼1200Å의 두께의 절연막을 형성하는 단계; 상기 절연막을 전면 건식 식각하여 측벽 스페이서를 형성하는 단계; 상기 10%∼30% 범위에서 식각 타겟을 설정하여 상기 절연막의 과도 식각을 수행하는 단계; 및 상기 측벽 스페이서를 이온주입 마스크로 사용하여 소오스/드레인 이온주입을 실시하는 단계를 포함하여 이루어진다.Accordingly, in order to achieve the above technical problem, a characteristic MOS transistor manufacturing method provided by the present invention includes: forming an insulating film having a thickness of 800 to 1200 Å on an entire structure of a semiconductor substrate on which a gate electrode pattern is formed; Dry etching the insulating film to form sidewall spacers; Performing an excessive etching of the insulating film by setting an etching target in the range of 10% to 30%; And performing source / drain ion implantation using the sidewall spacer as an ion implantation mask.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 4는 본 발명의 일 실시예에 따라 형성된 모스 트랜지스터의 단면을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.4 is a cross-sectional view of a MOS transistor formed according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the accompanying drawings.
우선, 본 실시예에서는 게이트 산화막(41) 및 게이트 전극(42) 형성 후, 전체구조 상부에 스페이서용 산화막을 800Å∼1200Å의 두께로 형성하고, 이를 전면 건식 식각하여 측벽 스페이서(43)를 형성한다. 여기서, 전면 건식 식각은 저스트 에치(just etch) 후, 10%∼30% 범위에서 과도 식각 타겟을 설정하여 과도 식각을 수행함으로써 측벽 스페이서(43)와 실리콘 기판(40)이 이루는 각도가 80° 이하로 나타나도록 한다.First, in the present embodiment, after the gate oxide film 41 and the gate electrode 42 are formed, a spacer oxide film is formed on the entire structure to a thickness of 800 Å to 1200 Å, and the entire surface is etched to form sidewall spacers 43. . In this case, the front dry etching is performed after the just etch, and by performing the excessive etching by setting the transient etching target in the range of 10% to 30%, the angle between the sidewall spacer 43 and the silicon substrate 40 is 80 ° or less. To appear.
특히 실험 결과, 측벽 스페이서(43)와 실리콘 기판(40)이 이루는 각도가 80°보다 낮은 경우에, 첨부된 도면 도 5에 도시된 주사전자현미경 사진에 나타난 바와 같이 소오스/드레인(44)의 모서리 부분에서 급격한 프로파일의 변화가 발견되지 않음을 미루어 볼 때, 80°의 각도가 그 임계점임을 확인하였다.Particularly, as a result of the experiment, when the angle formed between the sidewall spacer 43 and the silicon substrate 40 is lower than 80 °, the edge of the source / drain 44 as shown in the scanning electron micrograph shown in FIG. Considering that no sudden change of profile was found in the part, it was confirmed that the angle of 80 ° is the critical point.
이후, 측벽 스페이서(43)를 이온주입 마스크로 사용하여 소오스/드레인 이온주입을 실시하고, 이온주입된 도펀트를 활성화를 위한 열처리를 실시하여 소오스/드레인(44)을 형성한다. 이때, 이온주입은 p+소오스/드레인의 경우 도펀트로11B+또는 BF2 +를 사용하는데,11B+이온주입의 경우 1∼50keV의 이온주입 에너지, BF2 +의 경우 2∼100keV의 이온주입 에너지를 각각 사용하며, 도즈(dose)는 1×1015∼1×1016ions/㎠의 조건으로 실시한다. 그리고, n+소오스/드레인의 경우 도펀트로 As+또는 P+11을 사용하는데, As+이온주입의 경우 2∼100keV의 이온주입 에너지, P+11의 경우 2∼70keV의 이온주입 에너지를 각각 사용하며, 도즈(dose)는 1×1015∼1×1016ions/㎠의 조건으로 실시한다. 또한, 열처리는 노(furnace) 열처리 또는 급속 열처리(RTA) 모두가 적용 가능한데, 노 열처리의 경우 800∼950℃의 N2분위기에서 10분∼30분 동안 실시하며, 급속 열처리의 경우 900∼1050℃의 N2분위기에서 5초∼30초 동안 실시한다.Thereafter, the source / drain ion implantation is performed using the sidewall spacer 43 as an ion implantation mask, and the source / drain 44 is formed by performing heat treatment for activation of the ion implanted dopant. In this case, the ion implantation uses 11 B + or BF 2 + as a dopant for p + source / drain, and the ion implantation energy of 1 to 50 keV for 11 B + ion implantation and 2 to 100 keV for BF 2 + ion Injection energy is used, respectively, and the dose is performed under the conditions of 1 × 10 15 to 1 × 10 16 ions / cm 2. In the case of n + source / drain, As + or P +11 is used as a dopant, and As + ion implantation uses 2 to 100 keV ion implantation energy and P +11 uses 2 to 70 keV ion implantation energy, respectively. Dose is carried out under the conditions of 1 × 10 15 to 1 × 10 16 ions / cm 2. Furnace heat treatment or rapid heat treatment (RTA) can be used for both the heat treatment, and the furnace heat treatment is carried out for 10 minutes to 30 minutes in N 2 atmosphere of 800 ~ 950 ℃, 900 ~ 1050 ℃ for rapid heat treatment 5 seconds to 30 seconds in an N 2 atmosphere.
이처럼 소오스/드레인(44) 모서리 부분의 프로파일을 완만하게 형성하면, 이온주입 후의 열처리에 의해 결정화가 이루어질 때, 재결정화되는 면지수의 변화를 완화시키게 되므로, 상대적으로 응력장의 크기도 감소하여, 이온주입에 의해 형성된 결함을 열처리시 쉽게 제거할 수 있게 된다. 이에 따라, 종래에 비해 크게 개선된 전기적 특성을 기대할 수 있게 된다.Thus, when the profile of the corner portion of the source / drain 44 is formed smoothly, when the crystallization is performed by heat treatment after ion implantation, the change of the surface index to be recrystallized is alleviated, so that the magnitude of the stress field is relatively reduced, Defects formed by the injection can be easily removed during the heat treatment. Accordingly, it is possible to expect greatly improved electrical characteristics compared to the prior art.
첨부된 도면 도 6은 채널 길이에 따른 채널의 펀치쓰루 전압(BVDSS)의 변화를 도시한 그래프로서, 종래와 같이 측벽 스페이서용 산화막의 두께가 800Å인 경우, 채널 길이가 감소함에 따라 채널의 펀치쓰루 특성이 더욱 쉽게 열화됨을 확인할 수 있다.6 is a graph illustrating a change in punchthrough voltage (BVDSS) of a channel according to a channel length. When the thickness of the oxide film for sidewall spacers is 800 μs as in the related art, the punchthrough of the channel is reduced as the channel length decreases. It can be seen that the properties deteriorate more easily.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예를 들어, 전술한 일 실시예에서는 측벽 스페이서 형성을 위해 산화막을 사용하는 것을 일례로 들어 설명하였으나, 본 발명은 질화막과 같은 절연막을 사용하여 측벽 스페이서를 형성하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the use of an oxide film for forming sidewall spacers is described as an example. However, the present invention may be applied to the case of forming sidewall spacers using an insulating film such as a nitride film.
전술한 본 발명은 모스 트랜지스터의 소오스/드레인의 모서리 부분의 프로파일을 완만하게 형성하여 이온주입 결함을 억제함으로써 접합 누설전류를 저감시키는 효과가 있으며, 또한 고집적화된 소자에서 펀치쓰루 특성을 개선하는 효과가 있다.The present invention has the effect of reducing the junction leakage current by forming a profile of the edge of the source / drain of the MOS transistor smoothly to suppress the ion implantation defects, and also improve the punch-through characteristics in the highly integrated device have.
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