KR19990074547A - Indium tin oxide etchant and manufacturing method of the liquid crystal display device using the same - Google Patents

Abstract

ITO etching solution according to an embodiment of the present invention consists of HCl + CH ₃ COOH + HNO ₃ + H ₂ O. Here, the content of acetic acid is less than 37% in order to reduce the change over time, the content of nitric acid is preferably in the range of 0.2 ~ 0.6 vol% in order to increase the etching ratio to the ITO film and not to corrode the wiring made of molybdenum alloy. Do.

Description

Indium tin oxide etchant and manufacturing method of the liquid crystal display device using the same

The present invention relates to an etchant for ITO and a method of manufacturing a liquid crystal display device using the same.

In general, a display device is an electro-optical device used to convert an electrical signal into a visual image so that a human can directly recognize information.

Among such display devices, a liquid crystal display device is a display device that uses an optical property of a liquid crystal by changing an arrangement of liquid crystal molecules by applying an electric field. In this case, an electrode is required to apply an electric field, and this electrode is required to have conductivity and transparency, and suitable ITO (indium tin oxide) is mainly used.

The liquid crystal display device manufacturing method includes forming a wiring made of a metal, forming a protective film covering the wiring, and laminating and patterning an ITO film to form a transparent electrode. In general, the etchant used to pattern the ITO film is HCl + HNO ₃ + H ₂ O, and the wiring has low resistance to aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), molybdenum alloy (Mo alloy), etc. Use the same metal material. However, since the metal material, in particular, molybdenum or molybdenum alloy is well eroded by HCl + HNO ₃ + H ₂ O etchant, when the protective film formed between the wiring and the ITO film is damaged or minute holes are formed In particular, a problem arises in that the source / drain electrodes under the passivation layer and the metal wires connected thereto are disconnected.

When the etching solution is used as the HCl + CH ₃ COOH + H ₂ O to improve this problem, the molybdenum or molybdenum alloy is not eroded, even if the protective film is damaged or fine holes are formed, the wiring is not disconnected.

However, the etching solution HCl + CH ₃ COOH + H ₂ O is only half the etch ratio compared to HCl + HNO ₃ + H ₂ O, HCl + CH ₃ COOH + H ₂ O is HCl + HNO ₃ + H ₂ The change over time is severe compared to O. That is, as time passes, there is a problem that the etching ratio is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide an etching solution for ITO having excellent etching ratio under a condition that changes little with time and does not corrode wiring.

1 is a graph showing the rate of change of the etch ratio of the ITO membrane with time changes with respect to the content of acetic acid (CH ₃ COOH) contained in the etchant for ITO according to an embodiment of the present invention,

2 is a graph showing the etching ratio of the ITO film to the etching solution for ITO according to an embodiment of the present invention,

3 is a plan view showing the structure of a thin film transistor substrate according to an embodiment of the present invention;

4 is a cross-sectional view taken along the line II-II 'of FIG. 3,

5A through 5D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

ITO etching solution according to the present invention for solving this problem is HCl + CH ₃ COOH + HNO ₃ + H ₂ O.

At this time, in order to reduce the change over time, the content of CH ₃ COOH is preferably 37 vol% or less. In the case of forming the wiring with a metal material such as molybdenum or molybdenum alloy, the content of HNO ₃ is preferably in the range of 0.2 to 0.6 vol% in order to increase the etching ratio.

Here, the content of HCl is 17 vol% or less.

The etchant according to the present invention is used when the ITO film is patterned in the method of manufacturing a liquid crystal display device using the ITO film as a transparent conductive film and using signal wirings such as gate lines or data lines as molybdenum or molybdenum alloy.

Then, embodiments of the ITO etchant and a method of manufacturing a liquid crystal display device using the same according to the present invention will be described in detail with reference to the accompanying drawings so that a person having ordinary skill in the art can easily carry out the present invention. do.

Figure 1 shows the rate of change of the etch ratio of the ITO membrane according to the change over time with respect to the content of acetic acid (CH ₃ COOH) contained in HCl + CH ₃ COOH + HNO ₃ + H ₂ O as an etchant for ITO according to an embodiment of the present invention It is a graph shown.

Here, the horizontal axis represents the content rate (vol%) of CH ₃ COOH, and the vertical axis represents the etching rate change rate after 6 hours have elapsed.

At this time, the etch rate is the change rate of the etch ratio on the basis of 5 Å / sec, nitric acid is 0.4 vol%, hydrochloric acid is 16.15 vol%.

As shown in Figure 1, as a result of etching the ITO membrane using the etching solution HCl + CH ₃ COOH + HNO ₃ + H ₂ O according to the present invention, when the acetic acid content is more than 37vol%, the rate of change of the etch rate After 6 hours had elapsed based on 5 ms / sec, the measurement was over 2.0 ms / sec. That is, after 6 hours elapsed due to the volatility of acetic acid, the etching ratio to HCl + CH ₃ COOH + HNO ₃ + H ₂ O changes by more than 40%, it can be seen that the reliability of the process is less. However, it can be seen that as the amount of acetic acid is reduced, the rate of change of the etching rate decreases. Therefore, when the content of acetic acid in the etching solution HCl + CH ₃ COOH + HNO ₃ + H ₂ O to 37 vol% or less, it can be used as a stable etching solution in the process.

2 is a graph showing the etching ratio of the ITO film to the etching solution for ITO according to an embodiment of the present invention.

Here, the horizontal axis represents the content of HNO ₃ (vol%), and the vertical axis represents the etching ratio of the ITO membrane.

At this time, acetic acid was 37 vol% or less and hydrochloric acid was 16.15 vol%.

As shown in FIG. 2, as a result of etching the ITO membrane using the etching solution HCl + CH ₃ COOH + HNO ₃ + H ₂ O according to the present invention, when nitric acid is added at 0.2 vol% or more, the etching ratio of the ITO membrane is added to nitric acid. It is increased more than twice as much as it did not, and when the nitric acid is added at 0.4 vol% or more, the etching ratio of the ITO film is almost constant. Therefore, in the case of etching the ITO membrane using the etching solution HCl + CH ₃ COOH + HNO ₃ + H ₂ O according to the present invention, the content of nitric acid is preferably set to 0.2 vol% or more. However, when the content of nitric acid is more than 0.6 vol%, the molybdenum or molybdenum alloy, especially the molybdenum-tungsten alloy (MoW alloy), corrodes the molybdenum-tungsten alloy film containing 10 wt% of tungsten and thus the content of nitric acid is 0.6 vol%. It is preferable to set it as follows.

Next, a manufacturing method of the liquid crystal display device according to the present invention to which the etchant for ITO is applied will be described with reference to the drawings.

3 is a plan view illustrating a structure of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line II-II 'of FIG. 3.

A gate pattern including a gate line 200, a branch of the gate electrode 210, and a gate pad 220 formed at an end of the gate line 200 is formed on the substrate 100. The gate electrode 210 and the gate pad 220 each consist of a lower aluminum film or an aluminum alloy film 211 and 221 and an upper molybdenum-tungsten alloy film 212 and 222. The gate line 200 is also made of aluminum. Or a double film of an aluminum alloy film and a molybdenum-tungsten alloy film. The gate pad 220 transmits a scan signal from the outside to the gate line 200.

A gate insulating layer 300 is formed on the gate patterns 200, 210, and 220, and the gate insulating layer 300 has a contact hole exposing the molybdenum-tungsten alloy film 222, which is an upper layer of the gate pad 220. Have 720. On the gate insulating layer 300 above the gate electrode 210, a hydrogenated amorphous silicon (a-Si: H) layer 400 and a contact resistance between the channel layer and the source / drain electrodes for forming the channel layer of the thin film transistor. Hydrogenated amorphous silicon layers 510 and 520 that are heavily doped with n + impurities, which are contact layers to reduce the amount of impurities, are formed on both sides of the gate electrode 210.

A data line 600 is also vertically formed on the gate insulating layer 300, and a data pad 630 is formed at one end thereof to transmit an image signal from the outside. A source electrode 610, which is a branch of the data line 600, is formed on one doped amorphous silicon layer 510, and a drain electrode is disposed on the doped amorphous silicon layer 520 opposite to the source electrode 610. 620 is formed. The data pattern including the data line 600, the source and drain electrodes 610 and 620, and the data pad 630 may be formed of a molybdenum film or a molybdenum-tungsten alloy film.

A passivation layer 700 is formed on the data patterns 600, 610, 620, and 630 and the amorphous silicon layer 500 that is not covered by the data pattern, and the passivation layer 700 includes the upper molybdenum layer of the gate pad 220. Contact holes 720, 710, and 730 exposing the tungsten alloy film 222, the drain electrode 620, and the data pad 630 are formed, respectively.

Lastly, the passivation layer 700 is connected to the drain electrode 620 through the contact hole 710, and the pixel electrode 800 made of ITO is formed, and the gate pad 220 exposed through the contact hole 720 is formed. ) Is connected to the data pad 630 through the ITO electrode 810 for the gate pad and the contact hole 730 to transmit a signal from the outside to the gate line 200, and transmits a signal from the outside to the data line 600. A data pad ITO electrode 820 is formed.

5A through 5D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Next, a method of manufacturing the thin film transistor substrate having the structure shown in FIGS. 3 and 4 will be described with reference to FIGS. 5A to 5D. The manufacturing method proposed in this embodiment is a manufacturing method using five masks.

As shown in FIG. 5A, an aluminum film or an aluminum alloy film and a molybdenum-tungsten alloy film are sequentially stacked on the transparent insulating substrate 100, and photo-etched using a first mask to form a gate line 200 and a gate electrode 210. And a gate pad 220 to form a gate pattern formed of a double layer. That is, as shown in FIG. 5A, the gate electrode 210 is an aluminum or aluminum alloy film 211 below and a molybdenum-tungsten alloy film 212 above, and the gate pad 220 is an aluminum or aluminum alloy below. The film 221 and the molybdenum-tungsten alloy film 222 above, although not shown in Figure 5a, the gate line 210 is also made of a double film.

The gate pattern may be formed of a single layer by depositing one of aluminum, an aluminum alloy, molybdenum, and molybdenum-tungsten alloy.

As shown in FIG. 5B, a gate insulating layer 300 made of silicon nitride, a hydrogenated amorphous silicon layer 400, and a hydrogenated amorphous silicon layer 500 doped with a high concentration of N-type impurities are sequentially stacked. Thereafter, the doped amorphous silicon layer 500 and the amorphous silicon layer 400 are photo-etched using a second mask.

As shown in FIG. 5C, after the molybdenum-tungsten alloy film including molybdenum or tungsten is stacked, the wafer is wet-etched using a third mask to form the data line 600, the source electrode 610, the drain electrode 620, and the like. A data pattern including the data pad 630 is formed.

The data pattern may be formed of a single film of molybdenum or molybdenum alloy or a double film in combination thereof. In addition, in order to lower the resistance, an aluminum film or an aluminum alloy film may be added to the lower portion of the molybdenum film or molybdenum alloy film. In particular, in the case of molybdenum alloys, molybdenum-tungsten alloys containing about 10 wt% of tungsten are used.

Subsequently, the exposed doped amorphous silicon layer 500 is etched using the data patterns 600, 610, 620, and 630 as a mask to be separated from both sides around the gate electrode 210, while the doped amorphous silicon layer ( The amorphous silicon layer 400 between 510 and 520 is exposed.

As shown in FIG. 5D, after the protective film 700 made of silicon nitride is stacked, the fourth molybdenum-tungsten alloy film 222 of the gate pad 220 is photographed and etched together with the insulating film 300. Contact holes 720, 710, and 730 exposing the drain electrode 620 and the data pad 630.

Finally, as shown in FIG. 4, the ITO is stacked and etched using a fifth mask to be connected to the drain electrode 620 and the data pad 630 through the contact holes 710 and 730, respectively. An ITO pattern including the 800 and the ITO electrode 820 for the data pad and the gate pad ITO electrode 810 connected to the gate pad 220 through the contact hole 720 is formed.

At this time, the ITO membrane is etched using an etchant consisting of HCl + CH ₃ COOH + HNO ₃ + H ₂ O, it is preferable to reduce the content of acetic acid to 37 vol% or less in order to reduce the etch rate change rate with respect to the change over time.

In addition, in order to increase the etch ratio of the ITO film to the etching solution HCl + CH ₃ COOH + HNO ₃ + H ₂ O, the content of nitric acid is preferably at least 0.2 vol%, the protective film 700 during the etching is damaged to the etching solution In order to prevent penetration into the lower portion of the passivation layer 700 to erode the data patterns 600, 610, 620, and 630, the content of nitric acid is preferably set to 0.6 vol% or less.

At this time, the content of hydrochloric acid (HCl) is 17 vol% or less.

Therefore, in the method for manufacturing the etchant for ITO and the liquid crystal display according to the present invention, the etchant for ITO HCl (~ 17 vol%) + CH ₃ COOH (~ 37 vol%) + HNO ₃ (0.2 to 0.6 vol%) + H ₂ By using O, the etching ratio of the ITO film can be increased under the condition that the wiring is not corroded. In addition, the stability of the process can be improved by reducing the change over time.

Claims (11)

ITO etchant consisting of HCl, CH ₃ COOH, HNO ₃ and H ₂ O In claim 1, An etching solution containing less than 37 vol% acetic acid in the etchant. In claim 1, The etchant containing nitric acid in the etchant ranges from 0.2 to 0.6 vol%. In claim 1, The etchant containing hydrochloric acid in the etchant is 17 vol% or less. Forming a gate pattern including a gate line, a gate pad, and a gate electrode on the substrate, Stacking a gate insulating film on the substrate; Forming a channel layer and a contact layer on the gate insulating layer; Forming a data line and a source / drain electrode, Forming a contact hole in the passivation layer to expose a portion of the drain electrode after laminating a passivation layer on the date line and the source / drain electrode; Laminating an ITO film which is a transparent conductive material, And forming a pixel electrode by etching the ITO film with an etchant consisting of HCl, CH ₃ COOH, HNO _3, and H ₂ O. In claim 5, The data pattern is made of a thin film transistor substrate for a liquid crystal display device comprising a molybdenum-tungsten alloy film composed of molybdenum or tungsten, molybdenum and unavoidable impurities. In claim 6, The protective film is a method of manufacturing a thin film transistor substrate for a liquid crystal display device made of silicon nitride. In claim 7, The content of acetic acid in the etchant is less than 37 vol% manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 8, The content rate of nitric acid in the etchant ranges from 0.2 to 0.6 vol%. In claim 9, A method of manufacturing a thin film transistor substrate for liquid crystal display device, wherein the content of hydrochloric acid in the etchant is 17 vol% or less. In claim 10, And a tungsten content ratio of the molybdenum-tungsten alloy film is 10 wt%.