KR19990060819A - Metal wiring formation method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device for simultaneously forming via contacts and metal wirings.

In the conventional method of forming the via contact and the metal wiring at the same time, since the metal plug is formed only at the portion where the via contact is to be formed, when the contact plug and the metal thin film of the metal wiring are the same material, they must be left for metal wiring formation due to overetching. Since the thickness uniformity of the metal thin film becomes poor, the reliability of the metal wiring is reduced.

In the present invention, an etching stop layer is formed between the metal layers to prevent excessive etching when the upper metal layer is etched to form a contact plug, thereby increasing the uniformity of metal wiring formation by maintaining the thickness uniformity of the lower metal layer without damaging the metal wiring process. Can improve the reliability.

Description

Metal wiring formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the metal wiring forming process of simultaneously forming a via contact and a metal wiring, by using an etch stop layer to prevent excessive etching, the thickness of the metal wiring can be maintained to maintain the reliability of the device A metal wiring formation method of a semiconductor element which can be improved.

As the semiconductor devices have higher integration, the contact sizes of the metal interconnections are reduced, the aspect ratio is further increased, and the via contact filling characteristics of the metal interconnects are deteriorated. Therefore, in order to improve the buried characteristics of the via contact, researches on a method of forming a metal wire for simultaneously forming a via contact and a metal wire are being actively conducted, which will be described with reference to FIGS. 1 (a) and 1 (b). Is as follows.

1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of simultaneously forming a conventional via contact and a metal wiring and a problem caused by the same.

Referring to FIG. 1A, a first metal wire 12 is formed by depositing and patterning a metal thin film on a semiconductor substrate 11 on which various elements for manufacturing a semiconductor device are formed. After the photoresist is coated on the first metal wire 12 and the position at which the via contact is to be formed is determined, the photoresist is patterned to form a photoresist pattern (not shown). The first metal wire 12 is etched using the photoresist pattern (not shown) as a mask to form a metal plug at a position where a via contact is to be formed to act as the via contact plug 13. The insulating oxide film 14 is deposited on the entire structure, and then planarized by performing a CMP process. And the 2nd metal wiring 15 is formed.

If the metal wiring is formed in this manner, the metal plug is formed at the position where the via contact is to be formed, thereby eliminating the need for a subsequent via contact filling process.

However, the method of simultaneously forming the via contact and the metal wiring has a disadvantage in that the process is complicated and difficult to control the process, thereby decreasing the uniformity between the wafer and the wafer to wafer. In particular, since the metal plug is formed only at the portion where the via contact is to be formed, when the contact plug and the metal thin film of the metal wiring are the same material, the excessive etching causes poor thickness uniformity of the metal thin film to be left for forming the metal wiring (16). ). This is shown in Figure 1 (b). That is, since the etch stop cannot be performed after the contact plug 15 is formed, the thickness of the metal thin film remaining for each position in the wafer is not constant. Therefore, since the thickness of the metal pattern is not constant, the reliability of the metal wiring is lowered.

Accordingly, the present invention solves the problem that the thickness uniformity of the metal wiring is poor due to excessive etching in the metal wiring forming process for simultaneously forming the contact plug and the metal wiring, thereby improving the reliability of the device. The purpose is to provide.

According to an aspect of the present invention, there is provided a method of sequentially forming a first metal layer, an etch stop layer, and a second metal layer on a semiconductor substrate on which various elements for manufacturing a semiconductor device are formed, and selected regions of the second metal layer. Forming a contact plug by removing the contact plug; forming a first metal wiring by removing selected regions of the etch stop layer and the first metal layer; and forming and planarizing an insulating oxide film on the entire structure, and then planarizing the insulating oxide film. And forming a third metal layer thereon.

1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of simultaneously forming a conventional via contact and a metal wiring and the problems thereof.

2 (a) to 2 (d) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

11 and 21: semiconductor substrate 12 and 26: first metal wiring

13, 24a: contact plug 14, 27: insulated oxide film

15. Second metal wiring 16: Metal wiring with poor thickness uniformity

22: first metal layer 23: etch stop layer

24: second metal layer 25: photosensitive film pattern

28: third metal layer

The present invention will be described in detail with reference to the accompanying drawings.

2 (a) to 2 (d) are cross-sectional views of devices for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

Referring to FIG. 2A, a first metal layer 22 is formed on a semiconductor substrate 21 on which various elements for manufacturing a semiconductor device are formed. An etch stop layer 23 and a second metal layer 24 are formed on the first metal layer 22.

Here, the etch stop layer 23 must be a metal and a material having a constant etch selectivity with the second metal layer 24. For example, when the second metal layer 24 is an aluminum thin film, the etch stop layer 23 may be formed of tungsten. In general, aluminum is etched in Cl-based gas, and tungsten is etched in fluorine-based gas. Therefore, the etch stop layer 23 may be formed of a metal having a high etching selectivity with the upper second metal layer 24.

Referring to FIG. 2B, after the photoresist is coated on the second metal layer 24, the photoresist pattern 25 is formed only on a portion where the contact plug is to be formed by performing a photo and etching process. The second metal layer 24 is etched using the photoresist pattern 25 as a mask to form a contact plug 24a, and then the photoresist pattern 25 is removed.

At this time, the lower first metal layer 22 is not damaged by the etch stop layer 23. In the conventional method without using the etch stop layer, since the contact plug and the lower metal layer are the same material, the upper part of the remaining metal layer for the patterning is damaged and the uniformity is significantly reduced.

Referring to FIG. 2C, the etch stop layer 23 and the first metal layer 22 are removed by an etching process using a mask for patterning the metal lines to form the first metal lines 26. The first metal wire 26 is formed of an etch stop layer 23 and a first metal layer 22 simultaneously patterned.

FIG. 2 (d) is a cross-sectional view of the third metal layer 28 formed on the entire structure after the insulating oxide film 27 is formed on the entire structure and planarized by the CMP process. The third metal layer 28 is then patterned and used as the second metal wiring.

As described above, according to the present invention, by forming an etch stop layer between the metal layers to prevent excessive etching, the thickness uniformity of the lower metal layer is maintained without damage, thereby increasing the uniformity of metal wiring formation and improving the reliability of the metal wiring process. can do.

Claims (3)

Sequentially forming a first metal layer, an etch stop layer, and a second metal layer on the semiconductor substrate on which various elements for manufacturing the semiconductor device are formed; Removing the selected region of the second metal layer to form a contact plug; Removing selected regions of the etch stop layer and the first metal layer to form a first metal wire; And forming a third metal layer on the insulating oxide film after forming and planarizing the insulating oxide film over the entire structure. The method of claim 1, wherein the etch stop layer is formed of a metal having high etching selectivity with respect to the second metal layer. The method of claim 1, wherein when the etch stop layer is an aluminum thin film, the second metal layer is a tungsten film.