KR19990060499A - Japanese satellite broadcasting decoder - Google Patents

Abstract

In the satellite broadcasting decoder, the core module operation controller for controlling the operation of the MULTI2 core module and the control signal output from the core module operation controller are input to output unit function start control and initial start command for each operation mode. And an input direction selector for selecting an input direction of the MULTI2 core module, and a multi2 core module for performing encryption and decryption according to the direction selected by the input direction selector. It is possible to handle the minimum area and the fast decoding, and to adapt to the increase in the half-time retrieval of the basic function for future encryption enhancement.

Description

Japanese satellite broadcasting decoder

The present invention relates to a decoder, and more particularly, to a satellite broadcast decoder that restores an encrypted digital signal to its original form to implement a limited reception function of Japanese digital satellite broadcasting.

When implementing digital satellite broadcasting, the satellite broadcasting receiver must have a decoder for restoring the encrypted data transmitted from the broadcasting station in order to implement a limited reception function so that only a limited receiver can listen to the broadcasting.

Generally, there are two types of decoders, a European decoder and a Japanese decoder, and the European decoder uses a common discrambler type decoder, and the Japanese type decoder uses a multi2 (MULTI2) algorithm decoder. Hereinafter referred to as MULTI2.

The MULTI2 algorithm is composed of four functions π1, π2, π3, and π4, which are used in parallel to perform encryption key generation and data encryption.

In the MULTI2 encryption process of the Japanese-type decoder configured as described above, as shown in FIG. 1, a key generation unit 1 generating a key and a system key generated by the key generation unit 1 are inputted to perform encryption. It consists of an encryption part 2.

The encryption unit 2 encrypts the basic functions π1, π2, π3, and π4 by repeating n times, which is N = 4 * n, and the encryption process is performed in units of upper 32 bits and lower 32 bits. Perform.

Eight system keys of 32 bits are used, and eight work keys of 32 bits are used when operating in an encryption or decryption mode.

When transmitting and encrypting data in real digital broadcasting, block-by-block encryption is linked by a chain structure so as to correlate between blocks, and encryption is performed. When the transmission data stream can be divided into 64 bits, the CBC mode is used. If there is a part remaining even after dividing, only the remaining part is encrypted by applying the OFB mode.

In order to decrypt the ciphertext encrypted in the CBC / OFB mode, a basic function needs to perform both an encryption and a decryption process, and thus requires a decryption and an encryption module, respectively.

The Japanese decoder according to the prior art repeatedly uses several basic functions in the MULTI2 algorithm, which is complicated in construction, high in manufacturing cost, and requires the same decryption and encryption module. .

The present invention has been devised to solve such a problem, and it is possible to simultaneously perform key generation and encryption with one basic function module by designing a decoder in hardware that meets the specifications prescribed for use in Japanese digital satellite broadcasting. The purpose is to provide a Japanese satellite broadcast decoder.

1 is a view showing a MULTI2 encryption process according to the prior art

2 is a diagram showing a MULTI2 basic function module according to the present invention;

3 is a control logic diagram implemented using the MULTI2 basic function of FIG.

4 is a data flow diagram of the MULTI2 core module in CBC / OFB mode.

5 is a block diagram showing a decoder for satellite broadcasting according to the present invention.

6 is a block diagram showing a Japanese satellite broadcasting decoder according to the present invention.

A satellite broadcasting decoder using a multi2 (MULTI2) core module, comprising: a core module operation controller for controlling the operation of the multi2 (MULTI2) core module and a control signal output from the core module operation controller to start a unit function An indicator for outputting an initial start command for each control and operation mode, an input direction selector for selecting an input direction of the MULTI2 core module, and encryption and decryption according to a direction selected by the input direction selector It is characterized by consisting of a Multi2 (MULTI2) core module.

Hereinafter, with reference to the accompanying drawings as follows.

FIG. 3 is a diagram illustrating a basic function configuration of the MULTI2 algorithm according to the present invention, and FIG. 4 is a MULTI2 control block diagram implemented using the basic function of FIG.

Referring to FIG. 2, a basic function composed of π1, π2, π3, and π4 unit function modules of the MULTI2 algorithm is used for encrypting data when a data key is input and data processing is performed in a forward direction such as π1 → π2 → π3 → π4. And decoding is performed in the order of? 4?? 3?? 2?? 1.

Therefore, the encryption process is performed at the time of key generation and in the OFB mode operation, and the decryption fixing is performed at the CBC mode operation. Since each unit function module is unidirectional, the input and output parts are fixed.

Since the core module consists of only four unit functions, only the lower four keys and the upper four keys can be used.

If the basic function module illustrated in FIG. 3 is defined as a multi2 (MULTI2) core, a control diagram for implementing the multi2 (MULTI2) algorithm as shown in FIG. 4 is implemented along with the control logic to control the core logic.

If you receive an operation mode command from a microcomputer (not shown) and enter the corresponding mode, you must repeat the basic function module as many times as necessary in each mode.

As shown in FIG. 3, referring to FIG. 4, a counter 31 for counting the number of times each basic function module is performed, an indicator 32 for notifying the start and end of each module operation, and A core module operation controller 33 for selecting an input value of an encrypted text, an output value of a decrypted text, and a flow direction of data according to the execution mode selected by the microcomputer (not shown), a key selector 34 for selecting a key, and A signal generation unit 35 for notifying a microcomputer (not shown) of the state of the core logic, an initial start indicator 36 for instructing unit function start control and an initial start for each operation mode, and the core module operation air 33 An input direction selector 37 which selects a forward or reverse input direction by receiving the control signal output from the input signal, and receives an output signal of the initial start indicator 36 and the input direction selector 37 and encrypts or decrypts the input signal. MULTI2 to perform It consists of a module (20).

Using the MULTI2 module function of FIG. 3 configured as described above, the structure shown with the buffer to realize the chain structure of the CBC / OFB mode for the incoming input stream is shown in FIG.

Referring to FIG. 5, when the input stream is stored and full, the input buffer REG1 transmits 64-bit data to the core module and is transmitted to the first delay buffer INTER_REG1. A first delay buffer INTER_REG1 that reads data transmitted from REG1, stores an initialization vector, and transmits data to a second delay buffer INTER_REG2 in synchronization with the transmission buffer of the input buffer REG1, and the first delay. In the transmission synchronization of the buffer INTER_REG1, the second delay buffer INTER_REG2 is transmitted to the second delay buffer INTER_REG2 through an XOR operation with a result value of the core module MULTI2 Core.

If the data streams are transmitted in the above order, the CBC mode can be implemented, and a slightly different processing method is provided to realize the OFB mode.

In the OFB mode, the core module (MULTI2 Core) uses the first delay buffer because it must use the last ciphertext (64-bit) that was previously entered instead of the last input (less than 64-bit) data stored in the input buffer REG1. Receive an input value from (INTER_REG1).

At this time, the final stream data is transmitted from the input buffer REG1 to the first delay buffer INTER_REG1, and the resultant value of the core module MULTI2 Core and the final stream stored in the first delay buffer INTER_REG1 are XOR-operated. Get the decrypted text for the stream.

However, in order to match the result of the core module (MULTI2 Core) with the calculation position of the maximum stream, the first delay buffer (INTER_REG1) internally shifts between registers to adjust the position in advance during the calculation of the core module (MULTI2 Core). Release.

6 is a block diagram showing a Japanese satellite broadcasting decoding apparatus according to the present invention.

As shown in FIG. 6, in a decoder using a MULTI2 core, an operation mode controller 51 defining a mode to be executed by the decoder, and a data transfer command generator 52 outputting an operation start command of the MULTI2 core module. And a core input selection control unit 53 for selecting one of the data input to the MULTI2 core, a work key register 54, a system key 55, and a key for selecting a key used in the MULTI2 core. A selector 56 and a data flow controller 57 select a data to be passed through the MULTI2 core logic and a value to pass through the XOR function.

The decoder for satellite broadcasting using the MULTI2 function configured as described above operates as follows.

The operation mode controller 51 defines a mode to be executed by the decoder, and gives an operation mode command to the core module and each control logic, thereby becoming one control signal for the control logic, and almost all control logics are in this mode. Will refer to the command.

The mode command is divided into a reset mode, a key generation mode, an encryption mode, and a decryption mode.

The reset mode is sent at the beginning of the decoder operation or while waiting for input data. When the new data is input, the reset mode is changed to the key generation mode. When the decoding ends, the reset mode returns to the reset mode.

After the key is generated in the key generation mode, if the state of the input buffer REG1 is full, it operates in decryption mode or in encryption mode.

With reference to the signal indicating that the decoding is completed in the decryption mode, when finished, go to the reset mode in the ready state, and if the state of the input buffer REG1 is not full in the situation that the input data stream is no longer in the encryption mode, Will go.

In addition, when decryption is completed in the encryption mode, the controller returns to the reset mode and is ready to receive the next input.

The data transfer command generator 52 outputs a command to start the operation of the MULTI2 core module. In response to the command, data output from the input buffer REG1 occurs, and the core and the first and second delay buffers INTER_REG1 are generated. Data transfer from INTER_REG2 to output buffer REG2 occurs.

The data transfer command includes the state (full or not) of the input buffer REG1 from the input buffer REG1 controller 60 and the state of the output buffer REG2 from the output buffer REG2 controller 62. In this case, the core ready state (ready or not) and the stream input start signal are viewed and the condition is satisfied.

In addition, at the beginning of the MPEG data stream input, the MULTI2 core first generates a work key for decrypting the body. The elements used are a system key and a data key.

The core input selection control unit 53 selects an 8-byte input that enters the MULTI2 core. The core input selection control unit 53 transfers the first data key and a data stream from the input buffer REG1 in the decryption mode, and the first delay buffer INTER_REG1 in the decryption mode. In the encryption mode, data is transmitted from the first delay buffer INTER_REG1.

At this time, when the core enters the encryption mode immediately after the key generation, that is, the initial input stream data is less than 8 bytes, the initial vector is input.

The data flow controller 56 selects a value that passes through the xor function together with the data from the MULTI2 core logic. The data flow controller 56 selects between the first delay buffer INTER_REG1 and the second delay buffer INTER_REB2. It is discriminated according to the transfer command and other control signals.

In particular, when the value of the final empty counter 57 of the output buffer REG2 is 1, data from the first delay buffer INTER_REG1 is obtained. Otherwise, the data of the second delay buffer INTER_REG2 is determined. Select a value.

On the other hand, when decoding the data stream, it is necessary to determine where the end of the decoded data is.

This is because a decoded signal does not come out immediately after the data stream is input, but a certain processing time is required, and a delay effect occurs according to the application of each mode.

Accordingly, the final output is controlled by counting the time point of the first data transfer command of the output buffer REG2 and the last time point transmitted to the output and checking the validity of the signal currently decoded.

The blocks used at this time are the REG2 Final Empty Counter 57, the REG2 Initial Fetch Counter 58, and the Data Validity Checker 59.

The input buffer REG1 controller 60 includes a counter that counts for each byte input of the input buffer REG1, a state detector that checks the full state of the input buffer REG1 with a counter, and a serial input stream based on these. It consists of an input controller that controls the acceptance and movement of register values.

An Align Counter 61 which receives an input value of the input buffer REG1 of the input buffer REG1 controller 60 and has an initial value and changes between internal register values of the first delay buffer INTER_REG1. ) And an output buffer (REG2) controller 62.

The align counter 61 is enabled to the value of the REG2 Final Empty Counter 57 and shifts the register value of the first delay buffer INTER_REG1 in order to match the position of the result value of the core module. The operation can be performed at (45).

The output buffer REG2 controller 62 includes a counter that counts for each byte output of the output buffer REG2, a state detector for checking an empty state of the output buffer REG2 with the counter, and a data valid detector. It consists of controlling the serial output and the register value movement based on the signal from the signal. The write enable signal is sent to the data output properly.

According to the present invention, in the Japanese decoder using the MULTI2 algorithm, the MULTI2 core module consists of only four unit functions, which enables the minimum area and the fast decoding processing, and can adapt to the increase in the number of iterations of the basic functions for future encryption. Can be.

Claims (3)

In a satellite broadcast decoder using a multi2 (MULTI2) core module, A core module operation controller for controlling an operation of the MULTI2 core module; An indicator for receiving a control signal output from the multiplexer operation controller and outputting a unit function start control and an initial start command for each operation mode; An input direction selector for selecting an input direction of the MULTI2 core module; And a multi-core (MULTI2) core module for performing encryption and decryption according to the direction selected by the input direction selector. The method of claim 1, The MULTI2 core module is a Japanese satellite broadcasting decoder, characterized in that the data is processed using a rounding feedback method in the order of π1 → π2 → π3 → π4 in case of encryption. The method of claim 1, The MULTI2 core module is a Japanese satellite broadcasting decoder characterized in that the data is processed using a rounding feedback method in the order of π4 → π3 → π2 → π1 when decoding.