KR19990048038A - Multi-layer printed circuit board manufacturing method - Google Patents
Multi-layer printed circuit board manufacturing method Download PDFInfo
- Publication number
- KR19990048038A KR19990048038A KR1019970066639A KR19970066639A KR19990048038A KR 19990048038 A KR19990048038 A KR 19990048038A KR 1019970066639 A KR1019970066639 A KR 1019970066639A KR 19970066639 A KR19970066639 A KR 19970066639A KR 19990048038 A KR19990048038 A KR 19990048038A
- Authority
- KR
- South Korea
- Prior art keywords
- printed circuit
- hole
- photosensitive insulating
- forming
- via hole
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
본 발명의 다층 인쇄회로기판 제조방법은 동박적층판의 양면에 금속을 도금하고 에칭하여 인쇄회로패턴을 형성하는 단계와, 동박적층판의 양면에 1회의 커틴코팅방법으로 감광성 절연수지층을 도포하고 현상하여 비어홀을 형성하는 단계와, 층간 도통용 스로우홀을 형성한 후 인쇄회로패턴, 감광성 절연수지층 및 스로우홀의 내벽에 Cu도금층을 형성하는 단계와, Cu도금층을 에칭하여 인쇄회로 패턴을 형성하는 단계로 구성된다.In the method of manufacturing a multilayer printed circuit board of the present invention, the steps of forming a printed circuit pattern by plating and etching metal on both sides of the copper-clad laminate, and applying and developing the photosensitive insulating resin layer on the both sides of the copper-clad laminate by one cuttin coating method. Forming via holes, forming a through hole for interlayer conduction, and then forming a Cu plating layer on inner walls of the printed circuit pattern, the photosensitive insulating resin layer, and the through hole; and etching the Cu plating layer to form a printed circuit pattern. It is composed.
Description
본 발명은 다층 인쇄회로기판에 관한 것으로, 특히 층간 접속이 향상된 빌드업 다층 인쇄회로기판(build-up multi-layer printed circuit board)의 제조방법에 관한 것이다.The present invention relates to a multilayer printed circuit board, and more particularly, to a method of manufacturing a build-up multi-layer printed circuit board with improved interlayer connection.
전자부품과 부품내장기술의 발달과 더불어 회로도체를 중첩하는 다층 인쇄회로기판이 개발된 이래, 최근 다층 인쇄회로기판(Mulit-Layer Board)의 고밀도화에 대한 연구가 더욱 활발히 진행되고 있다. 그중에서도 빌드업(build-up)방식에 의해 다층 인쇄회로기판을 제조하는 방법이 널리 사용되고 있는데, 이 방법은 종래의 일반적인 BHV(blind via hole)공법과는 달리 절연층과 회로도체층을 순차적으로 적층해서 다층회로를 형성하는 방법이다. 따라서, 빌드업에 의한 인쇄회로기판의 제조는 그 방법 자체가 간단할 뿐만 아니라 그에 따라 제조되는 다층 인쇄회로기판(즉, 빌드업 MLB)은 기판의 층간회로의 연결을 이루는 비어홀(via hole)의 형성이 용이하며, 극소경 비어홀의 형성이 가능하고 회로도체의 두께가 얇아 미세회로의 형성이 용이한 잇점을 가진다.Since the development of electronic components and component embedding technology and the development of multilayer printed circuit boards overlapping circuit conductors, research on the densification of multi-layer printed circuit boards (Mulit-Layer Board) has been actively conducted. Among them, a method of manufacturing a multilayer printed circuit board by a build-up method is widely used. Unlike the conventional BHV method, an insulating layer and a circuit conductor layer are sequentially stacked. It is a method of forming a multilayer circuit. Therefore, the manufacturing of the printed circuit board by the build-up is not only simple in itself, but also the multilayer printed circuit board (i.e., the build-up MLB) manufactured accordingly is formed by the via hole forming the connection of the interlayer circuits of the substrate. It is easy to form, it is possible to form the microscopic via hole, and the thickness of the circuit conductor is thin, which has the advantage of easy formation of microcircuits.
이러한 빌드업 MLB에 대한 제조방법이 일본 공개특허 (평)7-231171호에 개시되어 있다. 상기한 특허에 의하면, 도 1(a)∼도 1(f)에 나타낸 바와 같이, 내층회로(12)가 형성된 도체회로기판(10) 위에 1차 감광성 절연수지(14)을 도포하고 광을 조사하여 원하는 비어홀(20) 보다 큰 제1미노광부(15)를 형성한 후, 현상을 하지 않은 상태에서 연속해서 2차 감광성 절연수지(16)를 도포한다. 그 후, 다시 광을 조사하여 상기한 제1미노광부(15) 보다 작은 제2미노광부(17)를 형성한 후, 상기한 제1미노광부(15)와 제2미노광부(17)를 현상하여 비어홀(20)을 형성한다. 이어서, 자외선경화 및 열경화, 크롬산에 의한 조화형성, 도금용 레지스트(resist)를 형성한 다음, 그위에 무전해 Cu도금만으로 외층도체회로(30)를 형성하여 빌드업 MLB를 완성한다.A manufacturing method for such build-up MLB is disclosed in Japanese Patent Laid-Open No. 7-231171. According to the above patent, as shown in Figs. 1A to 1F, the primary photosensitive insulating resin 14 is coated on the conductor circuit board 10 on which the inner layer circuit 12 is formed and irradiated with light. By forming the first unexposed portion 15 larger than the desired via hole 20, the secondary photosensitive insulating resin 16 is applied continuously without developing. Thereafter, light is irradiated again to form a second unexposed portion 17 smaller than the first unexposed portion 15, and then the first unexposed portion 15 and the second unexposed portion 17 are developed. To form a via hole 20. Subsequently, UV curing and thermosetting, roughening by chromic acid, and a plating resist are formed, and then the outer layer conductor circuit 30 is formed only by electroless Cu plating to complete the build-up MLB.
그러나, 상기한 방법은 1차 및 2차노광에 의해 제1미노광부(15)와 제2노광부(17)를 미리 형성하고 상기한 제1미노광부(15)와 제2노광부(17)를 한꺼번에 현상하기 때문에, 도 1(d) 및 도 1(e)에 나타낸 바와 같이, 절연수지층의 두께로 인한 적절한 광량의 전달 부족으로 노광취약부(22)가 발생하여, 현상 후에는 극소경인 비어홀(20)이 입구측이 좁고 내층회로측이 넓어지는 형상으로 된다. 이와 같은 홀의 형상에 따라 무전해 Cu 도금시 도금액이 홀내에 원활히 공급되지 않게 되어 도금취약부가 발생하는데, 이는 도금접촉의 신뢰성저화를 야기시킨다.However, in the above method, the first unexposed portion 15 and the second exposed portion 17 are formed in advance by the first and second exposures, and the first unexposed portion 15 and the second exposed portion 17 are described above. 1 (d) and 1 (e), the exposure weakening portion 22 is generated due to lack of proper light quantity transfer due to the thickness of the insulating resin layer, and after development, the via hole having a very small diameter is developed. The inlet 20 is narrow and the inner circuit side is widened. According to the shape of the hole, the plating liquid is not smoothly supplied in the hole during electroless Cu plating, and thus the plating weakening portion is generated, which causes the reliability of the plating contact.
상기한 문제를 해결하기 위해, 장시간 노광을 실시하여 노광량을 충분히 부여하는 경우에도 절연수지의 균열과 과경화에 의한 미현상 혹은 비어홀경의 축소가 발생한다. 또한, 상기한 홀의 형상으로 인해 비어홀의 크기가 대체로 0.2mm 정도로 제약을 받아 비어홀 형성정도가 저하되며, 결국 다층 인쇄회로기판의 고밀도화가 크게 제한되는 문제가 있다.In order to solve the above-mentioned problems, even when long exposure is performed and sufficient exposure amount is given, undeveloped or via hole diameters are reduced due to cracking and overhardening of the insulating resin. In addition, due to the shape of the hole, the size of the via hole is generally limited to about 0.2 mm, which reduces the formation of the via hole, resulting in a problem that the density of the multilayer printed circuit board is greatly limited.
상기한 여러 가지 문제를 해결하기 위한 또 다른 다층 인쇄회로기판 제조방법이 본 출원인이 출원한 한국특허출원 1996-25304호에 개시되어 있다. 도 2는 상기한 특허에 개시된 다층 인쇄회로기판 제조방법을 나타내는 도면이다. 우선, 도 2(a)에 나타낸 바와 같이, 양면에 동박막이 부착된 동박적층판(copper clad laminate;10) 위에 통상의 사진식각을 통해 인쇄회로패턴(12)을 형성한 후, 흑화환원처리를한다. 이후, 도 2(b)에 나타낸 바와 같이, 흑화막이 형성된 기판(10)에 제1감광성 절연수지(14)를 스크린인쇄방법(screen printing process)으로 인쇄하고 반경화(pre-cure)한 후, 마스크를 사용해서 상기한 감광성 절연수지(14)에 광을 조사하고 현상하여 V자형 제1포토비어홀(22)을 형성한다. 이어서, 도 2(c)에 나타낸 바와 같이, 제1감광성 절연수지(14) 위에 제2감광성 절연수지(16)를 도포하고 현상하여 제1포토비어홀(22) 위에 제2포토비어홀(24)을 형성한 후, 도 2(d)에 나타낸 바와 같이 층간의 도통을 위한 관통홀(40)을 형성한 후 절연층 위에 무전해 Cu 도금과 전해 Cu 도금을 실시하여 회로도금층(130)을 형성한다.Another method for manufacturing a multilayer printed circuit board for solving the various problems described above is disclosed in Korean Patent Application No. 1996-25304 filed by the present applicant. 2 is a view showing a method for manufacturing a multilayer printed circuit board disclosed in the above patent. First, as shown in FIG. 2 (a), the printed circuit pattern 12 is formed on the copper clad laminate 10 having copper foil films on both sides by ordinary photolithography, and then blackening reduction treatment is performed. do. Thereafter, as shown in FIG. 2 (b), the first photosensitive insulating resin 14 is printed on the substrate 10 having the blackening film formed thereon by a screen printing process and then semi-cured. The photosensitive insulating resin 14 is irradiated with light and developed using a mask to form a V-shaped first photovia hole 22. Subsequently, as shown in FIG. 2C, the second photosensitive insulating resin 16 is coated and developed on the first photosensitive insulating resin 14 to develop the second photovia hole 24 on the first photovia hole 22. After forming, as shown in FIG. 2 (d), the through-hole 40 for interlayer conduction is formed, and then the circuit plating layer 130 is formed by performing electroless Cu plating and electrolytic Cu plating on the insulating layer.
상기한 방법에 의해 형성된 다층 인쇄회로기판은 도면에 나타낸 바와 같이, 제2비어홀(24)이 제1비어홀(22) 보다 크게 되어 전체적으로 V자 형상으로 된다. 실질적으로 제1비어홀(22)과 제2비어홀(24)의 크기를 제어하여 정확한 V자 형태의 비어홀을 형상하는 것은 매우 어렵기 때문에, 가장 바람직한 구조는 도 3에 나타낸 바와 같이, 제2비어홀(24)의 직경(d2)이 제1비어홀(22)의 직경(d1) 보다 약 1.05∼2.0배인 것이다.In the multilayer printed circuit board formed by the above-described method, as shown in the drawing, the second via hole 24 is larger than the first via hole 22 to have an overall V shape. Since it is very difficult to form the exact V-shaped via hole by controlling the sizes of the first via hole 22 and the second via hole 24 substantially, the most preferable structure is shown in FIG. The diameter d2 of 24 is about 1.05 to 2.0 times larger than the diameter d1 of the first via hole 22.
일반적으로 고안정, 고정세의 다층 인쇄회로기판을 제작하기 위해서는 두께가 약 50μm 이상인 절연수지층과 직경이 약 1mm 정도인 비어홀이 요구된다. 그러나, 상기한 특허(출원번호 1996-25304)에 개시된 방법에서는 절연수지층을 스크린프린팅방법에 도포하기 때문에, 두께가 약 50μm 이상인 절연수지층을 도포하기란 불가능했으며, 이를 해결하기 위해 제1절연수지층과 제2절연수지층으로 이루어진 2층의 절연수지층을 형성하는 경우에는 공정의 복잡성에 의해 절연수지의 성분이 변하거나 열화를 초래하는 경우가 있었다. 또한, 비어홀을 형성하는 경우에도 직경이 다른 제1비어홀과 제2비어홀을 형성해야만 하기 때문에, 미세구경(약 1mm)의 홀을 형성하기란 대단히 어려운 일이었다.In general, in order to manufacture a high-definition, high-definition multilayer printed circuit board, an insulation resin layer having a thickness of about 50 μm or more and a via hole having a diameter of about 1 mm are required. However, in the method disclosed in the above-described patent (Application No. 1996-25304), since the insulating resin layer is applied to the screen printing method, it is impossible to apply the insulating resin layer having a thickness of about 50 μm or more, and to solve this problem, the first insulation In the case of forming a two-layered insulating resin layer composed of a resin layer and a second insulating resin layer, the components of the insulating resin may change or cause deterioration due to the complexity of the process. In addition, even when the via hole is formed, it is very difficult to form a hole having a fine diameter (about 1 mm) because the first and second via holes having different diameters must be formed.
더욱이, 감광성 절연수지층의 현상시 언더컷(undercut)이 발생하는 경우 비어홀이 2단의 단차를 가지고 형성되기 때문에, 2개의 언더컷이 생기게 되어 상기한 언더컷에서 도금층(130)이 쉽게 단락되는 문제가 있었다.Furthermore, when undercut occurs during development of the photosensitive insulating resin layer, since the via hole is formed with two steps, there are two undercuts, which causes a problem that the plating layer 130 is easily shorted at the undercut. .
본 발명은 상기한 문제를 해결하기 위한 것으로, 동박적층판의 양면에 1회의 커틴코팅방법으로 감광성 절연수지층을 형성하고 현상하여 비어홀을 형성함으로써 제조공정이 간단하고 절연수지층의 열화와 파손을 방지화할 수 있는 다층 인쇄회로기판 제조방법을 제공하는 것을 목적으로 한다.The present invention is to solve the above problems, by forming and developing a photosensitive insulating resin layer on both sides of the copper-clad laminate by a single coating method to form a via hole to simplify the manufacturing process and to prevent degradation and breakage of the insulating resin layer An object of the present invention is to provide a method for manufacturing a multilayer printed circuit board that can be manufactured.
본 발명의 다른 목적은 비어홀을 V자 형상으로 형성하여 절연수지층에 발생하는 언더컷을 최소화함으로써 신뢰성이 향상되고 수율이 향상될 수 있는 다층 인쇄회로기판 제조방법을 제공하는 것이다.Another object of the present invention is to provide a method of manufacturing a multilayer printed circuit board, in which a via hole is formed in a V shape to minimize undercuts generated in the insulating resin layer, thereby improving reliability and improving yield.
상기한 목적을 달성하기 위해, 본 발명에 따른 다층 인쇄회로기판 제조방법은 동박적층판의 양면에 금속을 도금하고 에칭하여 인쇄회로패턴을 형성하는 단계와, 상기한 동박적층판의 양면에 1회의 커틴코팅방법으로 감광성 절연수지층을 도포하고 현상하여 비어홀을 형성하는 단계와, 층간 도통용 스로우홀을 형성한 후 인쇄회로패턴, 감광성 절연수지층 및 스로우홀의 내벽에 Cu도금층을 형성하는 단계와, 상기한 Cu도금층을 에칭하여 인쇄회로 패턴을 형성하는 단계로 구성된다.In order to achieve the above object, a method of manufacturing a multilayer printed circuit board according to the present invention comprises the steps of forming a printed circuit pattern by plating and etching metal on both sides of the copper-clad laminate, and once the coating on both sides of the copper-clad laminate Coating and developing the photosensitive insulating resin layer by a method to form a via hole, forming a through hole for interlayer conduction, and then forming a Cu plating layer on an inner wall of the printed circuit pattern, the photosensitive insulating resin layer and the through hole, and Etching the Cu plating layer to form a printed circuit pattern.
동박적층판의 양면은 감광성 절연수지층과의 접착력 향상을 위해 흑화환원처리 되어 있고 절연수지는 약 50μm의 두게로 적층판 위에 도포되며, 비어홀은 V자 형상으로 현상된다.Both sides of the copper-clad laminate are blackened and reduced to improve adhesion to the photosensitive insulating resin layer, and the insulating resin is applied on the laminated plate at a thickness of about 50 μm, and the via hole is developed in a V shape.
도 1은 종래의 다층 인쇄회로기판의 제조방법을 나타내는 도면.1 is a view showing a manufacturing method of a conventional multilayer printed circuit board.
도 2는 다른 종래 다층 인쇄회로기판의 제조방법을 나타내는 도면.2 is a view showing a manufacturing method of another conventional multilayer printed circuit board.
도 3은 도 2의 방법에 의해 제조된 다층 인쇄회로기판의 구조를 나타내는 도면.3 is a view showing the structure of a multilayer printed circuit board manufactured by the method of FIG.
도 4는 본 발명에 따른 다층 인쇄회로기판 제조방법을 나타내는 도면.4 is a view showing a method for manufacturing a multilayer printed circuit board according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
110 : 동박적층판 112 : 인쇄회로패턴110: copper foil laminated plate 112: printed circuit pattern
114 : 감광성 절연수지층 120 : 포토비어홀114: photosensitive insulating resin layer 120: photo-via hole
130 : Cu도금층 140 : 스로우홀130: Cu plated layer 140: throw hole
이하, 첨부한 도면을 참조하여 본 발명에 따른 다층 인쇄회로기판의 제조방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a multilayer printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 가장 큰 특징은 종래와는 달리 원하는 두께의 감광성 절연수지층을 한 번의 공정에 의해 도포하여 절연수지의 물성변화를 최소화한 상태에서 외층과 내층의 패턴을 접속시키는 V자 형태의 비어홀을 형성하는 것이다.The biggest feature of the present invention is a V-shaped via hole which connects the pattern of the outer layer and the inner layer in a state in which the photosensitive insulating resin layer having a desired thickness is applied by one process unlike the prior art to minimize the change of the physical properties of the insulating resin. To form.
도 4는 본 발명에 따른 다층 인쇄회로기판의 제조방법을 나타내는 도면이다. 도 4(a)에 나타낸 바와 같이, 우선 양면에 동박막이 적층된 동박적층판(110)의 양면에 금속을 도금하고 사진식각(photolithography)방법으로 에칭하여 인쇄회로패턴(112)을 형성한 후, 도 4(b)에 나타낸 바와 같이 감광성 절연수지층(114)을 도포하고 현상하여 V자 형상의 비어홀(120)을 형성한다. 이때, 도면에는 나타내지 않았지만, 상기한 동박적층판(110)은 흑화막이 형성되도록 흑화처리되어 동박적층판(110)과 감광성 절연수지층(114)과의 접착력을 향상시킨다.4 is a view showing a method of manufacturing a multilayer printed circuit board according to the present invention. As shown in FIG. 4 (a), first, metals are plated on both surfaces of the copper-clad laminate 110 having the copper thin films laminated on both sides, and the printed circuit patterns 112 are formed by etching by photolithography. As shown in FIG. 4B, the photosensitive insulating resin layer 114 is coated and developed to form a V-shaped via hole 120. At this time, although not shown in the drawing, the copper foil laminate 110 is blackened to form a blackening film to improve the adhesion between the copper foil laminate 110 and the photosensitive insulating resin layer 114.
절연수지층(114)은 커틴코팅법(curtain coating process)에 의해 약 50μm의 두께로 도포된 후 예비건조과정을 통해 반경화(pre-cure)되며, 마스크가 진공밀착된 상태에서 자외선을 조사하고 현상액을 작용시켜 V자 형태의 포토비어홀(120)이 형성된다. 예비건조은 약 50∼130℃의 온도에서 약 5∼45분 동안 실시되는데, 건조온도가 50℃ 미만이거나 건조시간이 5분 미만일 경우에는 감광성 절연수지내의 용매(부틸 카아비톨(buthyl carbitol) 또는 부틸 셀로솔브(cellosolve))의 절연수지가 도막 표면부에 위치해서 자외선의 전달을 방해하게 되어 노광량 부족현상에 의해 포토비어홀의 형성이 곤란해지고 끈적거림으로 인해 마스크의 표면형태가 전사되거나 늘어 붙음이 발생한다.The insulating resin layer 114 is coated to a thickness of about 50 μm by a curtain coating process, and then semi-cured through a pre-drying process. The developer acts to form the V-shaped photo-via hole 120. Predrying is carried out for about 5 to 45 minutes at a temperature of about 50 to 130 ℃, if the drying temperature is less than 50 ℃ or drying time less than 5 minutes solvent in the photosensitive insulating resin (butyl carbitol or butyl The insulating resin of cellosolve is located on the surface of the coating film, which hinders the transmission of ultraviolet rays, making it difficult to form photo-via holes due to insufficient exposure, and the surface shape of the mask is transferred or stuck due to stickiness. do.
건조온도가 130℃를 초과하거나 건조시간이 45분을 초과하는 경우에는 감광성 절연수지내의 반응라디칼(reaction radical)의 과반응으로 인해 적정 노광량의 조사뒤에도 현상이 어려워 비어홀(120)의 형성이 곤란해 진다.If the drying temperature exceeds 130 ° C. or the drying time exceeds 45 minutes, the development of the via hole 120 is difficult because the development is difficult even after irradiation of the appropriate exposure amount due to the reaction of reaction radicals in the photosensitive insulating resin. Lose.
도 4(b)에서는 동박적층판(110) 양면의 포토비어홀(120)이 도시되어 있지만, 실제의 공정에서는 먼저 동박적층판(110) 상면에 우선 감광성 절연수지층(114)을 도포하고 상기한 공정을 거쳐 포토비어홀을 형성한 후 하면에 다시 수지층(114)을 도포하여 비어홀을 형성한다.Although the photo-via hole 120 of both surfaces of the copper-clad laminate 110 is shown in FIG. 4 (b), first, the photosensitive insulating resin layer 114 is first applied to the upper surface of the copper-clad laminate 110 and the above-described process is performed. After the photo-via hole is formed, the resin layer 114 is applied to the lower surface to form the via hole.
이후, 도 4(c)에 나타낸 바와 같이, 층간 도통용 스로우홀(through hole;140)을 드릴(drill)로 가공한 후 인쇄회로패턴(112), 감광성 절연수지층(114) 및 스로우홀(140)의 내벽에 Cu도금층(130)을 형성한다. Cu도금층(130)은 감광성 수지절연층(114)과 포토비어홀(120)에 요철을 부여하여 도금밀착성을 향상시키고 스로우홀(140) 내벽의 스미어(smear)를 제거한 후 ,스로우홀(140) 내벽에 도전성을 부여하기 위해 무전해 Cu도금을 실시하고, 이어서 약 15μm 두께의 전해 Cu도금을 실시함으로써 형성된다.Thereafter, as illustrated in FIG. 4C, after the through hole 140 is formed with a drill, the printed circuit pattern 112, the photosensitive insulating resin layer 114, and the through hole ( The Cu plating layer 130 is formed on the inner wall of the 140. The Cu plating layer 130 is provided with irregularities in the photosensitive resin insulating layer 114 and the photo via hole 120 to improve plating adhesion and remove smear of the inner wall of the through hole 140, and then, the inner wall of the through hole 140. It is formed by electroless Cu plating to impart conductivity to the electroless Cu plating, followed by electrolytic Cu plating having a thickness of about 15 μm.
그 후, 도 4(d)에 나타낸 바와 같이, 상기한 Cu도금층(130)을 사진식각방법으로 에칭하여 인쇄회로 패턴(131)을 형성한다.Thereafter, as shown in FIG. 4 (d), the Cu plating layer 130 is etched by a photolithography method to form a printed circuit pattern 131.
상기한 바와 같이, 본 발명에 따른 다층 인쇄회로기판 제조방법은 약 50μm의 감광성 절연수지층을 커틴코팅방법에 의해 도포한 후 V자 형상의 비어홀을 형성하기 때문에 공정이 간단해진다. 따라서, 2회의 공정에 동박적층판 한면의 절연수지층을 도포하는 종래의 방법에서 발생하는 절연수지층의 열화 및 파손을 방지할 수 있게 된다. 또한, 1회의 노광 및 현상에 의해 V자 형상의 포토비어홀을 형성하기 때문에, 절연수지층의 언더컷 현상이 최소화되어 다층 인쇄회로기판의 수율이 대폭 향상된다.As described above, the method for manufacturing a multilayer printed circuit board according to the present invention is simplified because the V-shaped via hole is formed after applying a photosensitive insulating resin layer having a thickness of about 50 μm by a curtin coating method. Therefore, it is possible to prevent deterioration and breakage of the insulating resin layer generated in the conventional method of applying the insulating resin layer on one side of the copper foil laminated plate in two steps. In addition, since the V-shaped photo-via hole is formed by one exposure and development, the undercut phenomenon of the insulating resin layer is minimized, and the yield of the multilayer printed circuit board is greatly improved.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970066639A KR100276262B1 (en) | 1997-12-08 | 1997-12-08 | A method of fabricating a multi-layer printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970066639A KR100276262B1 (en) | 1997-12-08 | 1997-12-08 | A method of fabricating a multi-layer printed circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19990048038A true KR19990048038A (en) | 1999-07-05 |
KR100276262B1 KR100276262B1 (en) | 2001-04-02 |
Family
ID=40749733
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970066639A KR100276262B1 (en) | 1997-12-08 | 1997-12-08 | A method of fabricating a multi-layer printed circuit board |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100276262B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100728764B1 (en) * | 2005-11-10 | 2007-06-19 | 주식회사 토픽 | Manufacturing method for Multi-layer PrintedCircuit Board |
KR100909310B1 (en) * | 2007-11-13 | 2009-07-24 | 주식회사 두산 | Manufacturing Method of Circuit Board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100998151B1 (en) * | 2008-04-10 | 2010-12-03 | 주식회사 디에스엘시디 | ??? module and method for manufacturing thereof |
-
1997
- 1997-12-08 KR KR1019970066639A patent/KR100276262B1/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100728764B1 (en) * | 2005-11-10 | 2007-06-19 | 주식회사 토픽 | Manufacturing method for Multi-layer PrintedCircuit Board |
KR100909310B1 (en) * | 2007-11-13 | 2009-07-24 | 주식회사 두산 | Manufacturing Method of Circuit Board |
Also Published As
Publication number | Publication date |
---|---|
KR100276262B1 (en) | 2001-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2837137B2 (en) | Method of manufacturing build-up multilayer printed circuit board | |
US4211603A (en) | Multilayer circuit board construction and method | |
KR100222752B1 (en) | Fabrication method of laminate pcb using laser | |
KR100327705B1 (en) | Method of producing a multi-layer printed-circuit board | |
US6638690B1 (en) | Method for producing multi-layer circuits | |
KR100897650B1 (en) | Fabricating Method of Multi Layer Printed Circuit Board | |
KR100276262B1 (en) | A method of fabricating a multi-layer printed circuit board | |
KR100455892B1 (en) | Build-up printed circuit board and manufacturing method thereof | |
KR20030016515A (en) | method for producing build-up multi-layer printed circuit board using a via filling | |
KR100869049B1 (en) | Semi-additive pcb manufacturing method with employing uv sensitive polyimide lamination | |
JP2699920B2 (en) | Method for manufacturing multilayer printed wiring board | |
JPH06260763A (en) | Manufacture of multilayer wiring board | |
US6274291B1 (en) | Method of reducing defects in I/C card and resulting card | |
JP2003115662A (en) | Method of manufacturing semiconductor device substrate | |
KR100213378B1 (en) | Fabricating method of build-up multi-layer circuit board | |
KR20100055801A (en) | Manufacturing method of pcb | |
JPH036880A (en) | Printed wiring board and manufacture thereof | |
JP2004152935A (en) | Printed wiring board | |
JP2984625B2 (en) | Multilayer printed wiring board manufacturing method | |
KR100222753B1 (en) | Fabrication method of laminate pcb elevation isolation | |
JPH077264A (en) | Manufacture of printed wiring board | |
KR19990048049A (en) | Manufacturing method of build-up multilayer printed circuit board | |
JP2954169B1 (en) | Manufacturing method of printed wiring board | |
JP2000294928A (en) | Via hole forming method | |
JPH05267848A (en) | Manufacture of printed circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20080701 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |