KR19990024450A - Data decoding device for digital video disk-ROM - Google Patents

Abstract

The present invention relates to a data decoding device for a digital video disk (DVD) -ROM that removes unnecessary memory. In particular, the DVD-ROM is PI-corrected by 182 bytes in the horizontal direction for the first block while removing unnecessary memory for VBR and DSI. Are stored in order, and when the PI correction of one block is completed, PO correction in 208 byte units (1 frame) is made in the vertical direction, rewritten, and then outputted to ATAPI. Save the corrected data, read the data in 208 byte units in the horizontal direction when PI correction of the next block is completed, perform PO correction, rewrite it, output it to ATAPI, and then return to the place where the frame is exited. The process of storing PI corrected data of a block is repeated for each block sequentially to By simultaneously performing PO error correction and output and PI error correction of the next block, the size of the ECC memory can be reduced to a size smaller than 2 blocks (for example, 208 x 208 bytes), and the memory can be built-in. It can also be used to speed up data transfer to a PC.

Description

Data decoding device for digital video disk-ROM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video disc (DVD) system, and more particularly, to a data decoding apparatus for DVD-ROM, which enables one-chip by removing unnecessary memory.

Recently, a system has been developed for recording and playing back moving images on or from a high density optical disk after compressing the image using a high efficiency coding technique, one of which is a DVD system.

The DVD system uses a variable bit rate (VBR) coding technique in which the amount of code generated in response to complex image information is changed, and a system similar to a moving picture expert group 2 (MPEG 2) for ensuring a high quality image. Doing.

Examples of the DVD include DVD-P (DVD-Player; playback only), DVD-ROM; Playback only), DVD-R (DVD-Recordable; recording only once), DVD-RAM (playing / recording multiple times), and the like.

The error correction in such a DVD system is in a Reed-Solomon error correction format. Usually, 37856 bytes of data are performed in units of 182 bytes horizontally and 208 bytes vertically. This horizontal correction is called PI (Parity Inner) error correction and vertical correction is called PO (Parity Outer) error correction.

Conventionally, in order to decode data of a DVD-ROM mounted in a personal computer (PC), the DVD-RAM chip as shown in FIG. 1 is applied to a DVD-ROM as it is.

FIG. 1 includes a dynamic random access memory (DRAM) 15 having a storage capacity of 256K × 16 bits for error correction, VBR control, and Data Search Information (DSI). The memory controller 12 controls the data arrangement of the DRAM 15 and performs error correction by inputting / outputting data in units of frames to the error code correction (ECC) unit 14. At this time, in order to make the PI error correction and the PO error correction into a cyclic structure, control is performed with a static random access memory (SRAM) 13 for two frames.

Here, as shown in FIG. 2, the DRAMs 15 are arranged such that E1 and E2 circulate with each other for error correction in an area corresponding to one block. In other words, if PI error correction is performed for E1, PO error correction is performed for E2. If PI error correction is performed for E2, PO error correction is performed for E1. The area from B1 to B12 is an area circulating for VBR control. Also, the DSI area is an area for storing DSI data.

In FIG. 1 configured as described above, data demodulated by the demodulator 11 is output to the SRAM 13 and the ECC unit 14 through the memory controller 12 in PI error correction frame units (here, 182 bytes).

The ECC unit 14 performs PI error correction to obtain an error value and an error position and outputs the result to the memory control unit 12. The memory control unit 12 stores the original data and the ECC unit 14 stored in the SRAM 13. The error correction is performed using the error value and the error position output from the (), and then stored in the DRAM 15. When the PI-corrected data is stored in the DRAM 15, the memory controller 12 reads the PI-corrected data from the DRAM 15 again in PO error correction frame units (208 bytes in this example), and the SRAM 13 and ECC units ( 14)

The ECC unit 14 performs PO error correction to obtain an error value and an error position and outputs the result to the memory control unit 12. The memory control unit 12 stores the original data and the ECC unit 14 stored in the SRAM 13. The error correction is performed using the error value and the error position output from the (), and then stored in the DRAM 15.

When the PO-corrected data is stored in the DRAM 15, the memory controller 12 reads the PO-corrected data from the DRAM 15, selects MPEG data, system data, and DSI data, and stores the system in a system buffer (not shown). The data is drawn, and the interface control unit 16 outputs MPEG data and DSI data. The interface control unit 16 controls data transmission to MPEG. In block data of 16 sectors, data not required by MPEG is discarded, and the remaining data is transmitted to a track buffer (not shown).

At this time, the data processor for the DVD-ROM performs VBR processing in software by a program in a PC, thereby eliminating the need for VBR control and DSI processing. Therefore, the area circulating for VBR control from B1 to B12 in the DRAM 15 and the DSI area for storing DSI data are unnecessary.

However, since the DRAM 15 for DVD-RAM is conventionally used for the DVD-ROM, the storage capacity of the DRAM is unnecessarily increased by the VBR area and the DSI area that are not necessary. If the memory size increases, it cannot be embedded in the decoding chip and must be externally mounted in the form of external memory. This makes one-chipization impossible. In addition, since the error-corrected data is transmitted to the PC through the E1 and E2 regions of the DRAM 15 and the VBR buffer, the data access time is delayed when viewed from the PC.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a data decoding apparatus for a DVD-ROM which reduces a memory size by eliminating unnecessary VBR and DSI regions in a DVD-ROM.

Another object of the present invention is to provide a data decoding apparatus for DVD-ROM which reduces the size of the ECC memory by changing the storage direction of PI corrected and PO corrected data for each block.

A feature of the data decoding apparatus for DVD-ROM according to the present invention for achieving the above object is a demodulation unit for demodulating the input data, and to store the PI-corrected data and PO-corrected data by changing the storage direction for each block A memory control unit that controls memory, error correction, and storage of PI correction data and PO correction data in the memory; and, when PO correction is controlled by the memory control unit, data is read from the memory in PO error correction frame units, and PI correction is performed. The error correction unit reads demodulated data in PI error correction frame units to perform PO correction of the current block and PI correction of the next block, and PO error correction is performed in PO error correction frame units and stored in the memory. Interface to read data of the frame from memory through memory controller and output to host It consists of including wealth.

1 is a block diagram of a conventional data decoding device for a digital video disk (DVD) -ROM

FIG. 2 is a diagram illustrating an example of division of use for the DRAM of FIG. 1.

3 is a block diagram of a data decoding apparatus for DVD-ROM according to the present invention;

4 is a view illustrating a process of storing PI-PO corrected data in the memory of FIG.

5 is a flowchart for a data decoding apparatus for DVD-ROM according to the present invention.

Explanation of symbols for the main parts of the drawings

31: demodulation unit 32: memory control unit

33: memory 34: SRAM

35: ECC unit 36: interface unit

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a data decoding apparatus for DVD-ROM according to the present invention, wherein the demodulation unit 31 for demodulating input data, the ECC for storing the PI-corrected data, and the PO-corrected data are changed for each block. The memory 33, the memory control unit 32 for controlling error correction and data storage and reading into the memory 33, and the SRAM 34 for two frames for performing PI error correction and PO error correction in a cyclic manner. And an ECC unit 35 for simultaneously performing PO error correction of the current block and PI error correction of the next block, and an interface unit 36 for transmitting PI-completed and PO-corrected data to the PC. .

The memory 33 is an ECC dedicated memory, and a storage capacity of 208 x 208 bytes is sufficient. This is a size slightly over one block. The memory 33 simultaneously stores and outputs PO-corrected data of one frame and PI-corrected data. When storing PI error corrected data, the PI parity is not stored under the control of the memory controller 32. That is, the PI parity is used for PI error correction. When PI error correction is performed, the PI parity is no longer needed, thereby reducing the size of the memory 33 by PI parity.

In addition, the interface unit 36 generally uses an advanced technology attached packet interface (ATAPI) for interfacing the DVD-ROM data decoding apparatus with a PC. In other words, ATAPI is an interface standard between a CD or DVD drive and a PC. It is a newly proposed standard for transferring decoded data from a drive to a host of a PC, and converts the decoded data into a packet type protocol that is data that can be processed by a PC. It serves to transmit.

The present invention configured as described above will be described in detail with reference to the flowchart of FIG. 5. That is, when data is read from the DVD-ROM, the DVD is demodulated by the demodulator 31 and then output to the memory controller 32 (step 501).

The memory control unit 32 is output to the SRAM 34 and the ECC unit 35 for two frames in PI error correction frame units (here, 182 bytes).

The ECC unit 35 performs PI error correction to obtain an error value and an error position and outputs the result to the memory control unit 32. The memory control unit 32 stores the original data and the ECC unit 35 stored in the SRAM 34. After error correction is performed using the error value and the error position outputted at (step 502), it is stored in the memory 33. At this time, the PI-corrected data is first stored sequentially in the horizontal direction as shown in a of FIG. 4 in units of 182 bytes (step 503). Here, the PI parity is not stored in the memory 33 under the control of the memory control unit 32. When 208 frames of PI correction are processed by 182 bytes, PI error correction of the first block E1 is completed. At this point, PO error correction is performed in the vertical direction as shown in FIG. 4A (step 504).

That is, in order to perform PO error correction, the memory control unit 32 reads the data stored in the memory 33 after the PI error correction in the PO error correction frame unit (here 208 bytes) in the vertical direction, and then the SRAM 34. And to the ECC unit 35.

The ECC unit 35 performs PO error correction to obtain an error value and an error position, and outputs the result to the memory control unit 32. The memory control unit 32 stores the original data and the ECC unit 35 stored in the SRAM 34. The error correction is performed using the error value and the error position output from the multiplier), and then rewritten to the memory 33 (step 505).

At this time, the data of the PO error corrected frame is hatched as shown in b of FIG. 4, and since the PI-PO is all completed data, it is no longer necessary to have it in the memory 33. Therefore, the memory controller 32 outputs 208 bytes of data (ie, hatched areas in FIG. 4B) stored in the memory 33 to the interface unit 36 (step 506), and the frame is output. At the exit, the PI error correction data of the new block E2 processed therebetween is written as shown in c of FIG. 4 (step 507). Therefore, the PI corrected data is sequentially stored in units of 182 bytes in the vertical direction as opposed to the previous block. That is, the ECC unit 35 must simultaneously perform PO correction of the current block and PI correction of the next block.

In this way, the PO error correction of one frame and the output of the interface unit 36 and the PI error correction of the next block are simultaneously performed. When the PO error correction ends 182 frames of 208 bytes, the first block (c) of FIG. All PI-PO error corrections for E1) are completed and the PI error correction of the next block (E2) is almost finished. Therefore, when the PO error correction of one block E1 is completed, the PI error correction of the next block E2 is completed, and ECC processing is possible only by the memory 33 of a size slightly larger than one block size.

In addition, since PI-corrected data of the new block E2 is stored in the memory 33 in the vertical direction as shown in d of FIG. 4, in order to perform PO error correction of the new block E2, horizontally as shown in d of FIG. 4. The data must be read in the direction. That is, the memory control unit 32 reads the data stored in the memory 33 in units of 208 bytes in the horizontal direction for PO correction, and outputs the data to the SRAM 34 and the ECC unit 35 (step 508). The ECC unit 35 performs PO error correction to obtain an error value and an error position, and outputs the result to the memory control unit 32. The memory control unit 32 stores the original data and the ECC unit 35 stored in the SRAM 34. Error correction is performed using the error value and the error position output from the multi-stage controller, rewritten to the memory 33 again (step 509), and immediately read and output to the interface unit 36 as shown in FIG. 510).

In addition, the PI error corrected data of the new block E3 is stored as shown in f of FIG. 4 at the position where the PO-corrected data frame exits. After PI error correction is completed, read the data in the vertical direction and perform PO error correction.

At this time, since the block returns to the original storage direction after the PI-PO correction of two blocks is performed, if the block number read in step 511 is increased by two (n = n + 2), error correction is not completed. (Step 512), the flow returns to step 502 to perform PI-PO error correction on the next block as described above.

As described above, PI and PO corrections are performed by changing the direction of writing and reading data into the memory 33 in units of blocks, thereby enabling ECC to be performed even with a small memory size.

On the other hand, the data arrangement when the PI-PO error correction data is output to the interface unit 36 is different from the original data order input to the ECC memory 33, it is necessary to rearrange the process. . In this case, since there is a buffer having about 16 blocks of memory in the ATAPI device itself of the interface unit 36, the data array can be easily readjusted without additional memory.

That is, the order of data initially stored in the memory 33 is sequentially stored in a horizontal column as follows. Then, after PI error correction is performed on 208 frames of 182 bytes, which are PI units, the PO error correction is again corrected by error correction by 208 bytes, followed by one frame consisting of 208 bytes 0 182 364 ... 37674, followed by 1 183 365 ... 37675 The next frame sequence is output to the interface unit 36 differently from the input sequence, so the interface unit 36 rearranges the sequence in the original serial order before transmitting to the host. . For example, when the PI-PO corrected data is stored in the memory, the storage direction is changed every block so that the PI-PO corrected data array output from the memory is readjusted in the original serial order.

0 1 2 3 4 5 6 ... 181

182 183 184 185 186 187 188 ... 363

364 365 366 367 368 369 370 ... 545

. .

. .

. .

37674 37675 ..... 37855

As described above, according to the data decoding apparatus for DVD-ROM according to the present invention, the unnecessary VBR and DSI memory are removed from the DVD-ROM, and the PI block is sequentially stored in the horizontal direction for 182 bytes for the first block. After the PI correction of one block is completed, PO correction is performed in 208 byte units (1 frame) in the vertical direction, and then outputted to the ATAPI. When the PI correction of the next block is completed, the data is read in 208 byte units in the horizontal direction, PO correction is performed, and then output to ATAPI. The process of storing data horizontally is repeated for all blocks in order to reduce the PO corrected data of one frame. By simultaneously storing the chapter and output and the PI-corrected data of the next block, the size of the ECC memory can be reduced to a size smaller than 2 blocks (for example, 208 x 208 bytes), and the memory can be built-in. It can be chipped and increases the data transfer speed to the PC.

In addition, since the PI parity is not stored after PI error correction, the size of the memory can be further reduced.

Claims (9)

In the data decoding device for digital video disk-ROM which demodulates input data and performs horizontal axis (PI) correction and vertical axis (PO) correction, and outputs them to a host. A memory for storing PI-corrected data and PO-corrected data by changing the storage direction for each block; A memory controller for controlling error correction and storage of PI correction data and PO data in the memory; Under the control of the memory controller, when PO is corrected, data is read from the memory in units of PO error correction frames, and when PI is corrected, data demodulated in units of PI error correction frames is read to perform PO corrections in the current block and PI corrections in the next block. Error correction means to be performed at the same time, When PO error correction is performed in the unit of PO error correction frame and stored in the memory, the data decoding for the digital video disk-ROM comprises an interface unit which reads the data of the frame from the memory through the memory controller and outputs it to the host. Device. The method of claim 1, wherein the memory is PO error correction frame unit x The size of the data decoding device for a digital video disk-ROM characterized in that the size smaller than the PO error correction frame unit. 3. The apparatus of claim 2, wherein the memory does not store PI parity under the control of a memory controller after PI correction. The method of claim 1, wherein the memory is And when the PO corrected data of one frame is output to the interface unit, PI correction data of the next block is stored in place of the frame. The method of claim 1, wherein the memory is Under the control of the memory controller, the PI corrected data is sequentially stored in the PI direction in the first direction with respect to the PI block in the first direction, and when the PI correction data of one block is completed, the PO error correction frame in the second direction is completed. After storing the PO-corrected data in units and outputting the stored PO-correction data to the interface unit, the PI-corrected data of the second block is stored after storing the PI-corrected data of the second block in the second direction. Upon completion, the PO-corrected data is stored in the PO error correction frame unit for the first direction, and the PI-corrected data of the third block is stored in the first direction where the frame is exited by outputting the stored PO correction data to the interface unit. Digital video disk-ROM data, characterized in that to repeat the process of saving all the blocks sequentially The coding apparatus. 6. The data decoding apparatus of claim 5, wherein the second direction is a longitudinal direction when the first direction is a horizontal direction, and the second direction is a horizontal direction when the first direction is a vertical direction. The method of claim 1, wherein the memory control unit For controlling the memory and the error correction means such that the storage of PO error corrected data of one frame and the output to the interface unit and the PI error corrected data of the next block are simultaneously performed. Data decoding device. The method of claim 1, wherein the interface unit PI-PO Data decoding apparatus for digital video disk-rom, which uses ATAPI which converts error-corrected data into a packet type protocol and transmits it to a host. The method of claim 1, wherein the interface unit And a rearrangement of the PI-PO corrected data output from the memory through the memory control unit in an original serial order to the host by using an internal buffer.