KR19990012155A - Nonvolatile Memory Device and Manufacturing Method Thereof - Google Patents

Abstract

A NAND type nonvolatile memory device and a method of manufacturing the same are disclosed. The nonvolatile memory device is a source / drain region of a first conductivity type of n memory cell transistors, repeated in a second direction orthogonal to the first direction while being spaced apart by a field region on the semiconductor substrate and extending in a first direction. And a memory cell array formed of an array of n word lines repeated in the first direction while extending in the second direction on top of the formed cell active pattern. A string select transistor and a ground select transistor are formed outside the first and nth memory cell transistors, respectively. In order to apply a voltage to the substrate of the memory cell array, a substrate junction hole is formed in an active pattern of an independent second conductivity type surrounded by a field region. At least one ground select transistor is disposed bypassing the substrate junction hole so that the substrate junction hole is disposed between the nth word line and the ground select transistor in the first direction and between the ground select transistors in the second direction. do. By simply arranging the well contacts in a longer longitudinal structure along the Y axis without adding a separate process, the contact area with the substrate can be increased to reduce the substrate connection resistance.

Description

Nonvolatile Memory Device and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile memory device that can easily form a substrate contact hole without adding a separate process. A memory device and a method of manufacturing the same.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products that have slow data input / output. Among these ROM products, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory that can electrically input / output data. Flash memory devices are an advanced form of EEPROM that can be electrically erased at high speed without removing them from the circuit board.The memory cell structure is simple, so the manufacturing cost per unit memory is low and the data is refreshed to preserve data. The advantage is that functionality is unnecessary, but the input / output speed of the data is hundreds of milliseconds to several milliseconds, which is significantly slower than tens of ns of RAM products.

Looking at the flash memory device from a circuit point of view, each memory cell can be controlled independently, so that the operation speed is high, but one contact is required per two cells, which increases the cell area. It can be controlled and classified into NAND type, which is advantageous for high integration.

In the NAND type flash memory device, a cell transistor operated by an external peripheral circuit has a structure in which a floating first gate and a second gate for controlling the first gate are stacked. Representative NAND type flash memory devices include a new ultra-integrated EPROM and flash EEPROM having a NAND cell structure, published by Masuoka et al. This is well illustrated in the EEPROM having the NAND cell structure disclosed in US Pat. No. 5,050,125.

FIG. 1 is a schematic diagram illustrating a memory cell array of a typical NAND type flash memory device, showing a memory cell array, a page buffer unit, and a decoder unit.

Referring to FIG. 1, a NAND type memory cell array is referred to as a 512 byte (ie, 4096 bit) word line direction (X-axis direction in FIG. 1) memory cell (hereinafter, referred to as a page unit) for data compatibility with a general memory product. ) Are divided into eight input / outputs (I / O; I / O ₀ ..., I / O ₇ ) so that each I / O has a 512-bit bit line (B / L ₁ ,…). Have

On the other hand, in a NAND type memory cell array, one bit line contact hole shares 2n memory cells in the bit line direction (Y-axis direction in FIG. 1) (where n is usually 8 or 16). Memory called string (string) is formed in series connection as a _{channel; (W / L 1, ...} word line), and a selection transistor to the both ends of each of the n memory cell transistors are the word lines that are orthogonal to the bit line Make up the unit. In addition, the memory cells of the page unit connected to the same string are called blocks.

Hereinafter, program or write, erase, and read operations of the NAND type flash memory device will be described in detail with reference to FIG. 2. For convenience, the operations will be described using a Fowler-Nordheim tunneling method.

2 is a cross-sectional view of a memory cell transistor cut in a channel direction in a typical NAND type flash memory device. Where reference numeral 1 is a P-type substrate (or P-type well), 90 is a tunnel oxide, 30 is a floating gate, 35 is an interlayer dielectric, 40 is a control gate, and 80 Represents N ⁺ source / drain regions, respectively. Reference numeral E denotes an erased cell, and P denotes a programmed cell.

First, a write operation is performed by injecting a part of electrons into the floating gate 30 through the tunnel oxide film 90 by F-N tunneling. That is, about 60% of the voltage applied to the control gate 40 is transferred to the floating gate 30 by charge capacitive coupling, and the thin tunnel oxide film 90 existing between the floating gate 30 and the substrate 1 is present. Potential difference is induced through). When the induced potential difference satisfies the F-N tunneling condition, electrons are injected from the substrate 1 into the floating gate 30. To this end, 0V is applied to the substrate 1 while applying a high voltage of 20V or more to the control gate 40.

The erase operation is an operation of discharging electrons injected into the floating gate 30 toward the substrate 1. The erase operation is performed by applying a high voltage to the substrate 1 and applying an OV to the control gate 40 as opposed to the write operation.

In the NAND type flash memory device, since data write and read operations are performed sequentially, it is impossible to write data to any memory cell such as DRAM. Therefore, in order to perform the write operation, the erase operation must be performed first.

On the other hand, the ability of preserving stored data, which is one of the characteristics of the flash memory device, depends on the reliability of the tunnel oxide film 90, and thus it is a limiting factor in the number of times of repeating write and erase operations. In general, to use as a memory product, it is necessary to repeat the erase and write operations of 100,000 to 1 million times. Therefore, although the erase operation may erase the entire memory cell at a time, it not only consumes a lot of time, but also unnecessary memory cells perform the erase operation to deteriorate the tunnel oxide layer 90. It became. Also, in order to apply a uniform voltage to the substrate 1 within a short time even when erasing all memory cells, a plurality of substrate connection holes are provided in the memory cell array as a medium for applying a voltage to the substrate 1. Is placed.

FIG. 3 is a plan view showing a portion of a memory cell array of a NAND type flash memory device according to a conventional method, corresponding to region A of FIG. 1, and is centered on a substrate connection hole (hereinafter, referred to as a well contact). . 4 is an enlarged plan view of the well contact region.

2 to 4, in the NAND type flash memory device, the cell active patterns 10, 11, 12, 13, 14, and 15 in which the channel and the source / drain of the memory cell transistor are to be formed are respectively formed in the field region 20. It extends in the Y axis in parallel with 21, 23, 24, and is repeated while being separated into the field region 22 by being connected to each other by a common source 17 within each input / output (I / O). . On the cell active patterns 10, 11, 12, 13, 14, and 15, the word lines W are spaced at a predetermined distance orthogonal to the cell active patterns and the field regions 20, 21, 22, 23, and 24. / L ₁ , W / L ₂ ,..., W / L _n are stretched and arranged on the X-axis, thereby stacking a memory cell transistor having a stacked gate structure including a floating gate 30 and a control gate 40. Form. A high concentration of N-type source / drain regions 80 is formed on the surface of the exposed substrate 1 between the word lines W / L ₁ , W / L ₂ ,..., W / L _n spaced as described above. do.

In the arrangement of the cell active patterns 10, 11, 12, 13, 14 and 15 extending along the Y axis and the word lines W / L ₁ , W / L ₂ , ..., W / L _n extending along the X axis. By forming a memory cell array having a predetermined degree of integration arranged in the XY direction, a string select line (i.e., a select transistor outside the first word line W / L ₁ and n-th word line W / L _n ), respectively. A string select line (SSL) and a ground select line (GSL) are provided to form a string as one memory unit.

One bit line connection hole (hereinafter referred to as a bit line contact) 50 is provided between the string select transistors SSL adjacent to each other, and the two strings have one bit line contact in the form of a mirror image. Share 50). The cell active patterns 10, 11, and 14 are orthogonal to the word lines through an insulating layer (not shown) on the word lines W / L ₁ , W / L ₂ ,..., W / L _n . The metal wires 60 arranged while extending in the Y axis parallel to the cell active pattern at the upper portion of the line 15 are the bit lines B / L _k-1 , B / L _k , B / L ₁ , B / L ₂ , ...). The bit lines B / L _k-1 , B / L _k , B / L ₁ , B / L ₂ ,... Are formed on the cell active patterns 10, 11, 14, and 15 through bit line contacts 50. Connected with.

Another outer side of the string is provided with an active region 17 for the common source between adjacent ground select transistors GSL and source connection holes (hereinafter referred to as source contacts) for each of the plurality of bit lines. ), A cell active pattern and an active region 17 for the common source are connected to each other through the source contact 54. The select transistors SSL and GSL are strapping for connecting the floating gate 30 and the control gate 40 to the field region 22 between each I / O in order to prevent signal delay caused by resistance. Butting connection holes (hereinafter referred to as butting contacts) 51, 52, 53 and 56. In addition, a well contact 55 ′ for bonding the substrate is formed on the active region 16 ′ surrounded by the field region 22, and the metal wiring layer 62 ′ is active through the well contact 55 ′. It is connected to the area 16 '.

In order to highly integrate the memory device, it is necessary to minimize the size of the memory cell transistors, especially the line width and the separation distance of the word lines W / L ₁ , W / L ₂ ,..., W / L _n , which are channel lengths. Thus, the well contact 55 'must be disposed between the select transistor 45' and the select transistor 46 'in order to be provided in the memory cell array. At this time, the distance X ₁ from the well contact 55 'to the active region 16' for the well contact, between the well contact 55 'and the ground select transistor (GSL) 45', 46 '. Since the distance L ₁ must satisfy the design rule, the well contact 55 'must be disposed to the minimum size in order to reduce the distance Y ₁ between the two selection transistors 45' and 46 '. As a result, a problem arises in that the substrate connection resistance of the well contact 55 'becomes large.

In addition, since the well contact 55 'has a thick field oxide film 22 and a ground select transistor (GSL) 45', 46 'disposed around it, the step is severe and an opening indicating a process difficulty of the metal wiring layer deposition process. The aspect ratio becomes large. As a result, board connection is not easy.

5A through 5D are cross-sectional views illustrating a well contact forming method of a NAND type flash memory device according to a conventional method, taken along line AA ′ of FIG. 4.

Referring to FIG. 5A, a P-type well 150 used as a substrate region of a memory cell array is formed to a predetermined depth in a semiconductor substrate 100 through a conventional photolithography process, an ion implantation process, and a diffusion process. Subsequently, an ordinary device isolation process is performed to form field oxide films 22 and 250 having a thickness of 4500 to 6000 GPa for dividing the substrate 100 including the P-type well 150 into an active region and a field region. After forming the first gate oxide film 200 on the resultant, the first conductive layer used as a floating gate of the memory cell transistor by depositing polycrystalline silicon doped with a high concentration of N-type impurities to a thickness of 1000 ~ 1500∼ Form 300. Subsequently, an oxide film or a composite film of an oxide film and a nitride film is grown on the first conductive layer 300 to form an interlayer dielectric film 350, and then the polycrystalline silicon doped with a high concentration N-type impurity thereon is 1000 to 1500 두께 thick. Deposition to form a second conductive layer 400 used as a control gate of the memory cell transistor. Subsequently, the second conductive layer 400 and the interlayer dielectric layer 350 are formed using the first photoresist layer pattern PR 410 to form the word line 40 and the selection transistors GSL 45 'and 46'. ) And the first conductive layer 300 are anisotropically etched. Here, Y ₁ represents the distance between two ground select transistors (GSL) 45 'and 46'.

Referring to FIG. 5B, after removing the first photoresist layer pattern 410, an oxide layer is deposited on the resultant to form a lightly doped drain (LDD) transistor. By etching back, the insulating film spacers 450 are formed on sidewalls of the gate electrodes 300 and 400. Subsequently, a high concentration of N-type impurities are ion implanted using the insulating film spacer 450 to form an N ⁺ -type impurity region (not shown).

Next, a second photoresist layer pattern 510 for exposing only the well contact region is formed by a conventional photolithography process, and the P-type impurity 500 is implanted into the exposed well contact region using the photoresist as an ion implantation mask. The ion implantation conditions of the P-type impurity 500 are performed in the same manner as in the normal P ⁺ source / drain ion implantation.

Referring to FIG. 5C, after removing the second photoresist layer pattern 510, boron and phosphorous may be used to planarize the surface of the substrate while insulating the metal wiring layer to be formed in a subsequent process and the gate electrodes 300 and 400. ) Forms a properly blended borophosphosilicate glass (BPSG) 550. Subsequently, heat treatment is performed at a temperature of 800 to 900 ° C. to planarize the BPSG film 550, and then a third photosensitive film pattern 560 for forming a well contact thereon is formed by a normal photographic process. Next, the well contact 55 ′ is formed by etching the BPSG layer 550 using wet etching and dry etching using the third photoresist pattern 560 as an etching mask. In FIG. 5C, a cross-section of the well contact 55 ′ is indicated by a dotted line, and the well contact 55 ′ is formed with a metal wiring layer to be formed in a subsequent process by using a wet etching process and a dry etching process as described above. The step and the slope are formed gently so as to be easily connected. That is, the wet etching process is performed to easily form the metal wiring layer by reducing the opening aspect ratio of the well contact. The opening aspect ratio is a measure of the difficulty of the metal wiring layer deposition process, and means the ratio of the vertical step C _Y to the size C _X of the connection hole. Therefore, the smaller the opening aspect ratio, the easier the deposition process of the metal wiring layer. In FIG. 5C, L ₁ represents a minimum separation distance between the well contact 55 'and the gate electrodes 300 and 400. Since L ₁ must satisfy a design rule, the well contact 55' is disposed to a minimum size. As a result, the opening aspect ratio becomes large and a problem arises in that the substrate connection resistance increases.

Referring to FIG. 5D, after removing the third photoresist pattern 560, metal wiring layers 62 ′ and 600 may be deposited by depositing a metal such as aluminum (Al). Subsequently, after the fourth photoresist pattern 610 is formed by a general photo process, the metal wiring layers 62 ′ and 600 are patterned using the fourth photoresist pattern 610. At this time, since the opening aspect ratio of the well contact 55 'is large, it is difficult for the metal wiring layers 62' and 600 to be connected to the well contact 55 '.

FIG. 6 is a cross-sectional view illustrating a well contact forming method of a NAND type flash memory device according to another conventional method along the line AA ′ of FIG. 4, and illustrates a method for reducing the opening aspect ratio of a well contact.

Referring to FIG. 6, the processes of FIGS. 5A through 5C are performed in the same manner until the third photoresist pattern 560 for forming the well contact 55 ′ is formed, and the third photoresist pattern 560 is performed. ) Is used as an etching mask to form the well contact 55 ′ by wet etching and dry etching the BPSG film 550. At this time, by increasing the wet etching amount of the BPSG film 550, the aperture aspect ratio of the well contact 55 'is lowered.

Subsequently, after the third photoresist layer pattern 560 is removed, aluminum (Al) is deposited to deposit metal wiring layers 62 ′ and 600. Subsequently, after the fourth photoresist pattern 610 is formed by a general photo process, the metal wiring layers 62 ′ and 600 are patterned using the fourth photoresist pattern 610. However, when the wet etching amount of the BPSG film 550 becomes excessive in the well contact 55 'forming process, the metallization layers 62' and 600 and the ground select transistor (GSL) 45 'or 46' are formed. The problem of shorting arises.

7A and 7B are cross-sectional views illustrating a well contact forming method of a NAND type flash memory device according to another conventional method according to the AA ′ line of FIG. 4, and the multilayer wiring method for preventing the above short problem. To illustrate.

Referring to FIG. 7A, the processes of FIGS. 5A to 5C are performed in the same manner to planarize the BPSG film 550, and then the BPSG film 550 is formed by a photolithography process using a third photoresist pattern (not shown). For example, the well contact 55 ′ is formed by etching through a dry etching process. Subsequently, a first metal layer 605 such as tungsten (W) is deposited on the resultant to a thickness sufficient to completely fill the inside of the well contact 55 ', followed by chemical mechanical polishing; The first metal layer 605 is polished by CMP) to planarize its surface.

Referring to FIG. 7B, after depositing aluminum (Al) on the resultant to deposit second metal layers 61 ′ and 600, the second metal layer 61 ′ is formed by using a fourth photoresist pattern 610. Pattern 600).

However, the above-described conventional method adds the processes of depositing and polishing the first metal layer, thereby causing a cost increase.

Accordingly, the present invention has been made to solve the problems of the conventional method described above, the object of the present invention is to easily form a substrate connection hole (well contact) without adding a separate process to reduce the substrate connection resistance and The present invention provides a nonvolatile memory device capable of preventing a short between a wiring layer and a selection transistor.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device which is particularly suitable for manufacturing the nonvolatile memory device.

1 is a schematic diagram illustrating a memory cell array of a NAND type flash memory device.

2 is a cross-sectional view of a memory cell transistor cut in a channel direction in a NAND type flash memory device.

FIG. 3 is a plan view illustrating a part of a memory cell array of a NAND type flash memory device according to a conventional method, corresponding to region A of FIG. 1.

4 is an enlarged plan view illustrating the well contact region in FIG. 3.

5A through 5D are cross-sectional views illustrating a well contact forming method of a NAND type flash memory device according to a conventional method, taken along line AA ′ of FIG. 4.

FIG. 6 is a cross-sectional view illustrating a well contact forming method of a NAND type flash memory device according to another conventional method along the line AA ′ of FIG. 4.

7A and 7B are cross-sectional views illustrating a well contact forming method of a NAND type flash memory device according to another method according to the AA ′ line of FIG. 4.

FIG. 8 is a plan view illustrating a part of a memory cell array of the NAND type flash memory device according to the present invention corresponding to region A of FIG. 1.

FIG. 9 is an enlarged plan view of the well contact region of FIG. 8. FIG.

10A to 10D are cross-sectional views illustrating a well contact forming method of a NAND type flash memory device according to the present invention, taken along line BB ′ of FIG. 9.

Explanation of symbols for the main parts of the drawings

100: semiconductor substrate 10, 11, 12, 13, 14, 15, 16: cell active

150: P type well 20, 21, 22, 23, 24, 25: Field oxide film

30,300: first conductive layer 45,46: select transistor

35,350: interlayer dielectric film 40,400: second conductive layer

450: insulating film spacer 50: bit line contact

51,52,53,56: Butting contact 54: Source contact

55,500: well contact 60: bit line

61 dummy metal wire 550 flattening film

62,63,64,65,600: metal wiring layer

In order to achieve the above object, the present invention provides a first conductivity type of n memory cell transistors, which is repeated in a second direction orthogonal to the first direction while being spaced apart from the field region on the semiconductor substrate and extending in the first direction. And a cell active pattern having a source / drain region of and a memory cell array having an array of n word lines repeated in a first direction while extending in a second direction on top of the cell active pattern. In

A string select transistor and a ground select transistor formed respectively outside the first and nth memory cell transistors; And a substrate junction hole formed in an independent second conductivity type active pattern surrounded by the field region for applying a voltage to the substrate of the memory cell array, wherein at least one ground select transistor is bypassed around the substrate junction hole. Wherein the substrate junction hole is disposed between the nth word line and the ground select transistor in the first direction and is disposed between the ground select transistors in the second direction. do.

The semiconductor substrate may further include a second conductivity type well formed in the semiconductor substrate and having the memory cell array disposed thereon.

The n memory cell transistors are connected in series by sharing a source / drain of the first conductivity type, and preferably, n is composed of 8 or an integer multiple of 8.

The word line or the ground select transistor is not disposed above the active pattern of the second conductivity type in which the substrate junction hole is formed.

In addition, the present invention to achieve the above object,

A cell active pattern spaced apart from the field region on the semiconductor substrate and extending in the first direction and repeated in a second direction perpendicular to the first direction, and extending in the second direction on top of the cell active pattern; A memory cell array comprising an array of n word lines repeated in one direction; N memory cell transistors each including a floating gate and a control gate stacked on the cell active pattern, and a source / drain region of a first conductivity type formed on an exposed substrate between the word lines; A string select transistor and a ground select transistor formed respectively outside the first and nth memory cell transistors; A bit connected to the cell active pattern through bit line junction holes formed between the string select transistors adjacent to each other, extending in the first direction at the same pitch as the cell active pattern on the word line; line; And a substrate connection hole formed in an independent second conductive type active pattern surrounded by a field region between each input / output for applying a voltage to the substrate of the memory cell array, wherein at least one ground select transistor is connected to the substrate connection. Wherein the substrate connection hole is disposed between the nth word line and the ground select transistor in the first direction and is disposed between the ground select transistors in the second direction by bypassing the hole around the hole. Provided is a volatile memory device.

The cell active pattern has an active line width at the bit line junction hole greater than or equal to an active line width of the memory cell transistor.

According to a preferred embodiment of the present invention, a common source active region extending in the second direction between the adjacent ground select transistors, a source connection hole formed for each bit line in the common source active region, and And a butting junction hole formed to connect the floating gate and the control gate to the field region between each input / output. The bit line junction hole is not disposed in the bit line in which the source connection hole is formed.

In order to achieve the above another object, the present invention provides a cell active formed in the upper portion of the semiconductor substrate, the cell active is repeated in a second direction orthogonal to the first direction while being spaced apart from the field region and extending in the first direction. Forming a pattern; By stacking a first conductive layer for a floating gate, an interlayer dielectric layer, and a second conductive layer for a control gate on the cell active pattern, and patterning the second conductive layer for a photolithography process, a memory cell having a stacked gate structure including the floating gate and the control gate. Forming a memory cell array comprising a transistor, a string select transistor, a ground select transistor, and n word lines extending in the second direction and orthogonal to the first direction and extending in the second direction, the at least one ground Forming a select transistor to bypass around a substrate connection hole to be formed in a subsequent process; Implanting an impurity of a first conductivity type into the exposed substrate between the word lines to form a source / drain region of the first conductivity type; Forming a planarization layer on top of the resultant product; Etching the planarization layer to form a substrate connection hole disposed between an n-th word line and a ground select transistor in the first direction and between the ground select transistors in the second direction; And forming a metal wiring layer on the substrate connection hole.

Before forming the field region on the semiconductor substrate, the method may further include ion implanting a second conductivity type impurity into the substrate to form a second conductivity type well on which the memory cell array is disposed. Can be.

In the patterning of the first conductive layer, the interlayer dielectric layer, and the second conductive layer by photolithography, the first conductive layer, the interlayer dielectric layer, and the first conductive layer may be defined so that the channel length of the memory cell transistor is defined as the line width of the word line. 2 The conductive layer is etched by the self-aligning method by one photo process.

Before forming the source / drain regions of the first conductivity type, the method may further include forming insulating layer spacers on sidewalls of the stack gate.

Prior to forming the planarization layer, the method may further include selectively exposing a portion where the substrate connection hole is to be formed and implanting impurities of a second conductivity type into the portion.

In the step of forming the substrate connection hole, preferably, the planarization film is etched in the order of wet etching / dry etching. In addition, the metal wiring layer is formed by sequentially stacking tin (Ti) / tin-nitride film compound / aluminum / tin-nitride film compound.

The method may further include selectively exposing a portion of the memory cell array in which the bit line junction hole is to be formed and ion implanting impurities of a first conductivity type into the portion.

According to the present invention, one of the two ground select lines GSL, which is a select transistor, is disposed so as to bypass the periphery of the substrate junction hole (hereinafter, referred to as a well contact), and the well contact is a ground select transistor different from the word line. Place in between. Thus, by simply disposing the well contact in a longer longitudinal structure along the Y axis without adding a separate process, it is possible to increase the contact area with the substrate to reduce the substrate connection resistance.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 8 is a plan view showing a portion of a memory cell array of a NAND type flash memory device according to the present invention corresponding to region A of FIG. 1, and FIG. 9 is an enlarged plan view of the well contact region in FIG. 8.

8 and 9, in the NAND type flash memory device according to the present invention, the cell active patterns 10, 11, 12, 13, 14, and 15 in which the channel and the source / drain of the memory cell transistor are to be formed are respectively fields. The regions 20, 21, 23, 24 are spaced apart and arranged repeatedly in the X axis while extending in the Y axis parallel to each other. The cell active patterns 10, 11, 12, 13, 14, and 15 are connected to an active pattern 17 for a common source.

On the cell active patterns 10, 11, 12, 13, 14, and 15, the word lines W are spaced at a predetermined distance orthogonal to the cell active patterns and the field regions 20, 21, 22, 23, and 24. / L ₁ , W / L ₂ ,..., W / L _n are repeatedly arranged in the Y-axis while extending in the X-axis, whereby a stacked gate structure memory cell transistor including a floating gate 30 and a control gate 40 is provided. To form. A high concentration of N-type source / drain regions 80 is formed on the surface of the exposed substrate between the word lines W / L ₁ , W / L ₂ ,..., W / L _n spaced as described above.

In the arrangement of the cell active patterns 10, 11, 12, 13, 14 and 15 extending along the Y axis and the word lines W / L ₁ , W / L ₂ , ..., W / L _n extending along the X axis. By forming a memory cell array having a predetermined degree of integration arranged in the XY direction, a string select line (i.e., a select transistor outside the first word line W / L ₁ and n-th word line W / L _n ), respectively. SSL) and a ground select line GSL are formed to form a string as one memory unit. In the string, n memory cell transistors are connected in series while sharing a source / drain.

One bit line connection hole (hereinafter referred to as a bit line contact) 50 is provided between the string select transistors SSL adjacent to each other, and the two strings have one bit line contact in the form of a mirror image. Share 50). The cell active patterns 10, 11, and 14 are orthogonal to the word lines through an insulating layer (not shown) on the word lines W / L ₁ , W / L ₂ ,..., W / L _n . A metal line 60 repeating along the X-axis is arranged on the upper side of the line 15 in parallel with the cell active pattern, and the bit lines B / L _k-1 , B / L _k , B / L ₁ , B / L ₂ ... The bit lines B / L _k-1 , B / L _k , B / L ₁ , B / L ₂ ,... Are formed on the cell active patterns 10, 11, 14, and 15 through bit line contacts 50. Connected with. Preferably, in the cell active patterns 10, 11, 12, 13, 14, and 15, the active line width of the bit line contact 50 is greater than or equal to the active line width of the memory cell transistor.

Another outer side of the string is provided with an active region 17 for the common source extending in the X-axis direction between adjacent ground select transistors GSL, and a plurality of common source active regions 17 in the common source active region 17. A source connection hole (hereinafter referred to as a source contact) 54 is formed for each bit line. Accordingly, the cell active patterns 10, 11, 12, 13, 14, and 15 and the common source active region 17 are connected to each other through the source contact 54. The bit line contact 50 is not disposed on the bit line where the source contact 54 is disposed.

Select transistors GSL (45, 46) to the floating gate 30 and the control gate 40 in the field region 22 between each input / output (I / O) in order to prevent signal delay due to resistance Strapping butt connecting holes (hereinafter referred to as butting contacts) 51, 52, 53 and 56 for connection are provided.

The active region 16 in which the well contacts 55 for forming a voltage on the substrate of the memory cell array are formed is surrounded by the field regions 22 separating the I / Os. The metal wiring layer 62 is connected to the active region 16 through the well contact 55. Here, the at least one ground select transistor GSL is disposed to bypass the well contact 55, so that the well contact 55 is connected to the nth word line W / L _{n in the} Y-axis direction. The transistors are disposed between the select transistors GSL and disposed between the ground select transistors GSL in the X-axis direction. The word lines W / L ₁ , W / L ₂ ,..., W / L _n and the ground select transistor GSL are not disposed on the well active region 16.

In FIG. 9, the distance Y ₂ between the nth word line W / L _n and the ground select transistor GSL 46 is the distance Y between two ground select transistors in a conventional nonvolatile memory device. ₁ ). In addition, L ₂ represents the distance between the well contact 55 and the adjacent conductive layers, that is, the nth word line W / L _n and the ground select transistors 45 and 46, and X ₂ represents the well contact 55. ) From the well active region 16. As shown in FIG. 9, the well contact 55 of the present invention is disposed in a longer longitudinal structure along the Y axis, thereby increasing the contact area with the substrate, thereby reducing the substrate connection resistance.

10A to 10D are cross-sectional views illustrating a well contact forming method of a NAND type flash memory device according to the present invention, taken along line BB ′ of FIG. 9.

Referring to FIG. 10A, a P-type well 150 used as a substrate region of a memory cell array is formed to a predetermined depth in a semiconductor substrate 100 through a conventional photolithography process, an ion implantation process, and a diffusion process. That is, the boron (B) ion is implanted with energy of 100 keV and a dose of ^{2 to} 3 × 10 ¹³ / cm ² and then diffused for 5 to 10 hours at a high temperature of 1050 to 1150 ° C. to form a P type of 2.5 to 3 μm depth The well 150 is formed. Subsequently, a field oxide film for dividing the substrate 100 including the P-type well 150 into an active region and a field region by performing a conventional device isolation process, for example, a selective polysilicon oxidation (SEPOX) process. (22,250) is formed to a thickness of 4500-6000 kPa.

Subsequently, a first gate oxide film and a tunnel oxide film (not shown) are grown on the resultant. In this case, the tunnel oxide film formed in the memory cell array is grown to a thickness of 90 to 100 Å, and the first gate oxide film of the selection transistor is formed to have a thickness equal to or greater than the thickness of the tunnel oxide film. Subsequently, the first conductive layer 300 is used as a floating gate of a memory cell transistor having a specific resistance of 250 to 400 Ω / □ by depositing polycrystalline silicon to a thickness of 1000 to 1500 GPa on the resultant and depositing a high concentration of N-type impurities. To form. Subsequently, an oxide film or a composite film of an oxide film and a nitride film is grown on the first conductive layer 300 to form an interlayer dielectric film 350 having an equivalent oxide film thickness of 160 to 200 GPa. Next, by depositing a polycrystalline silicon doped with a high concentration of N-type impurities on the interlayer dielectric film 350 to a thickness of 1000 ~ 1500 Å and a tungsten silicide film to a thickness of 1000 ~ 1500 Å on it, the resistivity is 8 ~ 10Ω The second conductive layer 400 used as the control gate of the memory cell transistor of / square is formed. Subsequently, the second conductive layer 400 and the interlayer dielectric layer 350 are formed using the first photoresist layer pattern PR 410 to form the word line 40 and the selection transistors GSL 45 'and 46'. ) And the first conductive layer 300 are anisotropically etched. Here, Y ₂ represents the distance between the _nth word line (W / L _n ) and one ground select transistor (GSL) 46.

Referring to FIG. 10B, after the first photoresist layer pattern 410 is removed, an oxide layer is deposited to a thickness of 1000 to 1500 kV over the resultant to form an LDD structure transistor, and then etched back to form the gate electrode ( An insulating film spacer 450 is formed on the sidewalls of 300 and 400 to a thickness of 800 to 1200 Å. Next, N-type impurities, such as arsenic (As) ions, are implanted with an energy of 50 keV and a dose of 5-6 × 10 ¹⁵ / cm ² using the insulating film spacer 450 to form an N ⁺ impurity region (not shown). ).

Subsequently, a second photoresist pattern 510 for selectively exposing only the well contact region and the P-type source / drain region of the P-channel transistor is formed by a conventional photolithography process, and then the exposed well is used as an ion implantation mask. P-type impurities 500, such as boron fluoride (BF ₂ ) ions, are implanted into the contact region and the source / drain regions at an energy of 40 to 60 keV and a dose of 5 to 6 x 10 ¹⁵ / cm ² .

Referring to FIG. 10C, after removing the second photoresist layer pattern 510, boron (B) and phosphorus (P) to planarize the surface of the substrate while insulating the metal wiring layer to be formed in a subsequent process and the gate electrodes 300 and 400. ) Is suitably formed to form a silicon glass film (BPSG) 550 having a thickness of 5000 to 6000 GPa. Subsequently, heat treatment is performed at a temperature of 800 to 900 ° C. for about 10 to 30 minutes to planarize the BPSG film 550, and then a third photosensitive film pattern 560 for forming a well contact thereon is subjected to a general photographic process. To form. Next, the well contact 55 is formed by etching the planarization layer 550 using wet etching and dry etching using the third photoresist pattern 560 as an etching mask. In FIG. 10C, a cross section of the well contact 55 is indicated by a dotted line, and the well contact 55 may be formed on the substrate by using a wet etching process and a dry etching process as described above. The step and the slope are formed gently so as to be connected. That is, the wet etching process is performed to easily form the metal wiring layer by reducing the opening aspect ratio of the well contact 55. Here, L _x2 represents the amount of etching in the lateral direction by wet etching. In the present invention, since one ground select transistor is disposed to bypass the periphery of the well contact 55, the conventional nonvolatile memory device in which the aperture aspect ratio C _y2 / C _x2 of the well contact 55 is shown in Fig. 5C. It can be seen that compared to the much improved. In addition, it can be seen that the distance (L ₂ ) from the well contact 55 to the nearest conductive layer also increases the process margin.

Referring to FIG. 10D, after removing the third photoresist layer pattern 560, a portion of the memory cell array in which a bit line contact (50 of FIG. 8) is to be formed is selectively exposed, and an N-type impurity is formed on the region. Ion). As a result, the N-type impurity concentration in the bit line contact becomes higher than the N-type impurity concentration in other regions.

Subsequently, in order to form the bit lines (60 in FIG. 8) and the metal wiring layers 62 and 600 of the memory cell array on top of the resultant, a composite film of Ti / TiN / Al / TiN is 200 to 400 mW / 300 to 500 mW / 5000 to Laminate to a thickness of 6000 Å / 200 to 300 Å. Subsequently, after the fourth photoresist pattern 610 is formed by a general photographic process, the bit lines and the metal wiring layers 62 and 600 are patterned using the fourth photoresist pattern 610 as an etching mask.

Next, an NAND type nonvolatile memory device is completed by forming an oxide film / nitride film at a thickness of 1000 to 2000 GPa / 5000 to 6000 GPa as a passivation layer (not shown) on top of the resultant product.

As described above, according to the NAND type nonvolatile memory device according to the present invention, one of the two ground select transistors GSL is disposed so as to bypass the periphery of the well contact, and the well contact is different from the word line. Arranged between select transistors.

Thus, by simply disposing the well contact in a longer longitudinal structure along the Y axis without adding a separate process, it is possible to increase the contact area with the substrate to reduce the substrate connection resistance. In addition, the opening aspect ratio of the well contact is reduced, so that the metal wiring layer and the well active region can be easily connected, and the metal wiring layer and the ground select transistor are spaced apart from each other by a sufficient distance.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (20)

Cell active spaced apart from the field region on the semiconductor substrate, extending in a first direction, repeated in a second direction orthogonal to the first direction, and forming a first conductivity type source / drain region of n memory cell transistors. A nonvolatile memory device having a pattern and an array of n cell lines arranged in an upper portion of the cell active pattern in a second direction and extending in a second direction. A string select transistor and a ground select transistor formed respectively outside the first and nth memory cell transistors; And A substrate bonding hole formed in an active pattern of an independent second conductivity type surrounded by the field region for applying a voltage to the substrate of the memory cell array, At least one ground select transistor is disposed bypassing the substrate junction hole so that the substrate junction hole is disposed between the nth word line and the ground select transistor in the first direction and the ground select transistor in the second direction. Nonvolatile memory device, characterized in that disposed between. The nonvolatile memory device of claim 1, further comprising a second conductivity type well formed in the semiconductor substrate, the second conductivity type well being disposed above the memory cell array. The nonvolatile memory device of claim 1, wherein the n memory cell transistors are connected in series by sharing a source / drain of the first conductivity type. The nonvolatile memory device of claim 1, wherein n is configured to be an integer multiple of eight or eight. The nonvolatile memory device of claim 1, wherein the word line or the ground select transistor is not disposed on the second conductive type active pattern in which the substrate junction hole is formed. A cell active pattern spaced apart from the field region on the semiconductor substrate and extending in the first direction and repeated in a second direction perpendicular to the first direction, and extending in the second direction on top of the cell active pattern; A memory cell array comprising an array of n word lines repeated in one direction; N memory cell transistors each including a floating gate and a control gate stacked on the cell active pattern, and a source / drain region of a first conductivity type formed on an exposed substrate between the word lines; A string select transistor and a ground select transistor formed respectively outside the first and nth memory cell transistors; A bit connected to the cell active pattern through bit line junction holes formed between the string select transistors adjacent to each other, extending in the first direction at the same pitch as the cell active pattern on the word line; line; And A substrate connection hole formed in an active pattern of an independent second conductivity type surrounded by a field region between each input / output to apply a voltage to the substrate of the memory cell array, At least one ground select transistor is disposed bypassing the substrate connection hole so that the substrate connection hole is disposed between the nth word line and the ground select transistor in the first direction and the ground select transistor in the second direction. Nonvolatile memory device, characterized in that disposed between. The nonvolatile memory device of claim 6, further comprising a second conductivity type well formed in the semiconductor substrate at a predetermined depth and having the memory cell array disposed thereon. The nonvolatile memory device of claim 6, wherein the n memory cell transistors are connected in series by sharing a source / drain of the first conductivity type. The nonvolatile memory device of claim 6, wherein the active line width of the cell active pattern is greater than or equal to an active line width of the memory cell transistor. 7. The semiconductor device of claim 6, wherein a common source active region extending in the second direction between the ground selection transistors adjacent to each other, a source connection hole formed for each of the plurality of bit lines in the common source active region, and the respective mouths; And a butting junction hole formed to connect the floating gate and the control gate to a field region between the outputs and the outputs. The nonvolatile memory device of claim 10, wherein the bit line junction hole is not disposed in the bit line in which the source connection hole is formed. The nonvolatile memory device of claim 6, wherein the word line or the ground select transistor is not disposed above the active region of the second conductivity type in which the substrate junction hole is formed. Forming a field region over the semiconductor substrate to form a cell active pattern spaced apart from the field region and extending in a first direction and repeated in a second direction perpendicular to the first direction; By stacking a first conductive layer for a floating gate, an interlayer dielectric layer, and a second conductive layer for a control gate on the cell active pattern, and patterning the second conductive layer for a photolithography process, a memory cell having a stacked gate structure including the floating gate and the control gate. Forming a memory cell array comprising a transistor, a string select transistor, a ground select transistor, and n word lines extending in the second direction and orthogonal to the first direction and extending in the second direction, the at least one ground Forming a select transistor to bypass around a substrate connection hole to be formed in a subsequent process; Implanting an impurity of a first conductivity type into the exposed substrate between the word lines to form a source / drain region of the first conductivity type; Forming a planarization layer on top of the resultant product; Etching the planarization layer to form a substrate connection hole disposed between an n-th word line and a ground select transistor in the first direction and between the ground select transistors in the second direction; And And forming a metal wiring layer on the substrate connection hole. The method of claim 13, wherein before the field region is formed on the semiconductor substrate, a second conductivity type well in which the memory cell array is disposed is formed by implanting impurities of a second conductivity type into the substrate. The method of manufacturing a nonvolatile memory device, characterized in that it further comprises. The method of claim 13, wherein in the patterning of the first conductive layer, the interlayer dielectric layer, and the second conductive layer by photolithography, the channel length of the memory cell transistor is defined as the line width of the word line. A method of manufacturing a nonvolatile memory device, wherein the layer, the interlayer dielectric film, and the second conductive layer are etched by a self-aligning method by one photolithography process. 15. The method of claim 13, further comprising forming insulating film spacers on sidewalls of the stacked gates before forming the source / drain regions of the first conductivity type. The method of claim 13, further comprising selectively exposing a portion where the substrate connection hole is to be formed and ion implanting impurities of a second conductivity type into the portion before forming the planarization layer. Method of manufacturing volatile memory device. The method of claim 13, wherein in the forming of the substrate connection hole, the substrate connection hole is formed by etching the planarization layer in the order of wet etching / dry etching. The method of claim 13, wherein the metal wiring layer is formed by sequentially stacking a tin / tin-nitride film compound / aluminum / tin-nitride film compound. The method of claim 13, further comprising selectively exposing a portion of the memory cell array in which the bit line junction hole is to be formed and ion implanting impurities of a first conductivity type into the portion before forming the metal wiring layer. The manufacturing method of the nonvolatile memory device characterized by the above-mentioned.