KR19990009399A - COG type liquid crystal panel and semiconductor IC with bump wiring - Google Patents
COG type liquid crystal panel and semiconductor IC with bump wiring Download PDFInfo
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- KR19990009399A KR19990009399A KR1019970031804A KR19970031804A KR19990009399A KR 19990009399 A KR19990009399 A KR 19990009399A KR 1019970031804 A KR1019970031804 A KR 1019970031804A KR 19970031804 A KR19970031804 A KR 19970031804A KR 19990009399 A KR19990009399 A KR 19990009399A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
본 발명은 COG방식의 액정표시장치에서 입력배선과 구동IC를 접속하는 구조 및 방법에 관한 것이다.The present invention relates to a structure and method for connecting an input wiring and a driving IC in a COG type liquid crystal display device.
종래의 액정표시장치는 상기 입력배선을 FPC에 형성하여 구동IC의 입력단자에 연결했었다. 그런데, 상기 FPC는 가격이 높아 많은 양을 사용하면, 액정표시장치의 단가가 비싸지는 단점이 있다. 그리고, 상기 FPC의 사용량을 줄이기 위해 입력배선을 기판에 직접 실장시킨 액정표시장치도 개발되었으나, 이 경우는 입력배선의 교차부에 정전용량이 발생하고, 상기 입력배선의 저항이 커 입력배선의 두께를 두껍게 해야 한다는 단점이 있다.In the conventional liquid crystal display, the input wiring is formed on the FPC and connected to the input terminal of the driving IC. However, the FPC has a disadvantage that if the price is high and a large amount is used, the unit cost of the liquid crystal display device is high. In addition, a liquid crystal display device in which an input wiring is directly mounted on a substrate has been developed to reduce the amount of use of the FPC. There is a downside to thickening.
본 발명은 상기 입력배선 중, 일부를 구동IC의 밑면에 형성하되, 상기 구동IC의 밑면에 입력전극을 형성하고, 상기 입력전극에 금(Au)으로 범프를 형성하며, 동시에 범프배선을 형성하여 상기 범프배선과 상기 입력배선을 연결시킨다. 그래서, 본 발명은 상기 구동IC의 밑면의 범프배선이 입력배선의 역할을 담당하게 함으로써 종래에 비해 상기 입력배선의 저항을 줄일 수 있다.According to the present invention, a part of the input wiring is formed on a bottom surface of the driving IC, an input electrode is formed on the bottom of the driving IC, bumps are formed of gold (Au) on the input electrode, and bump bumps are formed at the same time. The bump wiring and the input wiring are connected. Thus, the present invention can reduce the resistance of the input wiring compared to the prior art by allowing the bump wiring on the bottom surface of the driving IC to play the role of the input wiring.
본 발명은 종래에 비해 입력배선의 저항이 작아 신호지연현상이 줄어 들기 때문에 고화질의 액정표시장치를 제조할 수 있다.According to the present invention, since the resistance of the input wiring is smaller than that of the related art, the signal delay phenomenon is reduced, so that a high quality liquid crystal display device can be manufactured.
Description
본 발명은 액정표시장치의 신호선구동입력배선에 관한 것으로서, 신호선구동IC위 입력배선을 저저항으로 형성하는 것에 그 목적이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal line driving input wiring of a liquid crystal display device, and has an object of forming an input wiring on a signal line driving IC with low resistance.
일반적인 표시장치로서 사용되는 CRT브라운관은 RGB 전자총에 의해 영상을 표시하는 방법을 사용한다. 그러나, CRT브라운관은 표시영역을 크게하려면 필연적으로 두께를 증가시켜야 한다는 단점이 있다. 그 이유는 전자총과 브라운관의 표면 사이의 거리가 충분히 확보되어야만 화면에 영상을 표시할 수 있기 때문이다.The CRT CRT used as a general display device uses a method of displaying an image by an RGB electron gun. However, the CRT CRT has a disadvantage in that it is necessary to increase the thickness in order to enlarge the display area. The reason is that an image can be displayed on the screen only when the distance between the electron gun and the surface of the CRT is sufficiently secured.
그래서, 이러한 CRT브라운관을 대체하는 표시장치들이 개발 중에 있는데, 그중 액정표시장치는 CRT브라운관을 대체하는 표시장치로서 가장 가까이 실용화단계에 접근해 있다.Therefore, display devices are being developed to replace the CRT CRTs, among which the liquid crystal display is approaching the practical use stage as a display device to replace the CRT CRTs.
액정표시장치는 액정패널과 구동IC의 접착방법에 따라 TAB방식의 액정표시장치와 COG방식의 액정표시장치로 구분지을 수 있다. 종래에는 TAB방식의 액정표시장치가 주류를 이루었으나, 제작기술의 발달에 따라 COG방식이 액정표시장치도 많이 개발되고 있다.The liquid crystal display device may be classified into a TAB type liquid crystal display device and a COG type liquid crystal display device according to a method of bonding the liquid crystal panel and the driving IC. Conventionally, TAB type liquid crystal display devices have become mainstream, but COG type liquid crystal display devices have been developed with the development of manufacturing technology.
일반적인 COG방식의 액정표시장치는 도1에 나타낸 것과 같이 투명기판으로 형성된 상판(10)과 하판(11)으로 구성되어 있다. 도면에는 도시되지 않았지만, 상기 상판은 한쪽면에 편광판이 부착되어 있고, 반대면에는 칼라필터와 공통전극이 형성되어 있다. 그리고, 상기 하판은 도면에는 도시되지 않았지만, 한쪽면에 편광판이 부착되어 있고, 상기 상판보다 조금 더 넓다. 상기 하판은 편광판이 부착되지 않은 면이 상기 상판의 공통전극과 대향하도록 맞붙어 있다.A general COG type liquid crystal display device is composed of an upper plate 10 and a lower plate 11 formed of a transparent substrate as shown in FIG. Although not shown in the drawing, the upper plate has a polarizing plate attached to one side thereof, and a color filter and a common electrode formed on the opposite side thereof. Although the lower plate is not shown in the figure, a polarizing plate is attached to one side thereof, and is slightly wider than the upper plate. The lower plate is joined so that the surface on which the polarizer is not attached is opposite to the common electrode of the upper plate.
상기 하판은 상기 상판에 대응하는 제1영역(12)과 상판에 대응하지 않는 제2영역(13)으로 구분지을 수 있다. 상기 제1영역에는 주사선(22)과 신호선(23)이 서로 직교하며 형성되어 있다. 그리고, 상기 제2영역(13)에는 상기 주사선(22)에 연결된 주사선구동IC(14)와 상기 신호선(23)에 연결된 신호선구동IC(15)가 부착되어 있다.The lower plate may be divided into a first region 12 corresponding to the upper plate and a second region 13 not corresponding to the upper plate. In the first region, the scan line 22 and the signal line 23 are perpendicular to each other. In addition, a scan line driver IC 14 connected to the scan line 22 and a signal line driver IC 15 connected to the signal line 23 are attached to the second region 13.
상기 신호선구동IC(15)는 입력단자(17)와 출력단자(18)로 구성되어 있다. 상기 입력단자는 R(Red)단자 6개와 G(Green)단자 6개 및 B(Blue)단자 6개와 SSC(Shift Start Clock)단자와 SSP(Shift Start Pulse)단자와 LP(Latch Pulse)단자와 감마(Gamma)입력선 9개와 아날로그 접지단자와 디지탈 접지단자와 디지탈 전압의 3.3V 전원단자와 아날로그 전압의 4.2V 전원단자와 공통전압단자(Vcom)와 축적전압단자(Vst)와 데이터입력단자(Din)단자 등으로 구성되어 있다. 상기 각 단자들은 때에 따라 개수의 증감이 있을 수 있다. 그리고, 상기 출력단자(18)는 상기 신호선(23)에 하나씩 연결되어 있다. 일반적으로 하나의 신호선구동IC(15)에 약 80~100개의 출력단자가 있다.The signal line driver IC 15 is composed of an input terminal 17 and an output terminal 18. The input terminals include 6 R (Red) terminals, 6 G (Green) terminals, 6 B (Blue) terminals, SSC (Shift Start Clock) terminals, SSP (Shift Start Pulse) terminals, LP (Latch Pulse) terminals, and gamma. (Gamma) 9 input lines, analog ground terminal, digital ground terminal, 3.3V power terminal of digital voltage, 4.2V power terminal of analog voltage, common voltage terminal (Vcom), accumulated voltage terminal (Vst) and data input terminal (Din Terminal). Each of the terminals may increase or decrease in number from time to time. The output terminal 18 is connected to the signal line 23 one by one. Generally, there are about 80 to 100 output terminals in one signal line driver IC 15.
도2의 확대평면도에 나타낸 것과 같이 상기 신호선구동IC(24)의 각각의 전극(26)에는 범프(25)가 형성되어 있다. 상기 범프를 통해 상기 전극과 입력배선이 연결된다. 상기 범프를 형성하는 공정은 도3에 나타낸 것과 같다. 먼저 전극(26)이 형성된 IC(24)의 표면에 보호막(27)을 도포하고, 상기 전극(26)을 노출시킨다(도3a). 그리고, 상기 전극에 접촉되도록 상기 IC의 표면에 금속(28)을 증착시킨다(도3b). 상기 금속 위에 포토레지스트(29)를 도포하고, 전극에 해당하는 부분의 포토레지스트를 제거한다(도3c). 그리고, 상기 포토레지스트가 도포된 IC의 표면에 금을 전착하여 범프(25)를 형성한다. 그러면, 상기 포토레지스트가 제거된 부분만 금이 전착된다(도3d). 그 후, 상기 포토레지스트와 금속을 제거하면, 범프(25)가 완성된다(도3e). 도4는 상기 범프(25)가 완성된 IC(24)의 표면을 나타낸 평면도이다.As shown in the enlarged plan view of FIG. 2, bumps 25 are formed on the electrodes 26 of the signal line driver IC 24. As shown in FIG. The electrode and the input wiring are connected through the bumps. The process of forming the bumps is as shown in FIG. First, a protective film 27 is applied to the surface of the IC 24 on which the electrode 26 is formed, and the electrode 26 is exposed (FIG. 3A). Then, a metal 28 is deposited on the surface of the IC so as to contact the electrode (Fig. 3B). A photoresist 29 is applied on the metal, and the photoresist of the portion corresponding to the electrode is removed (Fig. 3C). Then, gold is deposited on the surface of the IC to which the photoresist is applied to form bumps 25. Then, gold is electrodeposited only on the portion where the photoresist is removed (FIG. 3D). After that, when the photoresist and the metal are removed, the bump 25 is completed (Fig. 3E). 4 is a plan view showing the surface of the IC 24 in which the bumps 25 are completed.
그리고, 상기 액정표시장치는 하판의 외부에 따로 설치된 PCB 회로기판(19)과 상기 입력단자를 연결하기 위하여 데이터전송선(connection cable)(20)과 FPC(21)를 이용하였다. 상기 FPC(21)에는 신호선구동IC와 주사선구동IC의 입력단자에 연결되는 입력배선(16)이 형성되어 있다. 도1은 PCB기판(19)과 FPC(21)가 데이터전송선(20)으로 연결되어 있고, 상기 FPC(21)와 신호선구동IC의 입력단자(17)가 연결된 액정표시장치를 나타낸 것이다.In addition, the liquid crystal display uses a data connection line 20 and an FPC 21 to connect the PCB 19 and the input terminal separately installed on the outside of the lower plate. The FPC 21 has an input wiring 16 connected to the input terminals of the signal line driver IC and the scan line driver IC. FIG. 1 shows a liquid crystal display device in which a PCB 19 and an FPC 21 are connected by a data transmission line 20 and the FPC 21 and an input terminal 17 of a signal line driver IC are connected.
액정표시장치를 제조하는데 있어서, 신호선구동IC 혹은, 주사선구동IC에 신호를 입력하는 입력배선이 형성된 FPC는 상당히 가격이 높다. 때로 COG방식의 액정표시장치는 상기 FPC의 사용량을 줄이기 위해 도5에 나타낸 것과 같이 상기 입력배선(16)을 하판(11)에 직접 실장하기도 한다. 도5의 액정표시장치는 FPC가 필요없다는 장점이 있으나, 하판(11)에 직접 입력배선(16)의 저항이 높아 신호가 지연된다는 단점이 있다. 또, 상기 도5의 액정표시장치는 입력배선의 교차부(35)에서 기생용량(parasitic capacitor)가 발생하여 신호가 더욱 지연된다.In manufacturing a liquid crystal display device, an FPC in which a signal line driver IC or an input wiring for inputting a signal to a scan line driver IC is formed is quite expensive. Sometimes, the COG type liquid crystal display device directly mounts the input wiring 16 to the lower plate 11 as shown in FIG. 5 to reduce the usage of the FPC. The LCD of FIG. 5 has the advantage of not requiring an FPC, but has a disadvantage in that a signal is delayed because the resistance of the input wiring 16 directly on the lower plate 11 is high. In addition, in the liquid crystal display of FIG. 5, a parasitic capacitor is generated at the intersection portion 35 of the input wiring to further delay the signal.
상기 입력배선의 교차부(35)를 줄이기 위해 도6에 나타낸 것과 같이 신호선구동IC(24)의 밑면에 입력배선(16)을 구성한 액정표시장치도 제조된다. 그러나, 상기 도6의 신호선구동IC는 모든 입력배선을 신호선구동IC의 밑면에 구성하려면, 상기 신호선구동IC의 크기를 크게 해야 한다는 문제점이 있다. 왜냐하면, 상술한 바와 같이 상기 입력배선은 상당히 많기 때문에 상기 신호선구동IC의 밑면이 상기 입력배선을 모두 수용하려면, 그 폭이 기존의 IC보다 커야 하기 때문이다.In order to reduce the intersection 35 of the input wiring, as shown in FIG. 6, a liquid crystal display device having an input wiring 16 formed on the underside of the signal line driver IC 24 is also manufactured. However, the signal line driver IC of FIG. 6 has a problem in that the size of the signal line driver IC needs to be increased in order to configure all the input wirings on the underside of the signal line driver IC. This is because, as described above, since the input wiring is quite large, the width of the signal line driver IC must be larger than that of the existing IC in order to accommodate all of the input wiring.
상기 입력배선의 교차부를 줄이고 상기 신호선구동IC의 폭을 종래에 비해 크게 하지 않기 위해서, 도7과 같이 입력배선(16)의 일부만 신호선구동IC(24)의 밑면에 형성시킬 수도 있다. 그러나, 상기 입력배선의 저항 때문에 신호선구동IC의 밑면에 형성된 입력배선의 두께를 크게 해야만 한다. 따라서, 상기 도7의 액정표시장치는 상기 신호선구동IC 밑면에 많은 입력배선을 형성시킬 수 없으므로, 결국 상기 도5의 액정표시장치와 마찬가지로 교차부가 많아진다는 단점은 극복하기 어렵다.In order to reduce the intersection of the input wiring and not make the width of the signal line driver IC larger than in the related art, only a part of the input wiring 16 may be formed on the bottom surface of the signal line driver IC 24 as shown in FIG. However, due to the resistance of the input wiring, the thickness of the input wiring formed on the underside of the signal line driver IC must be increased. Therefore, since the liquid crystal display of FIG. 7 cannot form many input wires under the signal line driver IC, it is difficult to overcome the disadvantage that the number of intersections increases as in the liquid crystal display of FIG.
그래서, 상기 교차부를 종래보다 대폭 줄이면서 입력배선의 저항도 대폭 낮출 수 있는 액정표시장치가 필요한 것이다.Accordingly, there is a need for a liquid crystal display device capable of significantly reducing the intersection portion and reducing the resistance of the input wiring.
도1은 일반적인 COG방식의 액정표시장치를 나타낸 것이다.1 shows a liquid crystal display of a general COG method.
도2는 범프가 형성된 구동IC를 나타낸 단면도이다.2 is a cross-sectional view illustrating a driving IC in which bumps are formed.
도3은 범프를 형성하는 공정을 나타낸 단면도이다.3 is a cross-sectional view showing a process of forming a bump.
도4는 범프가 형성된 구동IC를 나타낸 평면도이다.4 is a plan view illustrating a driving IC in which bumps are formed.
도5는 입력배선이 모두 하판에 형성된 COG방식의 액정표시장치를 나타낸 것이다.5 shows a COG type liquid crystal display device in which all input wirings are formed on the lower plate.
도6은 입력배선이 구동IC의 밑면에 형성된 COG방식을 액정표시장치를 나타낸 것이다.6 shows a liquid crystal display (COG) system in which input wiring is formed on the underside of a driving IC.
도7은 입력배선의 일부가 구동IC의 밑면에 형성되고, 나머지 입력배선은 구동IC의 외측면에 형성된 액정표시장치를 나타낸 것이다.7 shows a liquid crystal display device in which a part of input wiring is formed on the underside of the driving IC, and the other input wiring is formed on the outer surface of the driving IC.
도8은 본 발명의 구동IC를 제조하는 공정을 나타낸 단면도이다.8 is a cross-sectional view showing a process for manufacturing a drive IC of the present invention.
도9는 본 발명의 구동IC를 나타낸 평면도이다.9 is a plan view showing a drive IC of the present invention.
도10은 본 발명을 이용한 액정패널의 일부를 나타낸 평면도이다.10 is a plan view showing a part of a liquid crystal panel using the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10: 상판11: 하판10: top plate 11: bottom plate
12: 제1영역13: 제2영역12: first region 13: second region
14: 주사선구동IC15: 신호선구동IC14: Scan Line Drive IC 15: Signal Line Drive IC
16: 입력배선17: 입력전극16: input wiring 17: input electrode
18: 출력전극19: PCB 기판18: output electrode 19: PCB substrate
20: 데이터전송선21: FPC20: data transmission line 21: FPC
22: 주사선23: 신호선22: scanning line 23: signal line
24: IC25: 범프24: IC25: bump
26: 전극27: 보호막26 electrode 27 protective film
28: 금속29: 포토레지스트28: metal 29: photoresist
30: 주사선구동IC32: 주사출력전극30: scan line drive IC32: scan output electrode
40: 신호선구동IC42; 신호출력전극40: signal line driving IC42; Signal output electrode
70: 신호구동입력배선71: 주사구동입력배선70: signal drive input wiring 71: scan drive input wiring
100: IC110: 제1전극100: IC110: first electrode
115: 제2전극120: 보호막115: second electrode 120: protective film
130: 금속140: 포토레지스트130: metal 140: photoresist
150: 범프배선200: 하판150: bump wiring 200: lower plate
205: 제2영역210: 상판205: second region 210: top plate
215: 제1영역220: 제1입력배선215: first area 220: first input wiring
230: 신호선구동IC240: 제2입력배선230: signal line driver IC 240: second input wiring
245: 범프배선250: PCB기판245: bump wiring 250: PCB substrate
260: 데이터전송선260: data transmission line
본 발명은 입력배선의 일부분을 IC의 범프로 대체한 액정표시장치이다. 액정표시장치의 입력배선이 IC 밑면을 통과하도록 형성하되, IC 사이는 금속으로 배선을 형성하고, IC 밑면은 범프로 형성하는 것이다.The present invention is a liquid crystal display in which part of the input wiring is replaced with a bump of the IC. The input wiring of the liquid crystal display device is formed so as to pass through the bottom of the IC, and the wiring is made of metal between the ICs, and the bottom of the IC is formed of bumps.
본 발명의 IC는 입력전극과 출력전극 외에 제1전극과 제2전극들이 더 있다. 상기 제1전극으로 신호가 입력되면 범프배선을 통해 제2전극으로 전달되기도 하고, 상기 제2전극으로 신호가 입력되면 범프배선을 통해 제1전극으로 신호가 전달된다.The IC of the present invention further includes a first electrode and a second electrode in addition to the input electrode and the output electrode. When a signal is input to the first electrode, the signal may be transmitted to the second electrode through bump wiring. When a signal is input to the second electrode, the signal may be transmitted to the first electrode through bump wiring.
본 발명의 IC를 제조하는 방법은 도9의 A-A' 단면선으로 나타난 도8를 통해 설명된다. 먼저 IC(100)의 표면에 보호막(120)을 도포하고, 제1전극(110)과 제2전극(115) 위의 보호막을 제거하여 상기 제1전극과 제2전극을 노출시킨다(도8a). 그리고, 상기 제1전극(110)과 제2전극(115)이 접촉되도록 상기 IC(100)의 표면에 금속(130)을 증착시킨다(도8b). 그리고, 상기 금속 위에 포토레지스트(140)를 도포하고, 상기 제1전극과 제2전극 사이의 영역의 포토레지스트를 제거한다(도8c). 상기 포토레지스트가 제거된 상기 제1전극과 제2전극 사이의 영역에 금(Au)으로 범프(150)를 형성시킨다.(도8d). 즉, 범프로 상기 제1전극과 제2전극을 연결하는 것이다. 마지막으로 상기 IC표면에 남아있던 포토레지스트를 모두 제거하여 범프를 완성한다. 도9는 본 발명의 IC의 표면을 나타낸 평면도이다. 상기 금속(130)은 매우 얇은 층이므로, 저항이 높다. 따라서, 제1전극과 제2전극 사이의 신호는 주로 금(Au)으로 형성된 범프배선을 통해 흐른다.The method of manufacturing the IC of the present invention is explained with reference to FIG. 8, which is shown by the section line A-A 'of FIG. First, the protective film 120 is coated on the surface of the IC 100, and the protective film on the first electrode 110 and the second electrode 115 is removed to expose the first electrode and the second electrode (FIG. 8A). . Then, the metal 130 is deposited on the surface of the IC 100 such that the first electrode 110 and the second electrode 115 are in contact with each other (FIG. 8B). Then, the photoresist 140 is coated on the metal, and the photoresist in the region between the first electrode and the second electrode is removed (Fig. 8C). A bump 150 is formed of gold (Au) in a region between the first electrode and the second electrode from which the photoresist is removed (FIG. 8D). That is, the first electrode and the second electrode are connected by bumps. Finally, all of the photoresist remaining on the IC surface is removed to complete the bumps. Fig. 9 is a plan view showing the surface of the IC of the present invention. Since the metal 130 is a very thin layer, the resistance is high. Therefore, the signal between the first electrode and the second electrode flows through the bump wiring formed mainly of gold (Au).
본 발명을 이용한 액정패널은 상기 범프배선이 형성된 IC가 일정한 간격을 두고 하판에 실장되며, 하판의 상기 IC 사이 영역에는 금속으로 입력배선을 채워져 구성된다. 도10은 본 발명을 이용한 액정패널의 일부를 나타낸 평면도이다.In the liquid crystal panel using the present invention, ICs in which the bump wirings are formed are mounted on the lower plate at regular intervals, and the input wirings are filled with metal in the area between the ICs of the lower plate. 10 is a plan view showing a part of a liquid crystal panel using the present invention.
상기 본 발명을 이용한 액정패널의 하판은 화소가 형성된 제1영역(215)과, 상기 제1영역의 범위를 넘어서는 제2영역(205)으로 구성된 기판(200)과; 상기 제2영역의 가장자리에 형성된 제1입력배선(220)과; 상기 제1입력배선과 상기 제1영역의 가장자리 사이에 형성되고, 일정한 거리를 두고 불연속부를 가진 제2입력배선(240)과; 상기 제2입력배선의 불연속부에 형성되어, 상기 불연속부가 범프(245)에 의해 연결된 IC(230)를 포함하여 구성된다. 상기 불연속부의 길이는 상기 IC의 제1전극과 제2전극의 거리와 같거나 짧다.The lower panel of the liquid crystal panel according to the present invention includes a substrate 200 including a first region 215 on which pixels are formed, and a second region 205 exceeding the first region; A first input wiring 220 formed at an edge of the second region; A second input wiring 240 formed between the first input wiring and an edge of the first region and having a discontinuous portion at a predetermined distance; The IC 230 is formed on the discontinuous portion of the second input wiring, and the discontinuous portion includes an IC 230 connected by a bump 245. The length of the discontinuity is equal to or shorter than the distance between the first electrode and the second electrode of the IC.
상기 제1영역은 복수개의 주사선과 신호선이 직교하여 형성되고, 그 교차부에 화소가 형성되어 있다. 상기 화소는 박막트랜지스터와 화소전극으로 구성되어 있다. 상기 제2영역은 가장자리에 제1입력배선이 FPC 혹은, 데이터전송으로부터 인출되어 형성되어 있고, 상기 제1입력배선과 제1영역 사이의 공간에 복수개의 IC가 일정한 간격을 두고 설치되어 있으며, 상기 IC 사이에는 제2입력배선이 형성되어 있다. 상기 IC의 밑면에는 전극이 형성되어 있고, 상기 전극 위에 범프가 형성되어 있으며, 상기 범프에 연결된 범프배선이 형성되어 있다. 그리고, 상기 범프배선과 상기 제2입력배선이 연결되도록 IC가 하판에 설치되어 있다.The first region has a plurality of scan lines and signal lines orthogonal to each other, and pixels are formed at the intersections thereof. The pixel is composed of a thin film transistor and a pixel electrode. The second region has a first input wiring formed at an edge thereof withdrawn from the FPC or data transmission, and a plurality of ICs are provided at regular intervals in a space between the first input wiring and the first region. A second input wiring is formed between the ICs. An electrode is formed on a bottom surface of the IC, bumps are formed on the electrodes, and bump wirings connected to the bumps are formed. In addition, an IC is provided on the lower plate such that the bump wiring and the second input wiring are connected to each other.
본 발명의 IC의 단측면에 연결된 제2입력배선의 일부가 IC의 범프로 대체되어 있다. 상기 범프는 금(Au)으로 형성되므로, 저항이 일반적인 금속에 비해 매우 낮다. 그러므로, 본 발명의 제2입력배선은 종래의 입력배선보다 저항이 낮다. 그래서, 상기 제2입력배선의 폭이 종래보다 줄어들 여지가 있어 IC의 크기를 줄일 수 있다는 장점이 있다. 게다가 상기 IC의 크기를 줄임으로써 IC의 장측면에 연결되는 제1입력배선이 형성될 영역이 넓어지므로, 상기 제1입력배선의 폭을 넓혀 저항을 줄일 수 있다는 장점도 있다.A part of the second input wiring connected to the short side of the IC of the present invention is replaced by the bump of the IC. Since the bump is formed of gold (Au), the resistance is very low compared to that of a general metal. Therefore, the second input wiring of the present invention has a lower resistance than the conventional input wiring. Therefore, the width of the second input wiring has a possibility of reducing the size of the IC than conventional, there is an advantage that the size of the IC can be reduced. In addition, since the area of the first input wiring connected to the long side of the IC is increased by reducing the size of the IC, the width of the first input wiring can be widened to reduce the resistance.
따라서, 제1입력배선과 제2입력배선에 인가되는 신호가 지연되지 않으므로, 신호선구동IC에 인가되는 신호가 정확해져 액정표시장치의 화질이 깨끗해진다는 장점이 있다.Therefore, since the signals applied to the first input wiring and the second input wiring are not delayed, the signal applied to the signal line driver IC is corrected, and thus the image quality of the liquid crystal display device is clear.
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| KR100592222B1 (en) * | 1999-06-04 | 2006-06-23 | 삼성전자주식회사 | Liquid crystal display device |
| KR100835404B1 (en) * | 2006-03-29 | 2008-06-04 | 비오이 하이디스 테크놀로지 주식회사 | Liquid Crystal Display With Selection Pad And Method For Manufacturing Thereof |
| KR100840682B1 (en) * | 2002-09-06 | 2008-06-24 | 엘지디스플레이 주식회사 | Liquid crystal dispaly apparatus of line on glass type |
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| JPH02259624A (en) * | 1989-03-30 | 1990-10-22 | Sharp Corp | Display device |
| JP3340005B2 (en) * | 1995-11-27 | 2002-10-28 | 株式会社日立製作所 | Liquid crystal display |
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| KR100592222B1 (en) * | 1999-06-04 | 2006-06-23 | 삼성전자주식회사 | Liquid crystal display device |
| KR100840682B1 (en) * | 2002-09-06 | 2008-06-24 | 엘지디스플레이 주식회사 | Liquid crystal dispaly apparatus of line on glass type |
| KR100835404B1 (en) * | 2006-03-29 | 2008-06-04 | 비오이 하이디스 테크놀로지 주식회사 | Liquid Crystal Display With Selection Pad And Method For Manufacturing Thereof |
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