KR19990005857A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19990005857A KR19990005857A KR1019970030075A KR19970030075A KR19990005857A KR 19990005857 A KR19990005857 A KR 19990005857A KR 1019970030075 A KR1019970030075 A KR 1019970030075A KR 19970030075 A KR19970030075 A KR 19970030075A KR 19990005857 A KR19990005857 A KR 19990005857A
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- thin film
- copper thin
- forming
- containing silicon
- barrier layer
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 title claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052802 copper Inorganic materials 0.000 claims abstract description 34
- 239000010949 copper Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000010409 thin film Substances 0.000 claims abstract description 29
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000009832 plasma treatment Methods 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 8
- 238000011065 in-situ storage Methods 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 12
- 229920000642 polymer Polymers 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 230000009977 dual effect Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 1
- 230000007261 regionalization Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 2
- 229910021591 Copper(I) chloride Inorganic materials 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- OXBLHERUFWYNTN-UHFFFAOYSA-M copper(I) chloride Chemical compound [Cu]Cl OXBLHERUFWYNTN-UHFFFAOYSA-M 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 금속 배선 형성 방법에 관한 것임.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
낮은 융점과 높은 비저항을 갖는 알루마늄 합금의 대체 재료로 사용되는 구리를 이용한 패턴 형성시 전면을 인캡슐레이션하지 않으면 후속 열처리 공정시 쉽게 산화되는 문제가 있으며, 이러한 문제를 방지하기 위하여 듀얼 대머스컨스(dual damascence) 방법 등을 적용하고자 하는 연구가 있어 왔으나 이 방법은 미리 하층 구조를 형성시켜야 하는 문제가 있음.If the front surface is not encapsulated during pattern formation using copper, which is used as an alternative to aluminum alloys with low melting point and high resistivity, it is easily oxidized during the subsequent heat treatment process. There have been studies to apply the dual damascence method, but this method has a problem of forming the lower layer structure in advance.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
실리콘 원자가 함유된 구리 박막을 형성한 후 인-시투로 구리 박막을 플라즈마 식각하고 암모니아 플라즈마 처리 또는 질소를 이용한 급속 열처리 공정을 연속적으로 실시함.After forming a copper thin film containing silicon atoms, the copper thin film was plasma-etched by in-situ, and ammonia plasma treatment or rapid heat treatment using nitrogen was continuously performed.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
현재까지 반도체 재료로 사용되고 있는 알루미늄(Al) 합금은 낮은 융점과 높은 비저항으로 인하여 ULSI급 반도체 소자에서는 더 이상 적용이 어렵게 됨에 따라 대체 재료의 필요성이 대두되었고 그러한 재료중의 하나가 구리이다. 구리를 이용한 박막으로 패턴을 형성할 때 전면을 인캡슐레이션(encapsulation)하지 않으면 후속 열처리 공정시 쉽게 산화되는 문제가 있다. 이러한 문제를 방지하기 위하여 듀얼 대머스컨스(dual damascence) 방법 등을 적용하고자 하는 연구가 있어 왔으나 이 방법은 미리 하층 구조를 형성시켜야 하는 문제점이 있다.Aluminum (Al) alloys, which have been used as semiconductor materials to date, are becoming difficult to apply to ULSI semiconductor devices due to their low melting point and high resistivity, and one of such materials is copper. If the entire surface is not encapsulated when forming a pattern using a thin film using copper, there is a problem of easily oxidizing during a subsequent heat treatment process. In order to prevent such a problem, there have been studies to apply a dual damascence method, but this method has a problem of forming a lower layer structure in advance.
따라서, 본 발명은 단순한 공정으로 구리 박막이 쉽게 산화되는 것을 방지하므로써 상술한 문제점을 해결할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can solve the above problems by preventing the copper thin film from being easily oxidized by a simple process.
상술한 목적을 달성하기 위한 본 발명은 실리콘 기판 상부에 제 1 절연막, 제 1 장벽층, 실리콘 원자가 함유된 구리 박막 및 제 2 장벽층을 순차적으로 형성하는 단계와, 상기 제 2 장벽층 상부에 제 2 절연막을 형성하고 패터닝하는 단계와, 상기 패터닝된 제 2 절연막을 마스크로하여 제 2 장벽층, 실리콘 원자가 함유된 구리 박막 및 제 1 장벽층을 플라즈마를 이용하여 순차적으로 식각하는 단계와,According to an aspect of the present invention, a first insulating film, a first barrier layer, a copper thin film containing silicon atoms, and a second barrier layer are sequentially formed on a silicon substrate, and the second barrier layer is formed on the silicon substrate. Forming and patterning an insulating film, sequentially etching a second barrier layer, a copper thin film containing silicon atoms, and a first barrier layer using a plasma using the patterned second insulating film as a mask;
실리콘이 함유된 기체를 이용한 과도 식각으로 상기 실리콘 원자가 함유된 구리 박막의 측벽에 실리콘이 적게 함유된 제 1 폴리머를 형성하는 단계와, 암모니아 플라즈마 처리를 실시하여 상기 실리콘 원자가 함유된 구리 박막의 전면에 실리콘이 다량 함유된 제 2 폴리머를 형성하는 단계로 이루어진 것을 특징으로 한다.Forming a first polymer containing less silicon on the sidewall of the copper thin film containing silicon atoms by transient etching using a gas containing silicon, and performing ammonia plasma treatment on the front surface of the copper thin film containing silicon atoms Forming a second polymer containing a large amount of silicon is characterized in that.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings
1 : 실리콘 기판 2 : 제 1 절연막1: silicon substrate 2: first insulating film
3 : 제 1 장벽층 4 : 구리 박막3: first barrier layer 4: copper thin film
5 : 제 2 장벽층 6 : 제 2 절연막5: second barrier layer 6: second insulating film
7 : 제 1 폴리머(Si less film) 8 : 제 2 폴리머(Si rich film)7: first polymer (Si less film) 8: second polymer (Si rich film)
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 1(a)에 도시된 바와 같이 실리콘 기판(1) 상부에 제 1 절연막(2), 제 1 장벽층(3), 구리 박막(4) 및 제 2 장벽층(5)을 순차적으로 형성한다. 제 1 절연막(2)은 SiO2막, BPSG막 및 TEOS막 등으로 형성된다. 구리 박막(4)은 0.5%∼5%의 실리콘 원자가 첨가된 구리를 화학 기상 증착(Chemical Vapor Deposition; CVD) 또는 물리 기상 증착(Physical Vapor Deposition; PVD) 방법으로 증착하여 형성한다. 제 1 및 제 2 장벽층(3, 5)은 티타늄나이트라이드(TiN) 또는 PESIN을 증착하여 형성한다. 제 2 장벽층(5) 상부에 플라즈마 산화막등과 같은 산화물 계통의 제 2 절연막(6)을 형성하고 패터닝한다.As shown in FIG. 1A, a first insulating film 2, a first barrier layer 3, a copper thin film 4, and a second barrier layer 5 are sequentially formed on the silicon substrate 1. . The first insulating film 2 is formed of a SiO 2 film, a BPSG film, a TEOS film, or the like. The copper thin film 4 is formed by depositing copper to which 0.5% to 5% of silicon atoms are added by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first and second barrier layers 3 and 5 are formed by depositing titanium nitride (TiN) or PESIN. A second insulating film 6 of an oxide type such as a plasma oxide film or the like is formed and patterned on the second barrier layer 5.
도 1(b)는 패터닝된 제 2 절연막(6)을 마스크로하여 제 2 장벽층(5), 구리 박막(4) 및 제 1 장벽층(3)을 플라즈마를 이용하여 식각한다. 플라즈마를 이용한 식각은 BCl3, Cl2, CCl4등과 같은 염소계 플라즈마를 이용하여 200℃ 이상에서 실시한다. 계속해서 SiCl4와 같은 실리콘이 포함된 기체를 이용한 과도 식각을 실시하여 구리 박막(4)의 내부 측벽에 SixNy(O) 계통의 폴리머(7)를 형성한다. 이때 식각 부산물은 CuClx의 형태로 휘발되므로 구리 박막(4)의 내부 측벽에 SixNy계통(SixNy(Oz); Si less film)의 제 1 폴리머(7)가 형성된다.In FIG. 1B, the second barrier layer 5, the copper thin film 4, and the first barrier layer 3 are etched using plasma using the patterned second insulating layer 6 as a mask. The etching using the plasma is performed at 200 ° C. or more using a chlorine-based plasma such as BCl 3 , Cl 2 , CCl 4, or the like. Subsequently, transient etching is performed using a gas containing silicon such as SiCl 4 to form a Si x N y (O) based polymer 7 on the inner sidewall of the copper thin film 4. At this time, since the etching by-product is volatilized in the form of CuCl x , the first polymer 7 of the Si x N y system (Si x N y (O z ); Si less film) is formed on the inner sidewall of the copper thin film 4.
도 1(c)는 암모니아(NH3) 플라즈마 처리 또는 질소(N2)를 이용한 급속 열처리 공정을 실시하여 제 1 폴리머(7)가 형성된 구리 박막(4)의 전면에 제 2 폴리머(8)를 형성한 단면도이다. 이때 구리 박막(4)내에 함유된 실리콘 원자가 구리 박막의 표면으로 이동되어 구리 박막의 측벽에서 실리콘과 질소간의 화합물(SixNy(Oz); Si rich film)을 형성하여 전면을 인캡슐레이션한다. 즉, 열역학적 측면에서 볼 때 Cu-Si간의 결합보다는 Si-N간의 결합이 보다 안정된 상태이므로 NH3플라즈마 처리 또는 N2를 이용한 급속 열처리 공정 등을 통하여 구리 박막 내부에 존재하는 Si 원자를 표면으로 이동시킬 수 있다. 이때 NH3플라즈마 처리는 750∼900℃의 온도와 0.3∼0.5 Torr의 압력 및 300∼700W의 전력 조건에서 실시한다. 또한, 플라즈마를 이용한 식각, 실리콘 원자가 포함된 기체를 이용한 식각, 그리고 NH3플라즈마 처리 또는 N2를 이용한 급속 열처리 공정은 하나의 챔버내에서 연속적으로 실시한다. 즉, 인-시투(IN-SITU)로 실시한다.FIG. 1 (c) shows a second polymer 8 on the entire surface of the copper thin film 4 on which the first polymer 7 is formed by performing an ammonia (NH 3 ) plasma treatment or a rapid heat treatment process using nitrogen (N 2 ). It is formed section. At this time, the silicon atoms contained in the copper thin film 4 are transferred to the surface of the copper thin film to form a compound between silicon and nitrogen (Si x N y (O z ); Si rich film) on the sidewall of the copper thin film to encapsulate the entire surface. do. That is, from the thermodynamic point of view, the Si-N bond is more stable than the Cu-Si bond, so the Si atoms present in the copper thin film are moved to the surface through the NH 3 plasma treatment or the rapid heat treatment process using N 2 . You can. At this time, the NH 3 plasma treatment is performed at a temperature of 750 to 900 ° C., a pressure of 0.3 to 0.5 Torr, and a power condition of 300 to 700 W. In addition, etching using plasma, etching using a gas containing silicon atoms, and rapid heat treatment using NH 3 plasma treatment or N 2 are continuously performed in one chamber. That is, it is performed in IN-SITU.
상술한 바와 같이 본 발명에 의하면 단순한 공정으로 구리 금속 배선을 인캡슐레이션할 수 있으므로 금속 배선의 산화를 방지할 수 있다.As described above, according to the present invention, since the copper metal wiring can be encapsulated in a simple process, the oxidation of the metal wiring can be prevented.
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| KR1019970030075A KR100274339B1 (en) | 1997-06-30 | 1997-06-30 | Method of forming a metal wiring in a semiconductor device |
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| KR1019970030075A KR100274339B1 (en) | 1997-06-30 | 1997-06-30 | Method of forming a metal wiring in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100542644B1 (en) * | 2002-05-08 | 2006-01-11 | 닛본 덴끼 가부시끼가이샤 | Semiconductor device having silicon-including metal wiring layer and its manufacturing method |
| US7687917B2 (en) | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH08330422A (en) * | 1995-05-31 | 1996-12-13 | Nec Corp | Semiconductor device and manufacture of the same |
| KR0149572B1 (en) * | 1995-08-22 | 1998-12-01 | 김주용 | Copper film etching method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100542644B1 (en) * | 2002-05-08 | 2006-01-11 | 닛본 덴끼 가부시끼가이샤 | Semiconductor device having silicon-including metal wiring layer and its manufacturing method |
| US7687917B2 (en) | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
| US7737555B2 (en) | 2002-05-08 | 2010-06-15 | Nec Electronics Corporation | Semiconductor method having silicon-diffused metal wiring layer |
| US7842602B2 (en) | 2002-05-08 | 2010-11-30 | Renesas Electronics Corporation | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
| US8115318B2 (en) | 2002-05-08 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
| US8642467B2 (en) | 2002-05-08 | 2014-02-04 | Renesas Electronics Corporation | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
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| KR100274339B1 (en) | 2001-01-15 |
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