KR19980084173A - Semiconductor device having device isolation film and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device having a device isolation film and a method of manufacturing the same. The present invention includes a device isolation film in which two material layers each having opposite material properties in stress characteristics in a trench are sequentially filled. Therefore, in the subsequent heat treatment process, the difference in thermal expansion rate between the material layer filling the trench and the substrate may be alleviated, so that lattice defects or the like generated on the substrate near the trench may continue to grow in the subsequent heat treatment process. It is possible to prevent the source and drain from turning on between adjacent transistors and junction leakage current which may occur through the trench as a result.

Description

Semiconductor device having device isolation film and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a device isolation film and a method of manufacturing the same, and more particularly, to a semiconductor device having a trench type device isolation film filled with an insulating material layer having opposite physical properties, and a method of manufacturing the same.

Device isolation characteristics in the semiconductor device are very important not only for improving the characteristics of semiconductor devices in units of cells but also for improving the characteristics of a semiconductor device including a plurality of cells. In particular, it is more important in the situation where the cell density of semiconductor devices is increasing day by day.

As semiconductor devices become more integrated, active regions and field regions on a substrate become narrower. Therefore, not only the width of various patterns formed in the active region is reduced, but also the pitch between the patterns is very small. This result is applied to the field region as it is, the device isolation technology that can further improve the device isolation characteristics.

Currently, in the manufacturing process of semiconductor devices, LOCOS and trench device isolation are widely used as device isolation methods. Among them, the LOCOS method is difficult to use in a future high integration era since the device isolation layer extends into the active region to reduce the active region. In the trench method, since the device isolation layer is formed by forming a trench at a predetermined depth in the substrate, there is no problem in that the device isolation film is extended to the active region as in the LOCOS method. However, problems related to the yield and reliability of semiconductor devices have arisen. This problem will be embodied through a detailed description of a semiconductor device having a device isolation film according to the prior art and a method of manufacturing the same.

1 to 3 are diagrams illustrating a semiconductor device having a device isolation film according to the prior art and a method of manufacturing the same.

First, referring to FIG. 3, in a semiconductor device having a device isolation film according to the related art, a trench 18 is formed on a semiconductor substrate 10, and a thin oxide film 20 is formed on the entire surface of the trench 18. have. The oxide film 20 is a thermal oxide film. An isolation layer 22a is formed in the trench 18 in which the oxide film 20 is formed. The element isolation film 22a is a USG film. The gate oxide layer 26 is formed on the adjacent semiconductor substrate 40 on the same plane as the device isolation layer 22a, and the gates are sequentially formed at positions spaced apart from the trench 18 by a predetermined distance on the gate oxide layer 26. A gate stack 28 formed of a first conductive layer pattern 28a, a gate second conductive layer pattern 28b, and a gate protective film pattern 28c is formed.

Next, a method of manufacturing a semiconductor device having a device isolation film according to the prior art will be described with reference to FIGS. 1 to 3.

Referring to FIG. 1, the semiconductor substrate 10 is divided into an active region and a field region, and a mask layer including first to third insulating layer patterns 12, 14, and 16 is formed on the active region. A trench 18 having a predetermined depth is formed in a portion corresponding to the field region of the semiconductor substrate 10 by using the mask layer as an etching mask. An oxide film 20 is formed on the entire inner surface of the trench 18. The oxide film 20 is formed of a thermal oxide film. A fourth insulating film 22 filling the trench 18 in which the oxide film 20 is formed on the inner surface is formed on the entire surface of the mask layer. Subsequently, a fifth insulating film 24 is formed over the fourth insulating film 22. The fourth insulating film 22 is formed of a USG film. The USG film has a thermal expansion rate about three times smaller than that of the silicon layer. Therefore, in the heat treatment process, the fourth insulating layer 22 is subjected to tensile stress. Subsequently, as shown in FIG. 2, the front surface of the resultant is first planarized. Primary planarization is performed until the interface of the second insulating film pattern 14 is exposed. As a result of the first planarization, the fifth insulating film 24 is completely removed and the fourth insulating film 22 is completely removed in the region corresponding to the active region of the semiconductor substrate 10. That is, it exists only in the trench 18 region. Subsequently, secondary planarization is performed on the entire surface of the fourth insulating film pattern 22a filling the second insulating film 14 and the trench 18. Secondary planarization is performed until the interface of the semiconductor substrate 10 is exposed. By the second planarization, the active region of the semiconductor substrate 10 is completely exposed, and the isolation layer 22a, which is also a fourth insulating layer pattern, is formed in the trench 18.

Subsequently, as shown in FIG. 3, the gate oxide layer 26 is formed on the entire surface of the active region, and the gate stack 28 is formed on the gate oxide layer at a predetermined distance from the trench. The gate stack 28 is formed of the gate first conductive layer pattern 28a, the gate second conductive layer pattern 28b, and the gate passivation layer pattern 28c sequentially formed.

As described above, in the semiconductor device having the device isolation film according to the related art and the method of manufacturing the same, dislocations due to silicon lattice defects are generated near the bottom of the trench 18 in the process of forming the trench 18. These dislocations grow further in a particular direction by thermal expansion coefficient differences between the material layer filling the trenches and the substrate, eventually forming leakage sources in the side portions under the trenches. When the transistor is formed by such a leak source, a junction leakage current is generated, which results in the source and drain regions interposed between the trenches being always turned on.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having an isolation layer capable of preventing deterioration of isolation characteristics due to dislocations of a silicon lattice.

Another object of the present invention is to provide a method of manufacturing the semiconductor device.

1 to 3 are diagrams illustrating a semiconductor device having a device isolation film according to the prior art and a method of manufacturing the same.

4 through 11 are diagrams illustrating a semiconductor device including a device isolation layer and a method of manufacturing the same according to an exemplary embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

40: Semiconductor substrate. 42, 42a: mask layer, mask layer pattern.

44, 46, and 48: first, second and third insulating films.

50: Anti Reflective Layer.

52a: Photoresist pattern. 54: Trench.

56: oxide film. 58, 60: first and second material layers.

62: fourth insulating film. 66: gate stack.

68, 70: gate first and second conductive layer patterns.

72: gate protective film pattern.

In order to achieve the above technical problem, a semiconductor device having an isolation layer according to the present invention includes a trench having a predetermined depth formed on a semiconductor substrate, a first material layer pattern formed on an entire surface of the trench, and the first filling of the trench. A second material layer pattern having a physical property opposite to the material layer pattern is provided.

According to an embodiment of the present invention, an oxide film having a predetermined thickness is further formed between the entire surface of the trench and the first material layer pattern.

According to an embodiment of the present invention, the oxide film has a portion formed on the side of the trench is thicker than the portion formed on the bottom.

According to an embodiment of the present invention, the first material layer pattern is an HTO film pattern as an insulating material layer pattern in which a stress characteristic is compressed.

According to an embodiment of the present invention, the second material layer pattern is a USG film pattern as an insulating material layer pattern in which the stress characteristic is tensilized.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a device isolation film according to the present invention comprises the steps of (a) forming a trench having a predetermined depth on the semiconductor substrate; And (b) sequentially forming and filling the trenches with material layers having opposite physical properties.

According to an embodiment of the present invention, step (a) (1) sequentially forms the first, second and third insulating films on the semiconductor substrate. (2) An antireflection film is formed on the third insulating film. (3) A photoresist pattern is formed on the antireflection film to expose a predetermined region of the antireflection film. (4) A mask layer is formed by sequentially patterning the antireflection film and the third to first insulating films by using the photoresist pattern as an etching mask. (5) The photosensitive film pattern is removed. (6) A trench having a predetermined depth is formed in the exposed area of the substrate using the mask layer.

According to an embodiment of the present invention, the step (b) comprises the steps of (b1) forming an oxide film in a predetermined thickness on the entire surface of the trench; (b2) forming a first material layer in a predetermined thickness on the entire surface of the mask layer and the oxide film; (b3) forming a second material layer on the front surface of the first material layer, the second material layer having opposite physical properties to the first material layer filling the trench; (b4) forming a fourth insulating film on the entire surface of the second material layer; (b5) performing a high temperature heat treatment on the resultant product on which the fourth insulating film is formed; And (b6) planarizing the entire surface of the high temperature heat-treated resultant until the interface of the semiconductor substrate is exposed.

According to an embodiment of the present invention, the first material layer is formed of an insulating material layer having a compressive property of stress, and the second material layer is an insulating material having a tensile property of stress. Form into layers.

According to an embodiment of the present invention, the first material layer is formed of an HTO film having a compressive characteristic of stress.

According to an embodiment of the present invention, the second material layer is formed of a USG film having tensile stress characteristics.

According to an embodiment of the present invention, the resultant formed the fourth insulating film is heat-treated at a temperature of 900 ℃ or more.

In the semiconductor device including the device isolation layer according to the present invention, material layers having opposite characteristics of stress are provided inside the trench as device isolation layers. Therefore, defects due to the potential of the silicon lattice generated in the substrate near the bottom of the trench after trench formation can be prevented from growing by the subsequent heat treatment process, such as a shallow pit that appears after the trench type isolation layer is formed. It is possible to prevent the formation of trench defects.

Hereinafter, a semiconductor device having an isolation layer and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 through 11 are diagrams illustrating a semiconductor device including a device isolation layer and a method of manufacturing the same according to an exemplary embodiment of the present invention.

First, a semiconductor device including an isolation layer according to an embodiment of the present invention will be described.

Referring to FIG. 11, a trench 54 having a predetermined depth is formed in a region divided into a field region of the semiconductor substrate 40. The trench 54 has a depth of about 2,500 μs. A gate insulating film 64 is formed on the active region in contact with the trench 54, and the gate insulating film 64 is a thermal oxide film. A gate stack 66 spaced apart from the trench 64 by a predetermined interval is formed on the gate insulating layer 64. The gate stack 66 may include a gate first conductive layer 68, a gate second conductive layer 70, and a gate passivation layer 72.

An oxide film 56 having a predetermined thickness is formed on the entire surface of the trench 54. The oxide film 56 is a thermal oxide film having a thickness of about 100 kPa to 300 kPa. The thermal oxide film is a material film for removing a leakage current source due to a silicon lattice defect or the like generated in a substrate near the trench 54 in the process of forming the trench 54. The oxide film 56 (thermal oxide film) has a thicker side portion than the bottom portion of the trench 56. The first material layer pattern 58a is formed on the entire surface of the oxide film 56. The first material layer pattern 58a is an insulating material layer pattern having a compressive stress characteristic. For example, the first material layer pattern 58a is a high temperature oxide (HTO) film pattern. The HTO film pattern has a thickness of about 1,000 kPa to 3,000 kPa. The inside of the trench 54 in which the first material layer pattern 58a is formed is filled with a second material layer pattern 60a having a physical property opposite to that of the first material layer pattern 58a. The second material layer pattern 60a is planarized with an interface of the semiconductor substrate 40. However, the planarization is a planarization that allows a step less than 1,000 dB between the trench 54 region and the active region. The second material layer pattern 60a is an insulating material layer pattern exhibiting a tensile stress characteristic opposite to the compressive stress. For example, the second material layer pattern 60a exhibiting the tensile stress characteristic may be an undoped silicate glass (USG) film pattern.

As described above, in the semiconductor device according to the present invention, the inside of the trench 54 is filled with two material layer patterns showing opposite physical characteristics. These results can serve as complementary to the side effects that can be caused by different coefficients of thermal expansion. Therefore, defects that may be caused by growth of defects due to the silicon lattice potential inherent near the trench of the substrate may be prevented, for example, a junction leakage current or a phenomenon in which the source and drain of an adjacent transistor are always turned on. have.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described.

Referring to FIG. 4, a mask layer 42 is formed on the semiconductor substrate 40. The mask layer 42 is formed of the first, second and third insulating layers 44, 46, and 48 and the anti-reflective layer (hereinafter referred to as ARC) sequentially formed. The first insulating film 44 is formed of a thermal oxide film, and is formed to a thickness of about 110 kPa to 160 kPa. The second insulating layer 46 is formed of a nitride film (Si ₃ N ₄ ), and is formed to a thickness of about 1,500 Å. In addition, the third insulating film 48 is formed of a high temperature oxide film (hereinafter referred to as HTO) to a thickness of about 500 kPa. In addition, the ARC 50 is formed of a SiON film, but has a thickness of about 600 kPa.

5 shows a step of forming a mask layer pattern 42a defining a trench formation region. Specifically, a photosensitive film (not shown) is applied to the entire surface of the ARC (50 of FIG. 4). Subsequently, the photoresist is patterned to form a photoresist pattern 52a exposing a predetermined region of the ARC 50. The exposed area of the ARC 50 is an area corresponding to the trench formation area. Subsequently, the mask layer (42 in FIG. 4) is anisotropically etched until the interface of the semiconductor substrate 40 is exposed using the photoresist pattern as an etching mask. As a result, the first to third insulating layer patterns 44a, 46a, 48a and the ARC pattern 50a which define the trench forming region corresponding to the exposed region of the photoresist pattern 52a of the semiconductor substrate 40 are formed. The mask layer pattern 42a comprised is formed. Thereafter, the photoresist pattern 52a is removed.

6 illustrates forming a trench 54. Specifically, the trench 54 having a predetermined depth is formed by anisotropically etching the exposed portion of the semiconductor substrate 40 by using the mask layer pattern 52a of FIG. 5 as an etching mask. The trench 54 is formed to a thickness of about 2,500 Å. In this process, the ARC pattern 50a which is a component of the mask layer pattern 42a and formed on the uppermost layer is removed, so that the mask layer pattern 42a includes the first to third insulating layer patterns 44a, 46a, and 48a. Is formed of a mask layer pattern 42b composed of

7 shows forming an oxide film 56 over the trench 54. Specifically, the oxide film 56 is formed on the entire surface of the trench 54 at a thickness of about 100 kV to about 300 kV, and the oxide film 56 is formed of a thermal oxide film. The oxide layer 56 is formed to have a different thickness according to the portion of the trench 54. That is, the portion formed on the bottom of the trench 54 is formed thinner than the portion formed on the side. The oxide layer 56 is formed to remove a leakage source in the vicinity of a trench generated by a lattice defect of a substrate in the process of forming the trench 54.

8 illustrates filling the trench 54 with a plurality of material layers 58 and 60. In detail, the first material layer 58 is formed on the mask layer pattern 42b from which the ARC pattern 50a is removed and on the entire surface of the oxide layer 56. The first material layer 58 is formed of an insulating material layer having a stress characteristic, for example, an HTO film. The first material layer 58 is formed to a thickness of about 1,000 ~ 3,000Å. Subsequently, a second material layer 60 is formed on the entire surface of the first material layer 58 to fill the trench 54 in which the first material layer 58 is partially formed on the side and the bottom. The second material layer 60 is an insulating material layer whose physical properties are opposite to that of the first material layer 58. In other words, unlike the first material layer 58, the second material layer 60 is formed of an insulating material layer that is tensilized, for example, a USG (Undoped Silicate Glass) film. Thus, the first and second material layers 58 and 60 have complementary properties to thermal expansion seen in subsequent heat treatment processes. After forming the second material layer 60, the entire surface of the second material layer 60 is planarized. A fourth insulating layer 62 is formed on the planarized second material layer 60. The fourth insulating layer 62 is formed of a plasma enhanced-tetra ethyl ortho silicate (PE-TEOS) film. The USG film, which is the second material layer 60, and the PE-TEOS film, which is the fourth insulating film 62, are both formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Subsequently, after the fourth insulating film 62 is formed, the entire resultant is heat treated at a high temperature of 900 ° C. or higher (eg, 900 ° C. to 1100 ° C.). This heat treatment is to prevent the oxide layer in the field region from being excessively recessed in the subsequent planarization process by increasing the density of the fourth insulating layer 62.

9 and 10 illustrate forming a trench type isolation layer. Specifically, as shown in FIG. 9, the first planarization of the entire surface of the fourth insulating layer 62 is started until the first planarization is performed until the interface of the second insulating layer pattern 46a is exposed. As a result of the first planarization, only the first and second insulating layer patterns 44a and 46a remain on the active region in contact with the trench 54 of the semiconductor substrate 40, and the second material is formed in the trench 54 region. The layer and the first material layer 60 and 58 in FIG. 8 are sequentially planarized to leave the first and second material layer patterns 58a and 60a. An interface between the second insulating layer pattern 46a and the material layer filling the trench 54 including the first and second material layer patterns 58a and 60a forms the same plane. Subsequently, second planarization is performed on the entire surface of the first planarized result. The second planarization is performed until the interface corresponding to the active region of the semiconductor substrate 40 is exposed. The second planarization is performed such that the step between the interface corresponding to the active region of the semiconductor substrate 40 and the interface of the material layer filling the trench 54 obtained as a result of the second planarization does not exceed 1,000 mW. A trench type isolation layer is formed on the semiconductor substrate 40 by the second planarization.

Subsequently, as shown in FIG. 11, a gate insulating film 64 is formed over the entire active region of the semiconductor substrate 40. The gate first conductive layer pattern 68, the gate second conductive layer pattern 70, and the gate passivation layer pattern 72 are sequentially formed on the gate insulating layer 64 at a position spaced apart from the trench 54 by a predetermined distance. A gate stack 66 consisting of these patterns is formed. Thereafter, semiconductor devices such as transistors and capacitors are formed according to a predetermined procedure.

As described above, the semiconductor device including the device isolation film and the method of manufacturing the same according to the present invention include a device isolation film sequentially filled with two material layers having opposite material properties in stress characteristics in the trench. Therefore, in the subsequent heat treatment process, the difference in thermal expansion rate between the material layer filling the trench and the substrate may be alleviated, so that lattice defects or the like generated on the substrate near the trench may continue to grow in the subsequent heat treatment process. It is possible to prevent the source and drain from turning on between adjacent transistors and junction leakage current which may occur through the trench as a result.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit of the present invention.

Claims (14)

(a) forming a trench having a predetermined depth on the semiconductor substrate; And and (b) sequentially forming and filling the trenches with material layers having opposite physical properties to each other. The method of claim 1, wherein step (a) (1) sequentially forming first, second and third insulating films on the semiconductor substrate; (2) forming an anti-reflection film on the third insulating film; (3) forming a photoresist pattern on the antireflection film to expose a predetermined region of the antireflection film; (4) forming a mask layer by sequentially patterning the antireflection film and the third to first insulating films using the photoresist pattern as an etching mask; (5) removing the photoresist pattern; And (6) forming a trench having a predetermined depth in the exposed region of the substrate using the mask layer. The method of claim 2, wherein the first, second, and third insulating films and the anti-reflection film are formed of a thermal oxide film, a nitride film, an HTO film, and a SiON film, respectively. The method of claim 2, wherein step (b) (b1) forming an oxide film in a predetermined thickness on the entire surface of the trench; (b2) forming a first material layer in a predetermined thickness on the entire surface of the mask layer and the oxide film; (b3) forming a second material layer on the front surface of the first material layer, the second material layer having opposite physical properties to the first material layer filling the trench; (b4) forming a fourth insulating film on the entire surface of the second material layer; (b5) performing a high temperature heat treatment on the resultant product on which the fourth insulating film is formed; And and (b6) planarizing the entire surface of the high temperature heat-treated resultant until the interface of the semiconductor substrate is exposed. The method of claim 4, wherein the oxide film is formed of a thermal oxide film. The method of claim 4, wherein the first material layer is formed of an insulating material layer having a compressive characteristic of stress. 7. The method of claim 6, wherein the first material layer is formed of an HTO film having a compressive stress property. The method of manufacturing a semiconductor device with an element isolation film according to claim 7, wherein the HTO film is formed to a thickness of about 1,000 to 3,000 Å. The method of claim 4, wherein the second material layer is formed of an insulating material layer in which stress characteristics are tensilized. 10. The method of claim 9, wherein the second material layer is formed of a USG film having tensile stress characteristics. The method according to claim 4, wherein the fourth insulating film is formed of a PE-TEOS film. 5. The method of claim 4, wherein the resultant product having the fourth insulating film is heat-treated at a temperature of 900 占 폚 or higher. The method of claim 12, wherein the entire surface of the resultant heat-treated at a temperature of 900 ° C. or more is planarized using a CMP method. 6. The method of claim 5, wherein the thermal oxide film has a thicker side portion than the bottom portion of the trench.