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KR19980083732A - Digital liquid crystal display panel drive circuit - Google Patents

Digital liquid crystal display panel drive circuit Download PDF

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Publication number
KR19980083732A
KR19980083732A KR1019970019142A KR19970019142A KR19980083732A KR 19980083732 A KR19980083732 A KR 19980083732A KR 1019970019142 A KR1019970019142 A KR 1019970019142A KR 19970019142 A KR19970019142 A KR 19970019142A KR 19980083732 A KR19980083732 A KR 19980083732A
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KR
South Korea
Prior art keywords
array
liquid crystal
crystal display
display panel
digital
Prior art date
Application number
KR1019970019142A
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Korean (ko)
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KR100229380B1 (en
Inventor
안길범
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구자홍
엘지전자 주식회사
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Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019970019142A priority Critical patent/KR100229380B1/en
Priority to JP12838698A priority patent/JPH10319924A/en
Priority to FR9806174A priority patent/FR2763416A1/en
Priority to GB9810599A priority patent/GB2325329A/en
Priority to DE1998121914 priority patent/DE19821914A1/en
Publication of KR19980083732A publication Critical patent/KR19980083732A/en
Application granted granted Critical
Publication of KR100229380B1 publication Critical patent/KR100229380B1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

본 발명은 디지탈 영상신호에 의해 액정표시판넬을 구동하여 화상이 액정표시판넬에 표시되도록 하는 디지탈방식의 액정표시판넬 구동회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital liquid crystal display panel driving circuit for driving an LCD panel by a digital video signal so that an image is displayed on the liquid crystal display panel.

이 디지탈방식의 액정표시판넬 구동회로는 n개의 화소데이타들을 입력하여 일시적으로 보관하기 위한 기억소자어레이와, 기억소자어레이로부터의 n개의 화소데이타를 k개씩 순차적으로 아날로그 화소신호로 변환하기 위한 디지탈-아날로그변환기어레이와, 기억소자어레이로부터의 n개의 화소데이타중 k개의 화소데이타를 선택하고 그 선택된 k개의 화소데이타를 상기 디지탈-아날로그변환기어레이쪽으로 전달하기 위한 디멀티플렉서어래이와, 액정표시판넬상의 n개의 데이타라인중 k개의 데이타라인을 선택하고 디지탈-아날로그변환기어레이로부터의 k개의 화소신호를 그 선택된 k개의 데이타라인쪽으로 전달하기 위한 멀티플렉서어래이를 구비한다.This digital liquid crystal display panel driving circuit includes a memory element array for inputting and temporarily storing n pixel data and a digital element for sequentially converting n pixel data from the memory element array into analog pixel signals by k sequentially. An analog converter array, a demultiplexer array for selecting k pixel data of the n pixel data from the storage element array and transferring the selected k pixel data to the digital-analog converter array, and n data on the liquid crystal display panel. A multiplexer array is provided for selecting k data lines of the line and delivering k pixel signals from the digital-to-analog converter array to the selected k data lines.

상기 구성에 의하여, 디지탈방식의 액정표시판넬 구동회로는 회로구성을 간소화함은 물론 순간전력소모량을 감소시킬 수 있는 이점을 제공한다.By the above configuration, the digital liquid crystal display panel driving circuit provides an advantage of simplifying the circuit configuration and reducing the instantaneous power consumption.

Description

디지탈방식의 액정표시판넬 구동회로Digital liquid crystal display panel drive circuit

제 1 도는 종래의 디지탈영상신호용 액정표시판넬 구동회로가 적용된 액정표시장치를 도시하는 도면.1 is a diagram showing a liquid crystal display device to which a conventional liquid crystal display panel driving circuit for a digital image signal is applied.

제 2 도는 본 발명의 실시 예에 따른 디지탈방식의 액정표시판넬 구동회로가 적용된 액정표시장치를 도시하는 도면.2 is a diagram illustrating a liquid crystal display device to which a digital liquid crystal display panel driving circuit according to an exemplary embodiment of the present invention is applied.

제 3 도는 제2도에 도시된 구동회로의 각부분의 동작타이밍도.3 is an operation timing diagram of each part of the driving circuit shown in FIG.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10,30 : 액정표시판넬20,40 : 액정표시판넬 구동회로10,30: liquid crystal display panel 20,40: liquid crystal display panel driving circuit

22,42 : 제1 래치어래이24,44 : 제2 래치어래이22,42: first latch array 24,44: second latch array

26,48 : D-A변환기어래이28,52 : 출력증폭기어래이26,48: D-A converter array 28,52: Output amplifier array

46 : 디멀티플렉서어래이50 : 감마보정부46: demultiplexer array 50: gamma complement

54 : 멀티플렉서어래이54: Multiplexer Array

본 발명은 액정표시판넬을 이용하는 표시장치에 관한 것으로, 특히 액정표시판넬을 디지탈(Digital)영상신호에 의해 구동하는 디지탈방식의 액정표시판넬 구동회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device using a liquid crystal display panel, and more particularly to a digital liquid crystal display panel driving circuit for driving a liquid crystal display panel by a digital image signal.

최근, 영상매체는 시청자에게 고해상도의 화상을 제공하기 위한 방식으로 기존의 아날로그(Analog) 영상신호 대신에 정보의 압축이 용이한 디지탈 영상신호로 전송하는 방식으로 전환되어가고 있는 추세에 있다. 이에 따라, 영상표시장치의 한 종류인 액정표시판넬도 기존의 아날로그 영상신호 대신에 디지탈 영상신호에 의해 구동될 수 있어야 하는 입장에 처하게 되었다. 이를 위하여, 액정표시판넬용 구동회로는 아날로그신호를 요구하는 액정표시판넬의 화소들을 구동하기 적합하도록 새롭게 구성되고 있다. 이 결과, 액정표시판넬 구동회로에는 기존의 아날로그방식의 액정표시판넬 구동회로와 디지탈방식의 액정표시판넬 구동회로가 병존하고 있다.Recently, video media have been converted to a digital video signal that can easily compress information instead of an analog video signal in order to provide a high resolution image to a viewer. Accordingly, the liquid crystal display panel, which is a type of image display device, is also in a position to be driven by a digital image signal instead of the existing analog image signal. To this end, the driving circuit for the liquid crystal display panel is newly configured to be suitable for driving pixels of the liquid crystal display panel requiring an analog signal. As a result, a conventional analog liquid crystal display panel driving circuit and a digital liquid crystal display panel driving circuit coexist in the liquid crystal display panel driving circuit.

이러한 액정표시판넬 구동회로는 액정표시판넬상의 화소들 각각에 영상신호에 해당하는 전압을 정확하게 인가할 수 있는 충분한 신호공급시간을 확보하여야만 한다. 이를 해결하기 위하여, 아날로그방식의 액정표시판넬 구동회로로서는 1수평주사라인상의 화소들을 2개 이상의 일정한 갯수씩 순차적으로 구동하는 방안이 일본국 공개특허공보 제1995-181933호에 개시되었다. 이 일본국 공개특허공보 제1995-181933호에 따르면, 아날로그방식 액정표시판넬 구동회로는 지연소자를 이용하여 영상신호를 지연시키고 지연된 영상신호는 수평라인상의 중간부분으로부터 우측끝에 이르는 화소들에 그리고 지연되지 않은 영상신호는 좌측끝으로부터 중앙부분에 이르는 화소들에 순차적으로 인가하였다. 이와같은 아날로그방식 액정표시판넬 구동회로는 아날로그 영상신호를 화소의 구동전압으로써 그대로 이용하기 때문에 수평라인상의 화소들을 2개씩 순차적으로 구동하여도 화소별로 충분한 신호공급시간을 확보할 수 있었다.Such a liquid crystal display panel driving circuit must secure a sufficient signal supply time for accurately applying a voltage corresponding to an image signal to each of the pixels on the liquid crystal display panel. In order to solve this problem, a method of sequentially driving two or more constant number of pixels on one horizontal scanning line as an analog type liquid crystal display panel driving circuit is disclosed in Japanese Patent Laid-Open No. 1995-191933. According to Japanese Patent Application Laid-Open No. 1995-191933, the analog-type liquid crystal display panel driving circuit uses a delay element to delay the video signal, and the delayed video signal is delayed to pixels extending from the middle to the right end on the horizontal line. The non-video signal was sequentially applied to the pixels from the left edge to the center portion. Since the analog type liquid crystal display panel driving circuit uses the analog image signal as the driving voltage of the pixel, it is possible to secure a sufficient signal supply time for each pixel even when two pixels on the horizontal line are sequentially driven.

이와는 달리, 디지탈방식 액정표시판넬 구동회로는 디지탈 영상신호를 아날로그 영상신호로 변환하는 신호변환시간을 요구하기 때문에 상기 일본국 공개 특허공보 제1995-181933호에서와 같은 아날로그방식 액정표시판넬 구동방안으로는 화소별 신호공급시간을 충분하게 확보할 수없다. 이에 따라, 디지탈방식 액정표시판넬 구동회로는 1수평라인상의 화소들을 동시에 구동하도록 제1도에 도시된 바와 같이 구성되었다.On the contrary, since the digital liquid crystal display panel driving circuit requires a signal conversion time for converting a digital image signal into an analog image signal, the analog liquid crystal display panel driving scheme as in Japanese Patent Laid-Open No. 1995-191933 is used. Cannot sufficiently secure the signal supply time for each pixel. Accordingly, the digital liquid crystal display panel driving circuit is configured as shown in FIG. 1 to simultaneously drive pixels on one horizontal line.

제1도를 참조하면, 액정표시판넬(10)은 각각 수직방향으로 배열된 600개의 화소들에 접속된 2400개의 데이타라인(DL1 내지 DL2400)을 구비한다. 그리고 액정표시판넬(10)상의 600×2400 개의 화소들을 구동하기 위한 구동회로(20)는 제1 내지 제3 데이타버스(Data Bus; DB1 내지 DB3)에 접속된 제1 래치어래이(22)와, 이 제1 래치어래이(22)에 종속 접속되어진 제2 래치어래이(24), 디지탈-아날로그(Digital-Analog; 이하 D-A라 함) 변환기어래이(26) 및 출력증폭기어래이(28)로 구성된다. 제1 및 제2 래치어래이(22,24)는 각각 2400개의 래치들로 구성된다. 제1 래치어래이(22)에 포함된 2400개의 래치들은 800개씩 구분되어 제1 내지 제3 데이타버스(DB1 내지 DB3)에 분산 접속된다. 아울러, 제1 래치어래이(22)에 포함된 2400개의 래치들은 3개씩 순차적으로 구동되어 제1 내지 제3 데이타버스(DB1 내지 DB3)로부터 1수평라인분의 적색(이하 R이라 함), 녹색(이하 G라 함) 및 청색(이하 B라 함) 화소데이타를 입력한다. 그리고 제2 래치어래이(24)에 포함된 2400개의 래치들은 각각 제1 래치어래이(22)의 2400개의 래치들로부터의 화소데이타를 동시에 입력하여 D-A변환기어래이(26)쪽으로 전송한다. 그러면, D-A변환기어래이(26)은 제2 래치어래이(24)로부터의 2400개의 화소데이타를 모두 화소신호로 변환하고 그 변환되어진 2400개의 화소신호를 출력증폭기어래이(28)에 공급한다. 이를 위하여 D-A변환기어래이(25)는 도시하지 않은 감마보정부로부터의 일정한 갯수(예를 들면, 5개)의 변환소스신호들을 공통적으로 입력하는 2400개의 D-A변환기어래이들로 구성된다. 이들 2400개의 D-A변환기어래이들은 각각 제2 래치어래이(24)의 해당래치로부터의 화소데이타의 논리값에 따라 변환소스신호들의 일부 또는 전부를 가산함으로써 화소신호를 발생하게 된다. 마지막으로, 출력증폭기어래이(28)은 D-A변환기어래이(26)로부터의 2400개의 화소신호들을 일정한 증폭율로 증폭하고 그 증폭된 2400개의 화소신호들을 액정표시판넬(10)의 2400개의 데이타라인(DL1 내지 DL2400)에 분산 공급한다. 이를 위하여, 출력증폭기어래이(28)도 D-A변환기어래이(26)의 2400개의 D-A변환기들에 분산접속된 2400개의 출력증폭기들을 구비한다.Referring to FIG. 1, the liquid crystal display panel 10 includes 2400 data lines DL1 to DL2400 connected to 600 pixels arranged in a vertical direction, respectively. The driving circuit 20 for driving 600 × 2400 pixels on the liquid crystal display panel 10 includes a first latch array 22 connected to first to third data buses DB1 to DB3; And a second latch array 24, a digital-analog (DA) converter array 26 and an output amplifier array 28 that are cascaded to the first latch array 22. As shown in FIG. The first and second latch arrays 22 and 24 each consist of 2400 latches. The 2400 latches included in the first latch array 22 are divided by 800 and distributed to the first to third data buses DB1 to DB3. In addition, the 2400 latches included in the first latch array 22 are sequentially driven three by three, so that one horizontal line of red (hereinafter, referred to as R) and green (from the first to third data buses DB1 to DB3) is applied. Hereafter referred to as G) and blue (hereinafter referred to as B) pixel data. Each of the 2400 latches included in the second latch array 24 simultaneously inputs pixel data from the 2400 latches of the first latch array 22 to the D-A converter array 26. Then, the D-A converter array 26 converts all 2400 pixel data from the second latch array 24 into pixel signals and supplies the converted 2400 pixel signals to the output amplifier array 28. To this end, the D-A converter array 25 is composed of 2400 D-A converter arrays for commonly inputting a predetermined number (eg, five) of conversion source signals from a gamma correction unit (not shown). These 2400 D-A converter arrays each generate a pixel signal by adding some or all of the conversion source signals according to a logic value of the pixel data from the corresponding latch of the second latch array 24. Finally, the output amplifier array 28 amplifies the 2400 pixel signals from the DA converter array 26 at a constant amplification rate and converts the amplified 2400 pixel signals to 2400 data lines DL1 of the liquid crystal display panel 10. To DL2400). To this end, the output amplifier array 28 also includes 2400 output amplifiers distributedly connected to the 2400 D-A converters of the D-A converter array 26.

이상과 같이, 종래의 디지탈방식의 액정표시판넬 구동회로는 액정표시판넬상의 1수평라인분의 화소들을 동시에 구동하여 화소별 신호공급시간을 충분하게 확보할 수 있었다. 그러나, 종래의 디지탈방식의 액정표시판넬 구동회로에서는 액정표시판넬의 수평라인에 포함된 화소의 수에 해당하는 D-A변환기들과 출력증폭기들이 사용되어야 하므로 그 회로구성이 복잡해지는 것은 물론이거니와 부피도 커지게 된다. 아울러, 종래의 디지탈방식의 액정표시판넬 구동회로에서는 많은 수의 D-A변환기들과 출력증폭기들이 동시에 구동되어야 하므로 순간 전력소모를 매우 커지게 한다.As described above, the conventional digital liquid crystal display panel driving circuit can drive the pixels of one horizontal line on the liquid crystal display panel at the same time to secure a sufficient signal supply time for each pixel. However, in the conventional digital liquid crystal display panel driving circuit, since the DA converters and output amplifiers corresponding to the number of pixels included in the horizontal line of the liquid crystal display panel have to be used, the circuit configuration is complicated and the volume is also large. You lose. In addition, in the conventional digital liquid crystal display panel driving circuit, a large number of D-A converters and output amplifiers must be driven at the same time, thereby greatly increasing instantaneous power consumption.

따라서, 본 발명의 목적은 회로구성을 간소화 할 수 있고 순간 전력소모를 감소시킬 수 있는 디지탈방식의 액정표시판넬 구동회로를 제공함에 있다.Accordingly, an object of the present invention is to provide a digital liquid crystal display panel driving circuit which can simplify the circuit configuration and reduce the instantaneous power consumption.

본 발명의 다른 목적은 액정표시판넬의 인출라인의 수량을 감소시킬 수 있는 디지탈방식의 액정표시판넬 구동회로를 제공함에 있다.Another object of the present invention is to provide a digital liquid crystal display panel driving circuit which can reduce the number of lead-out lines of the liquid crystal display panel.

상기 목적을 달성하기 위하여, 본 발명에 따른 디지탈방식의 액정표시판넬 구동회로는 수직방향으로 배열된 m개의 화소들에 공통적으로 접속되고 수평방향으로 나란하게 배열된 n개의 데이타라인을 가지는 액정표시판넬과, n개의 화소데이타들을 입력하여 일시적으로 보관하기 위한 기억소자어래이와, 기억소자어래이로부터의 n개의 화소데이타를 k개씩 순차적으로 아날로그 화소신호로 변환하기 위한 디지탈-아날로그변환기어래이와, 기억소자어래이와 디지탈-아날로그변환기어래이 사이에 접속되어 기억소자어래이로부터의 n개의 화소데이타중 k개의 화소데이타를 선택하고 그 선택된 k개의 화소데이타를 상기 디지탈-아날로그변환기어래이쪽으로 전달하기 위한 디멀티플렉서어래이와, 디지탈-아날로그변환기어래이와 n개의 데이타라인들 사이에 설치되어 n개의 데이타라인중 k개의 데이타라인을 선택하고 디지탈-아날로그변환기어래이로부터의 k개의 화소신호를 그 선택된 k개의 데이타라인쪽으로 전달하기 위한 멀티플렉서어래이를 구비한다.In order to achieve the above object, the digital liquid crystal display panel driving circuit according to the present invention has a liquid crystal display panel having n data lines commonly connected to m pixels arranged in the vertical direction and arranged in parallel in the horizontal direction. And a storage element array for temporarily storing and inputting n pixel data, a digital-to-analog converter array for converting n pixel data from the storage element array into analog pixel signals sequentially by k, and a storage element array. A demultiplexer array and a digital multiplexer array connected to the digital-analog converter array for selecting k pixel data of the n pixel data from the memory array array and transferring the selected k pixel data to the digital-analog converter array. Between the analog converter array and n data lines And having the same multiplexer arrays for delivering k pixel signal from the analog converter eoraeyi toward the selected k of the data line is installed, the selection of n data lines of the k data lines and digital.

본 발명에 따른 디지탈방식의 액정표시판넬 구동회로에서는 멀티플렉서어래이가 액정표시판넬에 탑재되도록 하여 액정표시판넬의 인출라인의 수를 최소화 한다.In the liquid crystal display panel driving circuit of the digital method according to the present invention, the multiplexer array is mounted on the liquid crystal display panel to minimize the number of lead-out lines of the liquid crystal display panel.

상기 목적들 외에 본 발명의 다른 목적 및 잇점들을 첨부도면을 참조한 다음의 바람직한 실시 예에 대한 상세한 설명을 통하여 명확하게 드러나게 될 것이다.Other objects and advantages of the present invention in addition to the above objects will become apparent from the following detailed description of the preferred embodiment with reference to the accompanying drawings.

이하, 본 발명의 바람직한 실시 예를 첨부한 제2도 및 제3도를 참조하여 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

제 2 도를 참조하면, 본 발명의 실시 예에 따른 디지탈방식의 액정표시판넬 구동회로를 포함하는 액정표시장치가 도시되어 있다. 제2도에 있어서, 액정표시장치는 액정표시판넬(30)에 접속되어진 액정표시판넬 구동회로(40)를 구비한다. 액정표시판넬(30)은 각각 수직방향으로 배열된 600개의 화소들에 공통적으로 접속된 2400개의 데이타라인(DL1 내지 DL2400)을 구비한다.Referring to FIG. 2, a liquid crystal display including a digital liquid crystal display panel driving circuit according to an exemplary embodiment of the present invention is illustrated. 2, the liquid crystal display device includes a liquid crystal display panel drive circuit 40 connected to the liquid crystal display panel 30. As shown in FIG. The liquid crystal display panel 30 includes 2400 data lines DL1 to DL2400 commonly connected to 600 pixels arranged in the vertical direction.

한편, 액정표시판넬(30)상의 600×2400 개의 화소들을 구동하기 위한 구동회로(40)는 제1 내지 제3 데이타버스(DB1 내지 DB3)에 접속된 제1 래치어래이(42)와, 이 제1 래치어래이(42)에 종속 접속되어진 제2 래치어래이(44), 디멀티플렉서어래이(46) 및 D-A변환기어래이(48)을 구비한다. 제1 및 제2 래치어래이(42,44)는 각각 2400개의 래치들로 구성된다. 제1 래치어래이(42)에 포함된 2400개의 래치들은 800개씩 구분되어 제1 내지 제3 데이타버스(DB1 내지 DB3)에 분산 접속된다. 아울러, 제1 래치어래이(42)에 포함된 2400개의 래치들은 3개씩 순차적으로 구동되어 제1 내지 제3 데이타버스(DB1 내지 DB3)로부터 1수평라인분의 R,G 및 B 화소데이타를 입력한다. 그리고 제2 래치어래이(44)에 포함된 2400개의 래치들은 각각 제1 래치어래이(42)의 2400개의 래치들로부터의 화소데이타를 동시에 입력하여 디멀티플렉서어래이(46)쪽으로 전송한다.Meanwhile, the driving circuit 40 for driving 600 × 2400 pixels on the liquid crystal display panel 30 includes a first latch array 42 connected to the first to third data buses DB1 to DB3, and A second latch array 44, a demultiplexer array 46, and a DA converter array 48 that are cascaded to the first latch array 42 are provided. The first and second latch arrays 42 and 44 each consist of 2400 latches. The 2400 latches included in the first latch array 42 are divided by 800 and distributed to the first to third data buses DB1 to DB3. In addition, 2400 latches included in the first latch array 42 are sequentially driven three by three to input one horizontal line of R, G, and B pixel data from the first to third data buses DB1 to DB3. . Each of the 2400 latches included in the second latch array 44 simultaneously receives pixel data from the 2400 latches of the first latch array 42 and transmits the same to the demultiplexer array 46.

디멀티플렉서어래이(46)은 제2 래치어래이(44)로부터의 2400개의 화소데이타를 800개씩 구분하여 3회에 걸쳐 D-A변환기어래이(48)쪽으로 전송한다. 이를 위하여 디멀티플렉서어래이(46)는 각각 제1 내지 제3 제어라인(SL1 내지 SL3)으로부터의 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)를 입력하는 800개의 디멀티플렉서들(DMP1 내지 DMP800)로 구성된다. 이들 800개의 디멀티플렉서 각각은 제3도에서와 같이 1수평주기동안 순차적으로 1의 논리값을 가지게 되는 상기 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)에 의해 제2 래치어래이(44)의 3개의 래치들로부터의 3개의 화소데이타를 순차적으로 D-A변환기어래이(48)쪽으로 전송한다. 이를 위하여, 800개의 디멀티플렉서들(DMP1 내지 DMP800) 각각은 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)를 게이트쪽으로 분산입력하는 3조의 MOS 트랜지스터(MF)로 구성된다. 여기서, 3조의 MOS 트랜지스터(MF)는 화소데이타가 5비트인 경우 15개가 되어야 하나 편의상 3개로 표현되었다. 하나의 디멀티플렉서(DMP)에 포함된 3조의 MOS 트랜지스터(MF)의 소오스들은 제2 래치어래이(44)에 포함된 3개의 래치에 각각 접속되고 그리고 이들 3조의 MOS 트랜지스터(MF)의 드레인들은 화소데이타의 비트별로 공통 접속된다. 아울러, 하나의 멀티플렉서(DMP)에 포함된 3조의 MOS 트랜지스터(MF)는 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)에 의해 1수평기간동안 서로 순차적으로 턴-온되어 제2 래치어래이(44)의 해당 래치로부터의 화소데이타를 D-A변환기어래이(46) 쪽으로 전송한다. 그러면, D-A변환기어래이(48)은 디멀티플렉서어래이(46)로부터의 800개의 화소데이타 모두를 화소신호로 변환한다. 이를 위하여 D-A변환기어래이(48)는 감마보정부(50)로부터의 적어도 일정한 갯수(예를 들면, 5개)의 변환소스신호를 공통적으로 입력하는 800개의 D-A변환기로 구성된다. 이들 800개의 D-A변화기들 각각은 해당 디멀티플렉서(DMP)로부터의 화소데이타의 논리값에 따라 감마보정부(50)로부터의 일정 갯수의 변환소스신호를 전부 또는 일부를 선택적으로 가산함에 의해 화소데이타를 아날로그 화소신호로 변환한다. 결과적으로, 800개의 D-A변환기들 각각은 1수평주사기간에 3개의 화소데이타를 아날로그 화소신호로 변환하게 된다.The demultiplexer array 46 divides the 2400 pixel data from the second latch array 44 by 800 and transmits them to the D-A converter array 48 three times. To this end, the demultiplexer array 46 includes 800 demultiplexers DMP1 to DMP800 which input first to third switching control signals SWS1 to SWS3 from the first to third control lines SL1 to SL3, respectively. do. Each of these 800 demultiplexers has three of the second latch arrays 44 in response to the first to third switching control signals SWS1 to SWS3, which sequentially have a logic value of 1 during one horizontal period as shown in FIG. Three pixel data from the four latches are sequentially transferred to the DA converter array 48. To this end, each of the 800 demultiplexers DMP1 to DMP800 includes three sets of MOS transistors MF for distributing and inputting the first to third switching control signals SWS1 to SWS3 to the gate. Here, the three sets of MOS transistors MF should be 15 when the pixel data is 5 bits, but are represented as 3 for convenience. The sources of the three sets of MOS transistors MF included in one demultiplexer DMP are connected to the three latches included in the second latch array 44, respectively, and the drains of the three sets of MOS transistors MF are pixel data. The bits are commonly connected by. In addition, the three sets of MOS transistors MF included in one multiplexer DMP are sequentially turned on each other for one horizontal period by the first to third switching control signals SWS1 to SWS3, and thus the second latch array ( The pixel data from the corresponding latch of 44 is transferred to the DA converter gear 46. The D-A converter array 48 then converts all 800 pixel data from the demultiplexer array 46 into pixel signals. To this end, the D-A converter array 48 is composed of 800 D-A converters which commonly input at least a certain number (eg, five) conversion source signals from the gamma correction unit 50. Each of these 800 DA transformers analogizes the pixel data by selectively adding all or part of a certain number of conversion source signals from the gamma correction unit 50 according to the logic value of the pixel data from the corresponding demultiplexer (DMP). Convert to a pixel signal. As a result, each of the 800 D-A converters converts three pixel data into an analog pixel signal in one horizontal scanning period.

또한, 구동회로(40)는 D-A변환기어래이(48)와 액정표시판넬(30)의 데이타라인들(DL1 내지 DL2400)의 사이에 직렬 접속된 출력증폭기어래이(52)와 멀티플렉서어래이(54)를 구비한다. 출력증폭기어래이(52)은 D-A변환기어래이(48)로부터의 800개의 화소신호들을 일정한 증폭율로 증폭하고 그 증폭된 800개의 화소신호들을 멀티플렉서어래이(52)쪽으로 출력한다. 이를 위하여, 출력증폭기어래이(54)도 D-A변환기어래이(48)의 800개의 D-A변환기들에 분산접속된 800개의 출력증폭기들로 구성된다. 마지막으로, 멀티플렉서어래이(54)는 출력증폭기어래이(52)로부터의 800개의 증폭된 화소신호를 2400개의 데이타라인(DL1 내지 DL2400)에 800개의 데이타라인씩 3회에 거쳐 순차적으로 전송한다. 이를 위하여, 멀티플렉서어래이(54)는 각각 제1 내지 제3 제어라인(SL1 내지 SL3)로부터의 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)를 입력하는 800개의 멀티플렉서들(MP1 내지 MP800)로 구성된다. 이들 800개의 멀티플렉서(MP1 내지 MP800) 각각은 제3도에서와 같이 1수평주기동안 순차적으로 1의 논리값을 가지게되는 상기 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)에 의해 출력증폭기어래이(52)로부터의 화소신호를 3개의 데이타라인(DL)에 순차적으로 전송한다. 이를 위하여, 800개의 멀티플렉서들(MP1 내지 MP800) 각각은 제 1 내지 제3 절환제어신호(SWS1 내지 SWS3)를 게이트쪽으로 분산입력하는 3개의 MOS 트랜지스터(MS)로 구성된다. 하나의 멀티플렉서(MP)에 포함된 3개의 MOS 트랜지스터(MS)의 소오스들은 출력증폭기어래이(52)에 포함된 하나의 출력증폭기의 출력단자에 공통적으로 접속되고 이들의 드레인들은 3개의 데이타라인(DL)에 분산접속된다. 아울러, 하나의 멀티플렉서(MP)에 포함된 3개의 MOS 트랜지스터(MS)는 제1 내지 제3 절환제어신호(SWS1 내지 SWS3)에 의해 1수해 1수평기간동안 서로 순차적으로 턴-온되어 출력증폭기어래이(5)에 포함된 해당 출력증폭기로부터의 화소신호들을 3개의 데이타라인(DL)에 분산공급한다.The driving circuit 40 also includes an output amplifier array 52 and a multiplexer array 54 connected in series between the DA converter array 48 and the data lines DL1 to DL2400 of the liquid crystal display panel 30. do. The output amplifier array 52 amplifies the 800 pixel signals from the D-A converter array 48 at a constant amplification rate and outputs the amplified 800 pixel signals to the multiplexer array 52. To this end, the output amplifier array 54 also consists of 800 output amplifiers distributedly connected to the 800 D-A converters of the D-A converter array 48. Finally, the multiplexer array 54 sequentially transmits the 800 amplified pixel signals from the output amplifier array 52 to the 2400 data lines DL1 to DL2400 three times, each time 800 data lines. To this end, the multiplexer array 54 may be configured as 800 multiplexers MP1 to MP800 that input first to third switching control signals SWS1 to SWS3 from the first to third control lines SL1 to SL3, respectively. It is composed. Each of the 800 multiplexers MP1 to MP800 has an output amplifier array due to the first to third switching control signals SWS1 to SWS3 having a logic value of 1 sequentially during one horizontal period as shown in FIG. The pixel signal from 52 is sequentially transmitted to three data lines DL. To this end, each of the 800 multiplexers MP1 to MP800 is composed of three MOS transistors MS for distributing and inputting the first to third switching control signals SWS1 to SWS3 to the gate. The sources of the three MOS transistors MS included in one multiplexer MP are commonly connected to the output terminals of one output amplifier included in the output amplifier array 52 and the drains thereof are connected to three data lines DL. Is distributedly connected to In addition, the three MOS transistors MS included in one multiplexer MP are sequentially turned on each other for one horizontal period by the first to third switching control signals SWS1 to SWS3, so that the output amplifier array is turned on. The pixel signals from the corresponding output amplifier included in (5) are distributed to three data lines DL.

상술한 바와 같이, 본 발명에 따른 디지탈방식의 액정표시판넬 구동회로는 1라인분의 화소데이타를 일시적으로 보관하는 래치어래이와 화소데이타를 화소신호로 변환하는 D-A변환기어래이 사이에 디멀티플렉서어래이를 그리고 출력증폭기어래이와 액정표시판넬의 데이타라인들 사이에 멀티플렉서를 설치함으로써 D-A변환기와 출력증폭기의 갯수를 데이타라인의 수의 절반, 삼분의 일 또는 그 이하로 줄일 수 있다. 이에 따라, 본 발명에 따른 디지탈 방식의 액정표시판넬 구동회로는 회로구성을 간소화함을 물론 순간 전력소모량을 줄일 수 있다. 아울러, 본 발명에 따른 디지탈방식의 액정표시판넬 구동회로는 멀티플렉서를 액정표시판넬에 탑재시켜 액정표시판넬의 인출라인의 수량을 감소시킬 수 있다.As described above, the digital liquid crystal display panel driving circuit according to the present invention draws and outputs a demultiplexer array between a latch array for temporarily storing one line of pixel data and a DA converter array for converting pixel data to pixel signals. By installing a multiplexer between the amplifier array and the data lines of the liquid crystal panel, the number of DA converters and output amplifiers can be reduced to half, one third or less of the number of data lines. Accordingly, the digital liquid crystal display panel driving circuit according to the present invention can simplify the circuit configuration and reduce the instantaneous power consumption. In addition, the digital liquid crystal display panel driving circuit according to the present invention may reduce the number of lead-out lines of the liquid crystal display panel by mounting a multiplexer on the liquid crystal display panel.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정하여져야만 한다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

수직방향으로 배열된 m개의 화소들에 공통적으로 접속되고 수평방향으로 나란하게 배열된 n개의 데이타라인을 가지는 액정표시판넬과,A liquid crystal display panel having n data lines commonly connected to m pixels arranged in a vertical direction and arranged side by side in a horizontal direction; n개의 화소데이타들을 입력하여 일시적으로 보관하기 위한 기억소자어래이와,a storage element array for temporarily storing n pixel data and 상기 래치어래이로부터의 n개의 화소데이타를 k개씩 순차적으로 아날로그 화소신호로 변환하기 위한 디지탈-아날로그변환기어래이와,A digital-to-analog converter array for converting n pixel data from the latch array into analog pixel signals sequentially by k; 상기 기억소자어래이와 상기 디지탈-아날로그변환기어래이 사이에 접속되어 상기 기억소자어래이로부터의 상기 n개의 화소데이타중 k개의 화소데이타를 선택하고 그 선택된 k개의 화소데이타를 상기 디지탈-아날로그변환기어래이쪽으로 전달하기 위한 디멀티플렉서어래이와,Connected between the storage element array and the digital-analog converter array to select k pixel data of the n pixel data from the storage array and transfer the selected k pixel data to the digital-analog converter array. Demultiplexer array for 상기 디지탈-아날로그변환기어래이와 상기 n개의 데이타라인들 사이에 설치되어 상기 n개의 데이타라인중 k개의 데이타라인을 선택하고 상기 디지탈-아날로그변환기어래이로부터의 상기 k개의 화소신호를 그 선택된 k개의 데이타라인쪽으로 전달하기 위한 멀티플렉서어래이를 구비한 것을 특징으로 하는 디지탈방식의 액정표시판넬 구동회로.A k-data line provided between the digital-to-analog converter array and the n-data lines to select k data lines of the n-data lines and convert the k pixel signals from the digital-to-analog converter array to the selected k data lines. A digital liquid crystal display panel drive circuit comprising a multiplexer array for transmitting to a side. 제 1 항에 있어서,The method of claim 1, 상기 디지탈-아날로그변화기어래이와 상기 멀티플렉서어래이 사이에 설치되어 상기 디지탈-아날로그변환기어래이로부터 상기 멀티플렉서어래이쪽으로 전송되는 상기 k개의 화소신호를 완충하기 위한 출력증폭기어래이를 추가로 구비하는 것을 특징으로 하는 디지탈방식의 액정표시판넬 구동회로.And an output amplifier array provided between the digital-analog converter array and the multiplexer array to buffer the k pixel signals transmitted from the digital-analog converter array to the multiplexer array. LCD panel driving circuit. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 멀티플렉서어래이는 상기 액정표시판넬의 인출라인의 수를 최소화하도록 상기 액정표시판넬에 탑재된 것을 특징으로 하는 디지탈방식의 액정표시판넬 구동회로.And the multiplexer array is mounted on the liquid crystal display panel to minimize the number of lead-out lines of the liquid crystal display panel. 제 3 항에 있어서,The method of claim 3, wherein 상기 디멀티플렉서어래이에 포함된 k개의 디멀티플렉서와 상기 멀티플렉서어래이에 포함된 k개의 멀티플렉서가 MOS 트랜지스터들로 구성되어진 것을 특징으로 하는 디지탈방식의 액정표시판넬 구동회로.And k demultiplexers included in the demultiplexer array and k multiplexers included in the multiplexer array comprising MOS transistors.
KR1019970019142A 1997-05-17 1997-05-17 Driving circuit of liquid crystal display panel using digital method KR100229380B1 (en)

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KR1019970019142A KR100229380B1 (en) 1997-05-17 1997-05-17 Driving circuit of liquid crystal display panel using digital method
JP12838698A JPH10319924A (en) 1997-05-17 1998-05-12 Liquid crystal display panel driving circuit of digital system
FR9806174A FR2763416A1 (en) 1997-05-17 1998-05-15 ATTACK CIRCUIT FOR DIGITAL TYPE LIQUID CRYSTAL DISPLAY PANEL
GB9810599A GB2325329A (en) 1997-05-17 1998-05-15 Digital-type liquid crystal display panel driving circuit
DE1998121914 DE19821914A1 (en) 1997-05-17 1998-05-15 Digital driver circuit for a liquid crystal display panel

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100373349B1 (en) * 2000-12-30 2003-02-25 주식회사 하이닉스반도체 Low power Source driver for LCD
KR100388799B1 (en) * 2001-04-11 2003-06-25 (주)더블유에스디 Source driver for TFT-LCD
KR20040022692A (en) * 2002-09-09 2004-03-16 주식회사 엘리아테크 Apparatus For Selecting Data Signal Of OELD Panel
KR100441150B1 (en) * 2002-01-22 2004-07-19 하이 맥스 옵토일렉트로닉스 코포레이션 Apparatus and method for data signal scattering conversion
KR100460983B1 (en) * 2001-10-16 2004-12-09 삼성전자주식회사 Digital Image signal Receiver capable of selectively outputting/amplifying digital image signal to be displayed
KR100530659B1 (en) * 2003-11-21 2005-11-22 리디스 테크놀로지 인코포레이티드 Organic Electro Luminiscence Display Pixel Driving Circuit
KR100750317B1 (en) * 2001-03-30 2007-08-20 샤프 가부시키가이샤 Liquid crystal display device and driving circuit thereof
KR100892960B1 (en) * 2001-06-06 2009-04-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Image display device and driving method thereof
KR100894077B1 (en) * 2001-11-10 2009-04-21 엘지디스플레이 주식회사 Data driving apparatus for liquid crystal display
US7683876B2 (en) 2004-09-14 2010-03-23 Samsung Electronics Co., Ltd. Time division driving method and source driver for flat panel display
CN110728951A (en) * 2019-10-23 2020-01-24 广东晟合技术有限公司 Driving structure and method of OLED panel with multiplexing switch and panel

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430100B1 (en) * 1999-03-06 2004-05-03 엘지.필립스 엘시디 주식회사 Driving Method of Liquid Crystal Display
JP2001034237A (en) * 1999-07-21 2001-02-09 Fujitsu Ltd Liquid crystal display device
JP4780839B2 (en) * 2000-02-18 2011-09-28 株式会社半導体エネルギー研究所 Image display device drive circuit and electronic device
US7301520B2 (en) 2000-02-22 2007-11-27 Semiconductor Energy Laboratory Co., Ltd. Image display device and driver circuit therefor
KR100675320B1 (en) * 2000-12-29 2007-01-26 엘지.필립스 엘시디 주식회사 Method Of Driving Liquid Crystal Display
GB0105148D0 (en) * 2001-03-02 2001-04-18 Koninkl Philips Electronics Nv Active Matrix Display Device
GB0105147D0 (en) 2001-03-02 2001-04-18 Koninkl Philips Electronics Nv Active matrix display device
US6630921B2 (en) * 2001-03-20 2003-10-07 Koninklijke Philips Electronics N.V. Column driving circuit and method for driving pixels in a column row matrix
JP2002311920A (en) * 2001-04-19 2002-10-25 Matsushita Electric Ind Co Ltd Liquid crystal display device, picture display application equipment and portable information terminal equipment
KR100815898B1 (en) * 2001-10-13 2008-03-21 엘지.필립스 엘시디 주식회사 Mehtod and apparatus for driving data of liquid crystal display
KR100815897B1 (en) * 2001-10-13 2008-03-21 엘지.필립스 엘시디 주식회사 Mehtod and apparatus for driving data of liquid crystal display
KR100864917B1 (en) 2001-11-03 2008-10-22 엘지디스플레이 주식회사 Mehtod and apparatus for driving data of liquid crystal display
US7006072B2 (en) 2001-11-10 2006-02-28 Lg.Philips Lcd Co., Ltd. Apparatus and method for data-driving liquid crystal display
JP3982249B2 (en) * 2001-12-11 2007-09-26 株式会社日立製作所 Display device
KR100840675B1 (en) * 2002-01-14 2008-06-24 엘지디스플레이 주식회사 Mehtod and apparatus for driving data of liquid crystal display
JP3758039B2 (en) 2002-06-10 2006-03-22 セイコーエプソン株式会社 Driving circuit and electro-optical device
JP2004037498A (en) * 2002-06-28 2004-02-05 Seiko Epson Corp Driving circuit for optoelectronic device, optoelectronic device, electronic apparatus, and method for driving optoelectronic device
JP2004053715A (en) * 2002-07-17 2004-02-19 Sanyo Electric Co Ltd Display device and its gamma correction method
JP3685176B2 (en) 2002-11-21 2005-08-17 セイコーエプソン株式会社 Driving circuit, electro-optical device, and driving method
JP4363881B2 (en) * 2003-04-10 2009-11-11 東芝モバイルディスプレイ株式会社 Liquid crystal display
US7889157B2 (en) 2003-12-30 2011-02-15 Lg Display Co., Ltd. Electro-luminescence display device and driving apparatus thereof
JP4400403B2 (en) 2004-10-06 2010-01-20 セイコーエプソン株式会社 Power supply circuit, display driver, electro-optical device, and electronic device
JP2006154545A (en) * 2004-11-30 2006-06-15 Sanyo Electric Co Ltd Liquid crystal display device
JP2006235357A (en) * 2005-02-25 2006-09-07 Koninkl Philips Electronics Nv Column electrode driving circuit and display device using the same
JP2006292807A (en) * 2005-04-06 2006-10-26 Renesas Technology Corp Semiconductor integrated circuit for liquid crystal display driving
JP4584131B2 (en) * 2005-04-18 2010-11-17 ルネサスエレクトロニクス株式会社 Liquid crystal display device and driving circuit thereof
KR100707634B1 (en) 2005-04-28 2007-04-12 한양대학교 산학협력단 Data Driving Circuit and Driving Method of Light Emitting Display Using the same
JP4710422B2 (en) * 2005-06-03 2011-06-29 カシオ計算機株式会社 Display driving device and display device
US20070035482A1 (en) * 2005-08-11 2007-02-15 Yu-Wen Chiou Driving circuits and methods for driving display cells
KR100662985B1 (en) 2005-10-25 2006-12-28 삼성에스디아이 주식회사 Data driving circuit and driving method of organic light emitting display using the same
JP4909572B2 (en) * 2005-11-11 2012-04-04 東芝モバイルディスプレイ株式会社 Liquid crystal display
US7250888B2 (en) * 2005-11-17 2007-07-31 Toppoly Optoelectronics Corp. Systems and methods for providing driving voltages to a display panel
JP2007225873A (en) * 2006-02-23 2007-09-06 Hitachi Displays Ltd Image display device
JP5403860B2 (en) 2006-10-10 2014-01-29 株式会社ジャパンディスプレイ Color liquid crystal display device
JP4367509B2 (en) * 2007-03-14 2009-11-18 エプソンイメージングデバイス株式会社 Electro-optical device, drive circuit, and electronic device
CN101976542B (en) * 2010-11-10 2012-07-04 友达光电股份有限公司 Pixel driving circuit
JP5642230B2 (en) * 2013-05-13 2014-12-17 株式会社ジャパンディスプレイ Liquid crystal display
CN104766564B (en) 2015-04-24 2017-03-15 京东方科技集团股份有限公司 A kind of display floater, its driving method and display device
US11283436B2 (en) * 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910003142B1 (en) * 1986-10-21 1991-05-20 가시오 게이상기 가부시기가이샤 Image display apparatus
US5170158A (en) * 1989-06-30 1992-12-08 Kabushiki Kaisha Toshiba Display apparatus
US5510807A (en) * 1993-01-05 1996-04-23 Yuen Foong Yu H.K. Co., Ltd. Data driver circuit and associated method for use with scanned LCD video display
US5510748A (en) * 1994-01-18 1996-04-23 Vivid Semiconductor, Inc. Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100373349B1 (en) * 2000-12-30 2003-02-25 주식회사 하이닉스반도체 Low power Source driver for LCD
KR100750317B1 (en) * 2001-03-30 2007-08-20 샤프 가부시키가이샤 Liquid crystal display device and driving circuit thereof
KR100388799B1 (en) * 2001-04-11 2003-06-25 (주)더블유에스디 Source driver for TFT-LCD
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US7683876B2 (en) 2004-09-14 2010-03-23 Samsung Electronics Co., Ltd. Time division driving method and source driver for flat panel display
CN110728951A (en) * 2019-10-23 2020-01-24 广东晟合技术有限公司 Driving structure and method of OLED panel with multiplexing switch and panel

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GB2325329A (en) 1998-11-18
JPH10319924A (en) 1998-12-04

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