KR19980082502A - Device isolation method of semiconductor device - Google Patents

Abstract

The present invention relates to a device isolation method for a semiconductor device, comprising: forming a mask layer exposing a predetermined portion on a semiconductor substrate; and forming a trench in the exposed portion of the semiconductor substrate using the mask layer as an etching mask. Forming a liner on the inner surface of the trench and forming a device isolation insulating film filling the trench on the liner; oxidizing the liner formed on the upper side of the trench; and removing the mask layer. Equipped. Therefore, the device isolation insulating film in the trench can prevent an increase in volume, thereby reducing the occurrence of stress, and preventing the formation of a space on the upper side of the trench. In addition, since the trench corners of the semiconductor substrate are rounded, the concentration of the electric field can be prevented.

Description

Device isolation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method capable of preventing an active region from being reduced due to an increase in device isolation region by using a trench.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

In general, semiconductor devices have isolated devices by a local oxide of silicon (LOCOS) method. The LOCOS method is a device isolation region by forming and oxidizing a pad oxide film between the nitride film and the semiconductor substrate in order to solve the stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed. The field oxide film is not only grown in the vertical direction of the semiconductor substrate but also has an oxide (Oxidant: O ₂ ) is also diffused in the horizontal direction along the pad oxide film is characterized in that it is grown under the pattern edge of the nitride film (edage).

The phenomenon of the field oxide film encroaching on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This buzz beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized in order to reduce the reduction in the size of the active area.

In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced, but when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate is increased and the signal transmission speed is lowered. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.

Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the stress buffer pad oxide film is reduced, and the PBLOCOS (Poly Si Buffered LOCOS) in which a polysilicon layer is interposed between the semiconductor substrate and the nitride film is used as the nitride film. Shielded Interface LOCOS (SILO), and Recessed Oxide LOCOS technologies that form field oxide films in semiconductor substrates.

However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.

Therefore, a buried oxide (BOX) type trench isolation technology has been developed that can overcome the problems of various device isolation techniques. BOX type device isolation technology A trench is formed in a semiconductor substrate and an oxide film is buried by chemical vapor deposition (hereinafter referred to as CVD). Therefore, it is possible to prevent loss of the active region due to the occurrence of a buzz beak, and a flat surface can be obtained by embedding and etching back the oxide film in the trench.

1 (A) to (D) are process diagrams showing a device isolation method according to the prior art.

Referring to FIG. 1A, a first mask layer 13 is formed on a semiconductor substrate 11 by thermal oxidation, and silicon nitride is deposited on the first mask layer 13 by CVD. 2 mask layer 15 is formed. Certain portions of the first and second mask layers 13 and 15 are selectively removed to expose the semiconductor substrate 11 by photolithography to define the device isolation region and the active region. The trench 17 is formed by dry etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth using the first and second mask layers 13 and 15 as masks.

Referring to FIG. 1B, the first and second mask layers 13 and 15 are removed. Then, the first, second and third insulating films 19, 21 and 23 are sequentially formed on the surface of the semiconductor substrate 11 including the trench 17 inside. In the above, the first insulating film 19 is formed by thermally oxidizing the semiconductor substrate 11 including the inside of the trench 17, and the second insulating film 21 is formed by depositing silicon nitride by the CVD method, and the third The insulating film 23 is formed by depositing silicon oxide by the CVD method.

Referring to FIG. 1C, polycrystalline silicon or amorphous silicon is deposited on the third insulating layer 23 to fill the trench 17. In addition, polysilicon or amorphous silicon is deposited on the outside so as to remain only inside the trench 17 by chemical mechanical polishing (hereinafter referred to as CMP) method to form a filler 25. When the filler 25 is formed by CMP of the polysilicon or the amorphous silicon, the third insulating film 23 outside the trench 17 is removed to expose the second insulating film 21. Then, the upper portion of the filler 25 is thermally oxidized to form an element isolation insulating film 27. At this time, the second insulating film 21 prevents the oxidation of the first insulating film 19 from proceeding.

Referring to FIG. 1D, the second and first insulating layers 21 and 19 are sequentially removed by the CMP method to expose the semiconductor substrate 11. Since the etching selectivity of the second insulating film 21 and the first insulating film 19 is different from the above, the second insulating film 21 is overetched to completely remove the first insulating film 19. At this time, the portion higher than the semiconductor substrate 11 of the element isolation insulating film 27 is also removed.

However, the device isolation method of the conventional semiconductor device described above has a problem in that stress is generated due to an increase in volume when oxidizing a filler filling a trench. In addition, when the second and first insulating layers formed outside the trench are removed, the second insulating layer on the side of the trench is also removed by the transient etching to completely remove the second insulating layer, so that a space is formed and the conductive material remains during the gate formation. Since there is a problem that the reliability of the device is lowered. In addition, the semiconductor substrate is sharply formed by the trench, so that an electric field is concentrated.

Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device that can reduce the occurrence of stress.

Another object of the present invention is to provide a device isolation method of a semiconductor device which can prevent the formation of a space on the upper side of the trench so that the conductive material does not remain when forming the gate, thereby preventing the reliability of the device from being lowered.

Another object of the present invention is to provide a device isolation method for a semiconductor device which can prevent the electric field from being concentrated at the corners of the trenches of the semiconductor substrate.

The device isolation method of the semiconductor device according to the present invention for achieving the above object is a step of forming a mask layer for exposing a predetermined portion on the semiconductor substrate, and using the mask layer as an etching mask exposed portion of the semiconductor substrate Forming a trench in the trench, forming a liner on the inner surface of the trench and forming a device isolation insulating film filling the trench on the liner, oxidizing the liner formed on the upper side of the trench, and the mask layer It comprises a step of removing.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 (A) to (D) are process drawings showing a device isolation method of a semiconductor device according to the prior art.

2 (A) to (D) are process drawings showing a device isolation method of a semiconductor device according to one embodiment of the present invention.

3A to 3D are process drawings showing a device isolation method for a semiconductor device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

31 semiconductor substrate 33 first mask layer

35: second mask layer 36: third mask layer

37: trench 39: liner

41: device isolation insulating film

2 (A) to (D) is a process diagram showing a device isolation method according to an embodiment of the present invention.

Referring to FIG. 2A, a first mask layer 33 is formed on the semiconductor substrate 31 by thermal oxidation, and silicon nitride is deposited on the first mask layer 33 by CVD. 2 mask layer 35 is formed. Predetermined portions of the first and second mask layers 33 and 35 are selectively removed to expose the semiconductor substrate 31 by photolithography to define the device isolation region and the active region. The trench 37 is formed by dry etching the exposed device isolation region of the semiconductor substrate 31 to a predetermined depth using the first and second mask layers 33 and 35 as masks.

Referring to FIG. 2B, polycrystalline silicon or amorphous silicon is deposited on the inside of the trench 37 and the surface of the second mask layer 35 by CVD to form a liner 39. Then, silicon oxide is deposited on the liner 39 to fill the trench 37 by CVD and then removed to expose the second mask layer 35 by the CMP method to form the device isolation insulating film 41.

Referring to FIG. 2C, the liner 39 formed on the upper side of the trench 37 including the side surfaces of the first and second mask layers 33 and 35 is oxidized. At this time, a bird's beak generated due to an increase in volume by the oxidation of the liner 39 rounds the corners of the semiconductor substrate 31 by the trench 37 to prevent the electric field from being concentrated. In the above, since the silicon oxide is filled in the trench 37 to oxidize the thinner liner 39 formed on the upper side of the trench 37 in the state where the device isolation insulating film 41 is formed, the increase in volume does not increase so that the stress is increased. Is suppressed.

Referring to FIG. 2D, the second and first mask layers 35 and 33 are sequentially removed by the CMP method to expose the semiconductor substrate 31. The first mask layer 33 and the isolation layer 41 made of silicon oxide have different etching selectivity from the second mask layer 35 made of silicon nitride. Therefore, even when overetching is performed to completely remove the second mask layer 35, a space is formed on the side of the trench 37 due to a slow edible speed of the first mask layer 33 and the device isolation insulating film 41. prevent.

3A to 3D are process diagrams showing a device isolation method of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 3A, a first mask layer 33 is formed on the semiconductor substrate 31 by thermal oxidation, and silicon nitride and polycrystalline silicon or silicon nitride are formed on the first mask layer 33 by CVD. Amorphous silicon is sequentially deposited to form second and third mask layers 35 and 36. Predetermined portions of the first, second and third mask layers 33, 35 and 36 are selectively removed to expose the semiconductor substrate 31 by photolithography to define the device isolation region and the active region. Then, the trench 37 is formed by dry etching the exposed device isolation region of the semiconductor substrate 31 to a predetermined depth using the first, second and third mask layers 33, 35 and 36 as a mask. do.

Referring to FIG. 3B, polycrystalline silicon or amorphous silicon is deposited on the inside of the trench 37 and the surface of the third mask layer 36 by CVD to form a liner 39. Then, silicon oxide is deposited on the liner 39 to fill the trench 37 by CVD and then removed to expose the second mask layer 35 by the CMP method to form the device isolation insulating film 41.

Referring to FIG. 3C, the liner 39 formed on the upper side of the trench 37 including the side surfaces of the first, second, and third mask layers 33, 35, 36 is oxidized. At this time, the bird's beak generated by the increase in volume by the oxidation of the liner 39 makes the semiconductor substrate 31 round the corners of the trench 37 to prevent the electric field from being concentrated. In the above, since the silicon oxide is filled in the trench 37 to oxidize the thinner liner 39 formed on the upper side of the trench 37 in the state where the device isolation insulating film 41 is formed, the increase in volume does not increase so that the stress is increased. Is suppressed.

Referring to FIG. 3D, the third, second, and first mask layers 36, 35, 33 are sequentially removed by the CMP method to expose the semiconductor substrate 31. At this time, the first mask layer 3 made of silicon oxide and the device isolation insulating film 41 are etched more than the third mask layer 36 made of polysilicon or amorphous silicon and the second mask layer 35 made of silicon nitride. Try to slow down. Therefore, the element isolation insulating film 41 is formed to be higher than the surface of the semiconductor substrate 31 to prevent dishing.

Therefore, the present invention can reduce the occurrence of stress by preventing the device isolation insulating film in the trench from increasing in volume, and prevents the formation of a space on the upper side of the trench, so that the conductive material does not remain during the gate formation, thereby ensuring reliability of the device. There is an advantage that can be prevented from being lowered. In addition, since the trench corners of the semiconductor substrate are rounded, there is an advantage that can prevent the electric field is concentrated.

Claims (4)

Forming a mask layer exposing a predetermined portion on the semiconductor substrate; Forming a trench in the exposed portion of the semiconductor substrate using the mask layer as an etching mask; Forming a liner on the inner surface of the trench and forming a device isolation insulating film filling the trench on the liner; Oxidizing a liner formed on the upper side of the trench; A device isolation method for a semiconductor device, comprising the step of removing the mask layer. The method according to claim 1, And forming the mask layer as a first mask layer made of a thermal oxide film and a second mask layer made of silicon nitride. The method according to claim 2, And forming a third mask layer made of polycrystalline silicon or amorphous silicon on the second mask layer. The method according to claim 1, A method for isolating a semiconductor device, wherein the liner is formed of polycrystalline silicon or amorphous silicon.