KR19980063014A - Synchronous method of synchronous stream cipher and its apparatus - Google Patents

Abstract

The present invention relates to a synchronization method and apparatus for synchronous stream cryptography in which received data can be normally decoded by suppressing consecutive zeroes in received data by more than a predetermined number of bits to accurately recover a received clock. Generally, in order to encrypt a digital data signal, a binary random number sequence having a uniform probability distribution is mixed with digital data, and the output encrypted data has a randomness characteristic in which 1's and 0's are uniformly distributed. However, if the above encryption scheme is applied to the T1-PCM line, excessive continuous 0s may appear in the received data, which may lead to unstable reproduction of the received clock. Therefore, do. Therefore, according to the present invention, a plain text block is mixed with a random number sequence block, and when all the bits of the mixed block and all bits of the plain text block are not 0, the mixed block is transmitted as a ciphertext block, If all the bits of the plaintext block are 0, the three plaintext blocks corresponding to the mixed block are transmitted instead of the three mixed blocks including the before and after blocks, Block is transmitted as a ciphertext block, the received ciphertext block is received and mixed with a random number sequence block, and if all the bits of the ciphertext block and all bits of the ciphertext block are not 0, If all the bits of the mixed block are 0, the ciphertext block corresponding to the mixed block is replaced with the deciphered block When all the bits of the ciphertext block are 0, three ciphertext blocks corresponding to the three mixed blocks including the before and after blocks are output to the decryption block, so that all bits of the plaintext block are 0 Quot; 0 " can be suppressed from continuing for more than a predetermined number of bits even after the encryption is performed.

Description

Synchronous method of synchronous stream cipher and its apparatus

FIG. 1 is a conventional synchronous stream cipher transmission and reception system.

FIG. 2 is a schematic diagram of a synchronous stream cipher transmission and reception system according to the present invention; FIG.

FIG. 3 is a block diagram of a synchronous stream cryptographic apparatus according to the present invention; FIG.

Description of the Related Art [0002]

1: transmitted random number sequence generator 2, 4: adder

3: Receiving Random Number Generator 5,6: 0 Detection and Replacement Unit

501, 502, 509, 510, 601, 602, 609, 610:

503, 504, 603, and 604:

505, 605: 0 detection /

506, 507, 606, 607:

508, 511, 608, 611: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous stream cipher method for encrypting and transmitting a digital data signal, and more particularly, To a synchronous stream cipher method and apparatus for synchronizing stream cipher.

In digital communication, the performance depends on how accurate the clock signal can be recovered from the receiver. Generally, the clock signal is recovered from the clock information according to the data transition using a phase locked loop do. However, when there is no transition among the transmission data, that is, when 0 or 1 is continuous, clock recovery can not be performed on the receiving side. Therefore, in the PCM method, not only a special restriction is applied so that the number of zeros can be suppressed by 15 or more at the time of coding at the time of speech coding, but also the AMI (Alternate Marked Inversion) line line) coding, it can be said that countermeasures for perfect clock recovery are taken.

FIG. 1 is a block diagram of a conventional synchronous stream cipher transmission and reception system. As shown in FIG. 1, a random number sequence data generated with a uniform probability distribution from a transmission random number sequence generator 1 is added to digital plaintext data through a summer 2 The random number sequence data generated by the received random number sequence generator 3 with a uniform probability distribution is added to the cipher text data thus received and transmitted through the summer 4, As shown in FIG. Therefore, the transmitted ciphertext data has a randomness characteristic in which 1 and 0 are uniformly distributed. When this encryption scheme is applied to the T1-PCM line, the probability that a K-bit continuous 0 phenomenon appears in the ciphertext data output is 2- ^K , and accordingly, when 0 of the received data is continuous, clock regeneration becomes unstable There was a problem. For example, since the PCM repeater is designed to withstand up to 15 consecutive zeroes, a cryptosystem capable of suppressing zero or more than 15 consecutive ciphers after the ciphertext is required for stable clock regeneration.

Therefore, it is an object of the present invention to provide a synchronous decoding apparatus and a synchronous decoding method, which are capable of correctly recovering a received clock and correctly decoding received data by never allowing continuous 0s of K bits or more in a ciphertext data block, A method of synchronizing stream ciphers, and a device therefor.

It is an object of the present invention to provide a decoding apparatus and a decoding method and a decoding method thereof, in which a transmission random number sequence block is mixed with a plaintext block, and it is detected that all bits of the mixed block are 0 and all bits of the plaintext block are 0, If all the bits of the mixed block and all bits of the plain text block are not 0, the mixed block is transmitted as a ciphertext block, and when all bits of the mixed block are 0, the plaintext block corresponding to the mixed block is transmitted as a ciphertext block , And when all the bits of the plaintext block are 0, three plaintext blocks including the before and after blocks of the plaintext block are replaced with a ciphertext block, and the received random number sequence block is transmitted to the received ciphertext block. Detects whether all bits of the mixed block are 0 and detects whether all bits of the received ciphertext block are 0, And outputs the mixed block to the decryption block if all the bits of the entry and the mixed block and all bits of the ciphertext block are not equal to 0 and if all bits of the mixed block are 0, The ciphertext block is replaced with a decryption block, and when all the bits of the ciphertext block are 0, three ciphertext blocks including the before and after blocks of the ciphertext block are replaced with a decryption block, The following will describe in detail with reference to one drawing.

FIG. 2 is a block diagram of a synchronous stream cipher transmission and reception system according to the present invention. As shown in FIG. 2, a summator 2 for mixing a plaintext block with a random number generator of the transmission random number generator 1, And detects whether all the bits of the mixed block are 0, and detects whether all bits of the plain block are 0, so that all bits of the mixed block and all bits of the plain block Is not 0, normally transmits the mixed block as a ciphertext block, and when all bits of the mixed block are 0, the plain text block corresponding to the mixed block is replaced with a ciphertext block and transmitted, If all the bits of the plaintext block are 0, instead of the mixed block, three plaintext blocks including the before and after blocks of the plaintext block are replaced with the ciphertext block, (4) for mixing the transmitted and received ciphertext block with a random number sequence block of the received random number sequence generator (3), and a mixing block of the adder (4) and the received ciphertext block Detects whether all bits of the mixed block are 0, and detects whether all bits of the ciphertext block are 0. If all bits of the ciphertext block and all bits of the ciphertext block are not 0, And outputs the decrypted block to the decryption block. If all the bits of the decryption block are 0, the decryption block substitutes the decrypted block corresponding to the decrypted block instead of the mixed block, And a zero detection and substitution unit 6 for replacing the ciphertext block with the deciphered text block and outputting the ciphertext block including the preceding and succeeding blocks of the ciphertext block instead of the mixed block.

For the sake of simplicity, n-bit plaintext blocks, random-numbered blocks, and ciphertext blocks are set as follows, where block size selection is n = [(k + 1) / 2] and [X] do.

The i-th plaintext block P _i : (P _in , P _{in + 1} , ....., P _{in + n-1} )

the i-th random number sequence block _{K i: (K in, K} in + 1, ....., K in + n-1)

i th ciphertext block _{C i: (C in, C} in + 1, ....., C in + n-1)

i < th decrypted text block _{Q i: (Q in, Q} in + 1, ....., Q in + n-1)

Vector 0: (0, 0, ....., 0)

Vector 1: (0, 0, ....., 1)

FIG. 3 is a block diagram of a synchronous stream cryptographic apparatus according to the present invention. As shown in FIG. 3 (a), a summer 2 for mixing a plaintext block P _i with a random number sequence K _i , A shift register 501 for storing and outputting the plaintext block P _i in synchronism with the system clock CK and a mix block P _i A shift register 502 for storing and outputting K _i in synchronization with the system clock CK and a 0 detection unit 503 for detecting whether all the bits of the plaintext block P _i of the shift register 501 are 0, mixing block of said shift register (502) (P _i K _i) all the bits are 0 detector 504 for detecting a zero lice, 2 keep the output zero detection holding unit (505 to over the period of the system clock (CK) the zero detecting signal of the zero detector 503) and , The zero detection output signal of the zero detection holding unit 505 is supplied to the system clock ( A detection output section 506 for receiving and outputting the zero detection signal of the zero detection section 504 synchronously with the system clock (507) of the shift register 502 only in a state in which no 0 detection signal is output in the detection output units 506 and 507, _i K _i) selecting and outputting to and the control of the previous plaintext and a multiplexer 508 for selecting and outputting the plaintext block (P _i) of the shift register 501, the output from the shift register 501 A shift register 509 for storing and outputting the block P _i-1 in synchronization with the system clock CK and a shift register 509 for selectively outputting the block A selectively output from the multiplexer 508 to the system clock CK (P _i-1 ) of the shift register 509 only when the detection output unit 506 outputs the zero detection signal, and outputs the ciphertext block C otherwise transmitting the _i-1) is constitutes a transmitting end to a multiplexer 511 to be transmitted to the ciphertext block (C _i-1) by selecting a block (a) of the shift register 510. As shown in (b) of FIG. 3, the adder 4 for mixing and outputting the ciphertext block C _i-1 with the random number sequence block K _i , the ciphertext block C _i- And the mixing block C _i ( _i ) of the summer 4 (C _i ), (C _i ) of the shift registers 601 and 602, and shift registers 601 and 602 for storing and outputting the shift clocks K _i and K _i in synchronization with the system clock CK. K _i ) 0 detection units 603 and 604 for detecting whether all the bits are 0 and a 0 detection and holding unit 603 for maintaining 0 detection signals of the 0 detection unit 603 for two periods of the system clock CK, A 0 detection output signal of the 0 detection and holding unit 605 and a 0 detection signal of the 0 detection unit 604 to the system clock ( 607, 607, 607, 607, 607, 607, 607, 607, 606, 607, The mixing block C _i K _i) For the other and selecting and outputting a previously encrypted text block that is output from the multiplexer 608 and the shift register 601 for selecting and outputting the ciphertext block (C _i) of said shift register (601) (C _i-1) and the multiplexer 608, shift register 609, which respectively store the output to match the synchronization of the block (a) is selected output to the system clock (CK) from (610), and the detection output (C _i-1 ) of the shift register 609 only in a state where a 0 detection signal is output from the shift register 606 and outputs the selected ciphertext block C _i-1 to the decrypted statement block Q _i-1 . Otherwise, The multiplexer 611 selects the block A of the shift register 610 and outputs the block A to the decoded block Q _i-1 .

The zero detection and hold unit 505 includes a delay unit 505a for delaying the zero detection signal of the zero detection unit 503 for one cycle of the system clock CK and a delay unit 505b for delaying the output signal of the zero detection unit 503 and the delay And the zero detection holding unit 605 is constituted by the delay unit 605a and the output terminal of the delay unit 605a as well as the zero detection holding unit 505, And 0 detectors 503, 504, 603, and 604 correspond to exclusive OR gates for bit-by-bit exclusive OR operation, respectively, in the summers 2 and 4, The AND gate that receives and combines the blocks of the shift registers 501, 502, 602, and 602 or the blocks of the shift registers 501, 502, 601, And the detection output units 506, 507, 606, and 607 are D flip-flops.

The method and effect of the present invention will be described in detail as follows.

Any n-bit plaintext block (P _i) is input to a summer (2), is mixed with the transmitted random number sequence generator with a random n-bit input from (1) random number sequence block (K _i), the mixing operation the mixture Blocks _Pi K _i) is stored and the output is stored in the system clock (CK), the shift register 502 to match the synchronization with, and wherein the plaintext block (P _i) is the system clock (CK), the shift register 501 to match the synchronization with the And the previous plaintext block _Pi-1 output from the shift register 501 is stored in the shift register 509 in synchronism with the system clock CK and is output to the multiplexer 508. [ Is also stored in the shift register 510 in synchronization with the system clock CK and output. And, all the bits of the plaintext block (P _i) time is saved in the transfer register 501, are input to the plaintext block (P _i) is zero detector 503, and the plaintext block (P _i) as described above is 0, a 0 detection signal of 1 is output. That is, when all the bits of the plaintext block P _i are 0, all of the signals are inverted and received, and a 0 detection signal of 1 is output. Similarly, the mixing block _Pi K _i ) is stored in the shift register 502, the mixing block P _i K _i ) is input to the zero detection unit 504, and the mixture block P _i When all the bits of K _i are 0, a high-level 1 is output as a zero detection signal. On the other hand, as described above, when the zero detection unit 503 outputs the zero detection signal 1, the zero detection signal is maintained in the zero detection and hold unit 505 for two periods of the system clock CK. That is, the zero detection signal 1 is applied to one input terminal of the OR gate 505b and is delayed for one period of the system clock CK through the delay circuit 505a to be supplied to the other input terminal of the O gate 505b The zero detection signal 1 is output from the gate 505b during two cycles of the system clock CK.

As described above, the zero detection signal output from the zero detection / hold unit 505 and the zero detection unit 504 is the system clock The selection control terminals S ₁ and S _{0 of} the multiplexer 508 and the selection control terminals S of the multiplexer 511 are inputted to the detection output units 506 and 507 in synchronization with the selection control terminals S ₁ ) and (S ₀ ). Therefore, the multiplexer 508 selects the input terminal I _{0 thereof in the} state where no 0 detection signal is output from the detection output units 506 and 507 as described above, the mixing block (P _i K _i ) to the shift register 510 and in any other case any one of its commonly connected input terminals I ₀ -I ₁ is selected and the plain text block P _i of the shift register 501 is selected, And the multiplexer 511 outputs either of the commonly connected input terminals I ₀ and I ₁ in a state where the zero detection signal is not output from the detection output section 506 to the shift register 510 And outputs the block A of the shift register 510 to the cipher block C _i-1 . When the detection signal output from the detection output unit 506 is 0, the input terminal I ₂ And I ₃ to transmit the previous plaintext block P _i-1 of the shift register 509 to the ciphertext block C _i-1 .

Therefore, in a state where the 0 detection signals are not output from the 0 detection units 503 and 504, the previous block A stored in the shift register 510 is transmitted to the ciphertext block C via the multiplexer 511 _i-1 ) of the shift register 502, and the mixed block _Pi K _i is stored in the shift register 510 through the multiplexer 508.

In the state in which the 0 detection signal is output only from the 0 detection unit 504, the previous block A stored in the shift register 510 is output to the cipher text block C _i-1 through the multiplexer 511, The plaintext block P _i of the shift register 501 is stored in the shift register 510 via the multiplexer 508 so that the plaintext block P _i stored in the shift register 510 at the system clock CK thereafter Lt; _{RTI ID = 0.0} > (Pi) &_lt; / _{RTI &} (C _i ) through the multiplexer 511 in place of K _i .

In the state where the 0 detection unit 503 outputs the 0 detection signal, the previous plaintext block P _i-1 stored in the shift register 509 is output to the multiplexer 511 ) is output as the ciphertext block (C _i-1) through, this as well as the plaintext block (P _i) of the shift register 501 is stored in the transfer register 509, after the plaintext block from the system clock (CK) (P _i) is output as the ciphertext block (C _i) through multiplexer 511, and, where the plaintext block (P _i-1) output from the shift register 501 is a multiplexer 508 And the plaintext block P _i-1 of the shift register 510 is output to the cipher text block C _i-1 at the system clock CK.

The ciphertext block C _i transmitted and received as described above is input to the summer 4 and mixed with the random number sequence block K _i input from the received random number sequence generator 3, C _i ) and the mixed-mixed block C _{i 1} and stored in the shift registers 601 and 602 in synchronization with the system clock CK and output to the previous ciphertext block P _i-1 output from the shift register 601, The block A that is selectively output from the multiplexer 508 is also shifted in synchronization with the system clock CK in synchronization with the system clock CK and stored in the shift register 609 Is stored in the register 510 and output. The 0 detection units 603 and 604, the 0 detection and holding unit 605 and the detection output units 606 and 607 correspond to the 0 detection units 503 and 504, (505) and the detection output units (606) and (607).

Therefore, in a state in which 0 detection signals are not output from the 0 detection units 603 and 604, the block A stored in the shift register 610 is decoded in the decoded block _Qi-1 through the multiplexer 611, And the mixed block C _i output from the shift register 602, K _i is stored in the shift register 610 via the multiplexer 608.

In the state in which the 0 detection signal is output only in the 0 detection unit 604, the previous block A stored in the shift register 611 is output to the decipher block _Qi-1 through the multiplexer 611, The ciphertext block C _i stored in the shift register 601 is stored in the shift register 611 via the multiplexer 608 so that the ciphertext block C _i is multiplexed on the system clock CK, And output to the decipher block Q _i through the lexer 611.

In the state in which the 0 detection unit 603 outputs the 0 detection signal, the previous ciphertext block C _i-1 stored in the shift register 609 is output to the multiplexer 611 ) is output as decrypted text block (Q _i-1) through, and wherein the ciphertext block (C _i) of the shift register 601 is stored in the transfer register 609, the cipher text in a later system clock (CK) the blocks (C _i), the decrypted text block (Q _i) is output to, and wherein the ciphertext block to be output from the shift register _{(601) (C i-1} ) is a shift register 611 through a multiplexer 608 The ciphertext block C _i-1 of the shift register 611 is output to the decipher block Q _i-1 through the multiplexer 611 in the system clock CK.

As a result, k-bit consecutive zeros are also suppressed in the cascade block output of the sender, assuming that k bits (k = 2n-1 or k = 2n) consecutive zeros in any n-bit plaintext block are suppressed, Is completely decoded as follows.

Without block replacement (P _i ≠ 0 and P _i K _i ≠ 0), P _i ≠ 0 and P _i Since K _i ≠ 0, C _i-1 = P _i-1 K _i-1 and C _i = P _i K _i is transmitted, and C _i ≠ 0 and C _i Since K _i ? 0, Q _i-1 = C _i-1 K _i-1 = P _i-1 K _i-1 K _i-1 = P _i-1 and Q _i = C _i K _i = P _i K _i K _i = P _i .

If there is only one block replacement (P _i ? 0 and P _i K _i = 0), P _i ≠ 0 and P _i Since K _i = 0, C _i-1 = P _i-1 K _i-1 and C _i = P _i are transmitted, and at the receiving end, C _i ≠ 0 and C _i Since K _i = 0, Q _i-1 = C _i-1 K _i-1 = P _i-1 K _i-1 = K _i-1 K _i-1 P _i-1 and Q _i = C _i = P _i .

Also, if there are 3 block replacements (P _i = 0 and P _i Since in a transmitting end K _i is independent) P _i = 0, so _{C i-1 = P i-} 1, C i = P i, C i + 1 = P i + 1 is used for transmitting, C _i = 0 at the receiving end, Q ₁ = C _i-1 = P _i-1 , Q _i = C _i = P _i , and Q _{i + 1} = C _{i + 1} = P _{i +1} .

However, in the present invention described above, an n-bit error diffusion occurs in a channel error, a 3n-bit error diffusion occurs in a channel error, and a transmitter and receiver time delay However, since the assumption of P _i ≠ 0, which is a hardware realization problem, is not required, it is realized that the hardware burden of matching block sync and PCM channel synchronization is reduced when applied to multiple PCM This is advantageous.

Claims (8)

A first step of detecting whether all bits of the plaintext block are 0, mixing the plaintext block with a random number sequence block to detect whether all bits of the mixed block are 0, And if all the bits of the mixed block are not 0, the mixed block is transmitted as a ciphertext block. If all bits of the mixed block are 0, the corresponding plain text block is transmitted as a ciphertext block instead of the mixed block, A second step of, when all the bits of the plaintext block are 0, transmitting three plaintext blocks corresponding to the three mixed blocks including the previous and the next block to the ciphertext block; Detecting whether all the bits of the block are 0, mixing the ciphertext block with the random number sequence block, and detecting whether all bits of the mixed block are 0, If all the bits of the ciphertext block and all the bits of the ciphertext block are not 0 in the third step, the mixed block is output to the decrypted block, and if all the bits of the ciphertext block are 0, If all the bits of the ciphertext block are 0, three ciphertext blocks corresponding to the three ciphertext blocks including the before and after blocks are output to the decryption block. And a fourth step of synchronizing the stream cipher. The method of claim 1, wherein mixing in the first and third steps is performed by exclusive OR combination for each bit. The synchronizing method of a synchronous stream cipher according to claim 1 or 2, wherein detection of all bits in the first and third processes is performed by inverting and receiving the data of the block. A first summing unit for mixing a plaintext block with a random number generating block generated by a transmission random number generator, a first shift register for storing and outputting the plain text block, a second shift register for storing and outputting a mixed block of the first summer, And a second 0 detection unit for detecting whether all the bits of the mixed block stored in the second shift register are 0, and a 0 < th > detection unit for detecting whether all the bits of the clear block stored in the first shift register are 0, A first zero detection holding section for maintaining and outputting the zero detection signal of the first zero detection section during two periods of the system clock; and a second zero detection section for holding the zero detection signal A first multiplexer for selecting and outputting the mixed block of the second shift register only in the first shift register and selecting and outputting the plain block of the first shift register in the other case, A fourth shift register for storing and outputting a block output from the first multiplexer, and a fourth shift register for outputting a zero detection signal A second multiplexer for selecting a block of the fourth shift register and transmitting the selected block to a ciphertext block in a state in which the ciphertext block is output, and a second multiplexer for receiving the transmitted ciphertext block and mixing the random number sequence generated in the received random number sequence generator A fifth shift register for storing and outputting the ciphertext block, a sixth shift register for storing and outputting the mixed block of the second summer, and a sixth shift register for storing all the ciphertext blocks stored in the fifth shift register A third 0 detection unit for detecting whether the bit is 0, and a third 0 detection unit for detecting whether all the bits of the mixed block stored in the sixth shift register are 0 A 0th detection and holding unit for maintaining and outputting 0 detection signals of the 30th detection unit during 2 periods of the system clock; and a 0th detection and holding unit for outputting 0 detection signals in the 0th detection and holding unit and the 40th detection unit. A third multiplexer for selecting and outputting the mixed block of the sixth shift register only in a state where the ciphertext block is not in the fifth shift register, An eighth shift register for storing and outputting a block output from the third multiplexer; and a third shift register for outputting a zero detection signal in the state where the 0 & 7 shift register and outputs the decrypted block to the decryption block. Otherwise, the block of the eighth movement register is selected as a decryption block And a fourth multiplexer for outputting the multiplexed stream. 5. The synchronous stream cipher of claim 4, wherein the first and second summers are comprised of exclusive OR gates that are exclusive-ORed for each bit. The synchronous stream cipher system according to claim 3 or claim 5, wherein the first, second, third, and fourth detection units are configured by AND gates for inverting and receiving data of the block, Device. 6. The synchronous stream cipher system according to claim 4 or 5, wherein the first, second, third, and fourth detection units are configured by a Noah gate for directly receiving data of the block and combining them with each other. Device. 7. The semiconductor memory device according to claim 6, wherein the first and second detection / hold units comprise a delay unit for delaying and outputting a zero detection signal for one cycle of the system clock, and an OR gate for combining the output signal of the delay unit and the zero detection signal Wherein the synchronous stream cipher is a synchronous stream cipher.