KR19980054486A - Fuse box opening method of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. Technical problem to be solved by the invention

By opening the fuse box using a via hole mask before the protective film forming process, to simplify the process and to provide a method of opening the fuse box of the semiconductor device that can prevent the deterioration of the reliability of the device due to moisture penetration into the fuse box.

3. Summary of the Solution of the Invention

An interlayer insulating film and an interlayer insulating film are sequentially formed on an entire wafer structure in which a fuse box other than the cell region in which the element is formed is formed, and the fuse layer is etched by etching the interlayer insulating film and the interlayer insulating film having a predetermined thickness using a via hole forming mask. The present invention provides a method of opening a fuse box of a semiconductor device, comprising: forming a first protective layer and a second protective layer for protecting a lower layer on the entire structure.

4. Important uses of the invention

Used in fuse box opening process in semiconductor device manufacturing process.

Description

Fuse box opening method of semiconductor device

The present invention relates to a fuse box opening method for repairing a semiconductor device manufacturing process.

In general, when a defect occurs during a semiconductor device manufacturing process, an extra circuit is added to replace a defective device or a circuit in the device design to improve the yield of the device, and a fuse is connected to the integrated circuit. I'm designing a box together.

1 is a cross-sectional view of a fuse box opening process of a semiconductor device according to a related art, and includes a cell region (not shown) in which a semiconductor device is to be formed and a poly interlayer insulating film on an entire wafer structure in which a fuse box 1 other than the cell region is formed. 2) and forming the lower metal wiring in the cell region by the deposition of a lower metal wiring metal film and a series of etching processes, and then the first interlayer oxide film 3 and the SOG film (Spin-On-) on the entire structure. After forming the glass film 4 and the second interlayer oxide film 5 in sequence, and forming a via hole in which the lower metal wiring of the cell region is exposed by a series of visual processes using a mask for forming a via hole, the upper metal The upper metal wiring is formed in the cell region by the deposition and etching process of the wiring metal film.

Subsequently, PECVD (Plasma Enhanced Chemical) is used as a protective layer to protect from particles or contaminants that may affect device formation on the entire wafer structure, in which a series of semiconductor device manufacturing processes up to the upper metallization process are performed. Vapor Deposition (hereinafter referred to as PECVD) After the oxide film 6 and the PECVD nitride film 7 are sequentially formed, the PECVD nitride film outside the cell is subjected to a selective etching process using a repair mask for opening the fuse box. 7), the PECVD oxide film 6, the second metal interlayer oxide film 5, the SOG film 4, the first metal interlayer oxide film 3, and the poly interlayer dielectric film 2 of a predetermined thickness are selectively etched to open the fuse box. It shows what was made.

However, when the fuse box is opened by the conventional technology as described above, a repair mask process and a series of etching processes for the fuse box opening must be performed after the mask process for forming the via hole, and thus the overall process is complicated, and the fuse The fuse box is exposed to the air by an etching process for opening the box. At this time, moisture in the air penetrates into the fuse box, thereby degrading reliability of the device.

The present invention devised to solve the above problems by opening the fuse box using a via hole mask prior to the protective film forming process, it is possible to prevent the deterioration of the reliability of the device due to moisture penetration into the fuse box while simplifying the process. It is an object of the present invention to provide a fuse box opening method of a semiconductor device.

1 is a cross-sectional view of a fuse box opening process of a semiconductor device according to the prior art;

2A through 2C are cross-sectional views of a fuse box opening process of a semiconductor device according to an embodiment of the present invention;

3 is a cross-sectional view of the chip guide ring portion to which the present invention is applied.

Explanation of symbols on the main parts of the drawings

1: fuse box 2: poly interlayer insulating film

3, 5: metal interlayer oxide film 4: SOG film

6: PECVD oxide film 7: PECVD nitride film

8: photoresist pattern

The present invention for achieving the above object comprises the steps of sequentially forming an interlayer insulating film and a metal interlayer insulating film on top of the entire structure of the wafer pre-formed fuse box other than the cell region in which the device is formed; Etching the metal interlayer insulating film and the interlayer insulating film having a predetermined thickness by using a mask for forming a via hole to open a fuse box; And sequentially forming first and second protective layers for protecting the lower layer on the entire structure.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views of a fuse box opening process of a semiconductor device according to an embodiment of the present invention.

First, FIG. 2A shows a poly interlayer insulating film 2 formed over the entire wafer structure in which a fuse box 1 composed of a polysilicon film is formed in a cell region (not shown) where a semiconductor element is to be formed and in a region other than the cell region. After the lower metal wiring is formed in the cell region by the deposition of a metal film for lower metal wiring and a series of etching processes, the first interlayer oxide film 3 and the spin-on-glass film SOG 4 are formed on the entire structure. And a second interlayer oxide film 5 are sequentially formed, and then a photoresist is applied over the entire structure of the wafer including the cell region, and the photoresist pattern 8 is subjected to a series of photolithography processes using a mask for forming a via hole. It is shown that formed.

In this case, the fuse box may use a tungsten silicide layer instead of a polysilicon layer.

Subsequently, in FIG. 2B, the second interlayer oxide layer 5 having a predetermined thickness is etched by an isotropic etching process using the photoresist pattern 8 as an etch mask to widen a portion where the via hole is opened, and then the photoresist pattern 8 The second interlayer oxide film 5, the SOG film 4, the first interlayer oxide film 3, and the poly interlayer insulating film 2 of the predetermined thickness are formed by an anisotropic etching process using the etching mask as an etching mask. It shows that the fuse box is opened by selective etching.

Finally, FIG. 2C shows the PECVD oxide film 6 and PECVD as a protective layer for removing the photoresist pattern 8 and protecting it from particles or contaminants that may affect device formation on the entire structure. The formation of the nitride film 7 is shown in sequence.

Figure 3 shows that the above-described series of processes are also applied to the chip guard ring portion.

According to the present invention made as described above, the fuse box opening may be formed by opening the fuse box during the etching process for forming the via hole and then forming a protective film without performing the mask process for the fuse box opening and the etching process using the same. It is possible to omit a separate mask process and an etching process using the same, thereby simplifying the process, and preventing moisture penetration into the fuse box by exposure of the fuse box to the atmosphere. Reliability can be improved.

Claims (3)

Sequentially forming an interlayer insulating film and an intermetallic insulating film on the wafer entire structure in which a fuse box other than the cell region in which the device is formed is formed; Etching the metal interlayer insulating film and the interlayer insulating film having a predetermined thickness by using a mask for forming a via hole to open a fuse box; And A method of opening a fuse box of a semiconductor device, comprising the steps of sequentially forming a first and a second protective layer for protecting a lower layer on an entire structure. The method of claim 1, The opening of the fuse box by etching the interlayer insulating film and the interlayer insulating film having a predetermined thickness using a mask for forming a via hole may include: isotropically etching the interlayer insulating film having a predetermined thickness to widen a portion where the via hole is opened; And And anisotropically etching the interlayer insulating film having a residual thickness and the interlayer insulating film having a predetermined thickness. The method of claim 1, And the fuse box is either a polysilicon film or a tungsten silicide film.