KR19980026275A - Low Power Consumption CPU - Google Patents

Abstract

The present invention relates to a low power type CPU (DSP Core, Microprocessor Core) capable of reducing power consumption in a data path device driven in synchronization with a system clock. The low power type CPU of the present invention transfers data. A data bus for; A plurality of data path devices receiving data from the data bus in response to a control signal, performing data processing in synchronization with a system clock signal, and transferring a result of the processed data to the bus; A control signal generator configured to output a system clock control signal such that a system clock signal is not supplied except a control signal for controlling data transmission between a data bus and the data path devices and data path devices for performing an operation according to a command; And system clock gate means for limiting the system clock signal in response to the system clock control signal, so that the system clock signal is not supplied to the data path devices other than the data path devices according to the command, thereby preventing unnecessary data paths. Power consumption due to the operation of the devices can be prevented.

Description

Low Power Central Processor Unit (CPU)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU (DSP Core, Microprocessor Core), and more particularly, to a low power type CPU that can reduce power consumption in a data path device driven in synchronization with a system clock.

In response to the demands of portable electronic products and the long-term use of such portable products, the demand for low power type CPUs has risen in recent trends. In line with this trend, manufacturers who design CPUs (DSP Core and Microprocessor) are putting a lot of effort into making low-power cores.

In general, the CPU may vary depending on the architecture at the time of design, but the data path block in the CPU includes an operation unit and an address generator, and in particular, the operation unit includes many devices for data paths. That is, an Arithmetic Logical Unit (ALU), a multiplier, a barrel shifter, and the like belong to this. In the address generator, the data path block includes blocks that generate some memory addresses used in CPU installation and blocks that support special functions such as a repeat function. In addition, multiple data path blocks can be generated according to the CPU design architecture standard.

FIG. 1 is a diagram illustrating power consumption in data path devices driven in synchronization with a system clock in a conventional CPU. The first and second data buses Bus1 and Bus2 for transferring data and a system clock are shown in FIG. In response to the control signal B_to_D while being driven in common with the system clock, data is received from the first and second buses Bus1 and Bus2 to process data, and the generated data is responded to the control signal D_to_B. N data pass units (Unit 1-n), the data pass units (Unit 1-Unit n) and the first and second bus (n) output to the first and second buses (Bus1, Bus2) A control signal generator 100 for outputting control signals B_to_D, D_to_B, D_O_I for controlling data transfer between Bus1 and Bus2 is shown.

In the drawing, the control signal generator 100 outputs a control signal as follows. DN_O_I is a signal for controlling a previous result value to be input from the first data path device, and DN_to_B1 is a signal from the nth data path device to the first bus. The signal controls to move the data, and DN_to_B2 is a signal to control the data to move from the n-th data path device to the second bus. In addition, B1_to_DN is a signal for controlling data to move from the first bus to the n-th data path device, and B2_to_DN is a signal for controlling data to move from the second bus to the n-th data path device.

In the above configuration, the result of the first data path device Unit 1 and the second data path device Unit 2, which receives data from the first and second buses Bus1 and Bus2, respectively, is the n-1 data path. In the case of a command to be input to the unit n-1, a control signal from the first and second buses Bus1 and Bus2 to the first data path device and the second data path device Unit 1 and Unit 2 may be used. Data is input in response to B1_to_D1, D1_O_I, and the first and second data path devices (Unit 1, Unit 2) are operated by the system clock to have the result. The system clock allows the results of the first and second data path devices Unit 1 and Unit 2 to be input to the n-th pass device Unit n-1.

However, at this time, when the first and second data path devices (Unit 1, Unit 2) perform the operation in synchronization with the system clock (System Clock) or as a result of the first and second data path devices (Unit 1, Unit 2) Data path devices other than the first, second, and n-1 data path devices (Unit 1, Unit 2, Unit n-1) when is input to the n-1 data path device (Unit n-1) (Units 3, 4, ...) also operate by the system clock (System Clock), causing unnecessary power consumption.

An object of the present invention is to operate all data path devices in synchronization with the system clock as described above to reduce the unnecessary power consumption by operating only the data path device necessary for one command to solve the problem of power consumption. It is to provide a low power consumption CPU.

A low power consumption CPU of the present invention for achieving the above object includes a data bus for transferring data; A plurality of data path devices receiving data from the data bus in response to a control signal, performing data processing in synchronization with a system clock signal, and transferring a result of the processed data to the bus; A control signal generator configured to output a system clock control signal such that a system clock signal is not supplied except a control signal for controlling data transmission between a data bus and the data path devices and data path devices for performing an operation according to a command; And system clock gate means for limiting the system clock signal in response to the system clock control signal.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining power consumption in a data path device driven in synchronization with a system clock in a conventional CPU.

2 is a block diagram of a low power type CPU in accordance with the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a low power consumption CPU according to the present invention, in which the first and second buses Bus1 and Bus2 transfer data and the control signals B_to_D and D_O_I in response to the first and second buses. N data path devices that receive data from Bus1 and Bus2, perform operations in synchronization with a system clock signal, and transfer the result to first and second buses Bus1 and Bus2 1-Unit n), and control signals (B_to_D, D_to_B, D_O_I) and system for controlling data transmission between the first and second buses Bus1 and Bus2 and the data path devices Unit 1-Unit n. The control signal generator 200 which generates a system clock control signal DP_N_enable so that the clock signal System Clock is not supplied except the data path devices Unit 1, Unit 2, and Unit n-1 that perform an operation according to a command. And a system clock signal S in response to the system clock control signal DP_1_enable-DP_N_enable. It consists of a system clock gate means 300 composed of n AND gates A1 -An which limit the ystem clock.

In the above configuration, when a command to use the results of the first and second data path devices Unit 1 and Unit 2 as an input of the n-1 data path device Unit n-1 is given, the control signal B_to_D Data is input from the first bus Bus1 to the first data path device Unit 1, data is input from the second bus Bus2 to the second data path device Unit 2, and the system clock signal is input. The first and second data path devices (Unit 1, Unit 2) perform the operation, respectively, to obtain a result, and then synchronize the first and second data clock signals (System Clock). Data is transferred to the buses Bus1 and Bus2 and input to the n-th data path device Unit n-1 in response to the control signal B1_to_Dn-1.

In this case, while the first and second data path devices Unit 1 and Unit 2 and the n-1 data path device Unit n-1 perform operations, other data path devices Unit 3, 4, and 5 may be used. ...) is limited by the system clock control signals DP_3_enable, DP_4_enable, DP_5_enable ... DP_N_enable output from the control signal generator 200, thereby preventing the system clock from being supplied. That is, when the system clock control signal DP_1_enable-DP_N_enable is not input high from the control signal generator 200 according to the operation characteristics of the AND gates A1-An, the system clock signal is always the data path devices ( It is not supplied to Unit 1-Unit n).

The system clock control signal DP_1_enable − except for the data path devices (Unit 1, Unit 2, Unit n-1) according to the command among the data path devices (Unit 1 to Unit n) operating on the system clock signal as described above. By not allowing the system clock signal to be supplied through the AND gates A1-An corresponding to DP_N_enable, unnecessary data path devices Units 3, 4, 5... Can not be operated.

As described above, the system clock signal is not supplied to other data path devices other than the data path devices according to the command, thereby preventing power consumption due to unnecessary data path devices.

Claims (1)

A data bus for carrying data; A plurality of data path devices receiving data from the data bus in response to a control signal, processing the input data in response to a system clock signal, and transferring the processed data to the bus; A control signal generator that outputs a system clock control signal to limit a system clock signal supplied except for a control signal for controlling data transmission between a data bus and the data path devices and data path devices for performing an operation according to a command. ; And a plurality of system clock gate means for limiting the system clock signal in response to the system clock control signal.