KR102746080B1 - Three-dimensional semiconductor device - Google Patents

Abstract

A three-dimensional semiconductor device is provided. The three-dimensional semiconductor device comprises: a memory cell array region; extension regions on both sides of the memory cell array region; main isolation structures crossing the memory cell array region and the extension regions; a gate stack structure disposed within the memory cell array region and extending into the extension regions; vertical channel structures disposed between the main isolation structures and penetrating the gate stack structure within the memory cell array region; and at least one through region disposed within the memory cell array region or the extension regions and penetrating the gate stack structure, wherein the through region has a side including at least one step.

Description

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

The technical idea of the present invention relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor device including a through-hole region penetrating a gate stack structure.

A semiconductor device including gate electrodes stacked in a direction perpendicular to the surface of a semiconductor substrate is being developed. In order to achieve high integration of semiconductor devices, the number of stacked gate electrodes is increasing. As such, as the number of gate electrodes stacked in a direction perpendicular to the surface of a semiconductor substrate is increasing, the difficulty of the process of electrically connecting the gate electrodes to a peripheral circuit is increasing, and unexpected defects are occurring.

The problem that the technical idea of the present invention seeks to solve is to provide a three-dimensional semiconductor device.

The technical idea of the present invention is to provide a three-dimensional semiconductor device capable of high integration and a method for forming the same.

According to one embodiment of the present invention, a three-dimensional semiconductor device is provided. The three-dimensional semiconductor device includes: an upper substrate; a gate stacked structure disposed on the upper substrate and including gate electrodes, the gate electrodes being stacked while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate within a memory cell array region and having pad regions extending into an extension region adjacent to the memory cell array region and arranged in a step shape within the extension region; and at least one through region penetrating the gate stacked structure within the memory cell array region or the extension region. The at least one through region includes a lower region and an upper region above the lower region, and the upper region has a larger width than the lower region.

According to one embodiment of the present invention, a three-dimensional semiconductor device is provided. The three-dimensional semiconductor device includes: a lower substrate; a lower structure disposed on the lower substrate and including a peripheral circuit; an upper substrate disposed on the lower structure; a gapfill layer within a substrate hole in the upper substrate; a gate stacked structure disposed on the upper substrate and including gate electrodes; and a through region penetrating the gate stacked structure, wherein the through region has a side including a stepped portion.

According to one embodiment of the present invention, a three-dimensional semiconductor device is provided. The three-dimensional semiconductor device includes: a memory cell array region; extension regions on both sides of the memory cell array region; main isolation structures crossing the memory cell array region and the extension regions; a gate stack structure disposed within the memory cell array region and extending into the extension regions; vertical channel structures disposed between the main isolation structures and penetrating the gate stack structure within the memory cell array region; and at least one through region disposed within the memory cell array region or the extension regions and penetrating the gate stack structure, wherein the through region has a side including at least one step.

According to embodiments of the present invention, since a three-dimensional semiconductor device can be provided in which a peripheral circuit can be arranged under a gate stacked structure, the integration degree of the semiconductor device can be improved. In addition, since a through region penetrating the gate stacked structure, which is used to electrically connect gate electrodes of the gate stacked structure and peripheral circuits, can be provided, the integration degree of the semiconductor device can be improved even if the number of stacked gate electrodes is increased. In addition, since the through region can be formed with a larger width in the upper region than in the lower region, void defects, etc. that may occur when forming the through region with an insulating layer can be prevented.

FIG. 1 is a schematic block diagram of a semiconductor device according to one embodiment of the present invention.
FIG. 2 is a circuit diagram conceptually illustrating an exemplary example of the memory cell array region of a semiconductor device according to one embodiment of the present invention.
FIG. 3A is a plan view conceptually illustrating an exemplary example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 3b is a perspective view conceptually illustrating an exemplary example of a three-dimensional semiconductor element (10a) according to one embodiment of the present invention.
FIGS. 4 and 5 are cross-sectional views conceptually illustrating exemplary examples of three-dimensional semiconductor devices according to one embodiment of the present invention.
FIG. 6a is a plan view conceptually illustrating a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 6b is a perspective view conceptually illustrating a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 7a is a cross-sectional view conceptually illustrating a portion of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 7b is a cross-sectional view conceptually illustrating a deformation example of a portion of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIGS. 8A and 8B are enlarged partial views of portions of FIG. 4 to explain exemplary examples of three-dimensional semiconductor devices according to one embodiment of the present invention.
FIG. 9 is a plan view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention.
FIG. 10a is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention.
FIG. 10b is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention.
FIG. 10c is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention.
FIG. 11a is a perspective view conceptually illustrating a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 11b is a cross-sectional view conceptually illustrating a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIGS. 13a and 13b are cross-sectional views showing modified examples of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 14 is a plan view showing a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 15 is a plan view showing a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 16 is a plan view showing a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIG. 17 is a plan view showing a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention.
FIGS. 18a and 18b are process flow diagrams showing exemplary examples of a method for forming a three-dimensional semiconductor device according to one embodiment of the present invention.
FIGS. 19 to 24 are perspective views conceptually illustrating exemplary examples of a method for forming a three-dimensional semiconductor device according to one embodiment of the present invention.
FIGS. 25a to 31b are cross-sectional views conceptually illustrating exemplary examples of a method for forming a three-dimensional semiconductor device according to one embodiment of the present invention.

An exemplary example of a three-dimensional semiconductor device according to the technical idea of the present invention will be described with reference to FIG. 1. FIG. 1 is a schematic block diagram of a semiconductor device according to one embodiment of the present invention.

Referring to FIG. 1, a semiconductor device (10) according to one embodiment of the present invention may include a memory cell array region (20) and a control logic region (30).

The above memory cell array region (20) includes a plurality of memory blocks (BLK), and each of the memory blocks (BLK) may include a plurality of memory cells. The above control logic region (30) may include a row decoder (32), a page buffer (34), and a control circuit (36).

The plurality of memory cells of each of the above memory blocks (BLK) can be connected to the row decoder (32) through a string select line (SSL), a plurality of word lines (WL) and a ground select line (GSL), and can be connected to the page buffer (34) through bit lines (BL).

In embodiments, a plurality of memory cells arranged along the same row may be connected to the same word line (WL), and a plurality of memory cells arranged along the same column may be connected to the same bit line (BL).

The above row decoder (32) can decode an input address and generate and transmit driving signals of a word line (WL). The row decoder (32) can provide a word line voltage generated from a voltage generation circuit in the control circuit (36) in response to the control of the control circuit (36) to each of a word line selected from among the word lines (WL) and a word line unselected from among the word lines (WL).

The above page buffer (34) is connected to the memory cell array area (20) through the bit lines (BL) and can read information stored in the memory cells. Depending on the operation mode, the page buffer (34) can temporarily store data to be stored in the memory cells or detect data stored in the memory cells. The page buffer (34) can include a column decoder and a sense amplifier.

The column decoder can selectively activate bit lines (BL) of the memory cell array region (20), and the sense amplifier can detect the voltage of the bit line (BL) selected by the column decoder during a read operation to read data stored in the selected memory cell. The control circuit (36) can control the operations of the row decoder (32) and the page buffer (34). The control circuit (36) can receive a control signal and an external voltage transmitted from the outside, and operate according to the received control signal. The control circuit (36) can include a voltage generation circuit that generates voltages required for internal operations, for example, a program voltage, a read voltage, an erase voltage, etc., by using an external voltage. The control circuit (36) can control a read, write, and/or erase operation in response to the control signals. In addition, the control circuit (36) can include an input/output circuit. The above input/output circuit can receive data (DATA) during program operation and transfer it to the page buffer (34), and output data (DATA) received from the page buffer (34) to the outside during a read operation.

Referring to FIG. 2, an exemplary example of a circuit of each memory block (BLK) of the memory cell array area (20 of FIG. 1) of the three-dimensional semiconductor device (10 of FIG. 1) according to an embodiment of the present invention described in FIG. 1 will be described. FIG. 2 is a circuit diagram conceptually showing an exemplary example of the memory cell array area (20 of FIG. 1).

Referring to FIG. 2, each of the memory blocks (BLK) of the memory cell array region (20 of FIG. 1) may include memory cells (MC) connected in series to each other, a first selection transistor (ST1) and a second selection transistor (ST2) connected in series to both ends of the memory cells (MC).

The first and second selection transistors (ST1, ST2) and the memory cells (MC) between the first and second selection transistors (ST1, ST2) can form memory strings (S). The memory cells (MC) connected in series with each other can be respectively connected to word lines (WL) for selecting the memory cells (MC).

The gate terminal of the first selection transistor (ST1) may be connected to the first selection line (SL1), and the source terminal may be connected to the common source line (CSL). The gate terminal of the second selection transistor (ST2) may be connected to the second selection line (SL2), and the source terminal may be connected to the drain terminal of the memory cells (MC).

In one example, the first selection transistor (ST1) may be a ground selection transistor, and the second selection transistor (ST2) may be a string selection transistor (ST2).

In one example, the first selection line (SL1) may be the ground selection line (GSL of FIG. 1) in FIG. 1, and the second selection line (SL2) may be the string selection line (SSL of FIG. 1) in FIG. 1.

In Fig. 2, a structure is illustrated in which the first selection transistor (ST1) and the second selection transistor (ST2) are connected one by one to the memory cells (MC) that are connected in series with each other, but alternatively, a plurality of first selection transistors (ST1) or a plurality of second selection transistors (ST2) may be connected.

In one example, a first dummy line (DL1) may be arranged between the lowest word line (WL) among the word lines (WL) and the first selection line (SL1), and a second dummy line (DL2) may be arranged between the highest word line (WL) among the word lines (WL) and the second selection line (SL2). One or more first dummy lines (DL1) may be arranged, and one or more second dummy lines (DL2) may be arranged.

The drain terminal of the second selection transistor (ST2) may be connected to a bit line (BL). When a signal is applied to the gate terminal of the second selection transistor (ST2) through the second selection line (SL2), the signal applied through the bit line (BL) is transmitted to memory cells (MC) that are connected in series with each other, so that a data read and write operation can be executed. In addition, an erase operation that erases data written in the memory cells (MC) may be executed by applying a predetermined erase voltage through the substrate.

A semiconductor device according to one embodiment of the present invention may include at least one dummy string (DS). The dummy string (DS) may be a string including a dummy channel that is electrically separated from the bit line (BL).

FIG. 3A is a plan view conceptually illustrating an exemplary example of a three-dimensional semiconductor device (10) according to one embodiment of the present invention. FIG. 3B is a perspective view conceptually illustrating an exemplary example of a three-dimensional semiconductor device (10) according to one embodiment of the present invention, FIG. 4 is a cross-sectional view illustrating a region taken along line I-I' of FIG. 3A, and FIG. 5 is a cross-sectional view illustrating a region taken along line II-II' of FIG. 3A.

Referring to FIGS. 3A, 3B, 4, and 5, an exemplary three-dimensional semiconductor device (10) may include a lower substrate (105), a lower structure (110) on the lower substrate (105), an upper substrate (150) on the lower structure (110), and a gate stacked structure (270) on the upper substrate (150).

The lower substrate (105) may be a semiconductor substrate formed of a semiconductor material such as single crystal silicon. The lower structure (110) may include a peripheral circuit (PCIR) arranged on an active region (120) limited to an isolation region (115), and a lower insulating layer (140) covering the peripheral circuit (PCIR). The peripheral circuit (PCIR) may include a peripheral transistor (PTR) and peripheral wirings (130) electrically connected to the peripheral transistor (PTR). The lower insulating layer (140) may be formed of silicon oxide. The upper substrate (150) may be a semiconductor substrate formed of a semiconductor material such as polysilicon.

An exemplary three-dimensional semiconductor device (10) may include a gapfill layer (160a) disposed within a first substrate hole (155a) penetrating the upper substrate (150) and an intermediate insulating layer (162) disposed on a side surface of the upper substrate (150). The gapfill layer (160a) and the intermediate insulating layer (162) may be formed of the same insulating material, for example, silicon oxide.

The gate stacked structure (270) may include gate electrodes that are stacked and spaced apart from each other in a direction perpendicular to the surface of the upper substrate (150). The gate electrodes of the gate stacked structure (270) may be formed of a conductive material including at least one of doped silicon, a metal nitride (e.g., TiN), a metal silicide (e.g., WSi, TiSi, TaSi, etc.), or a metal (e.g., W). The doped silicon may be polysilicon including an N-type impurity (e.g., P, As, etc.) or a P-type impurity (e.g., B, etc.).

An exemplary three-dimensional semiconductor device (10) may include a lower interlayer insulating layer (210L) disposed between the lowermost gate electrode of the gate stack structure (270) and the upper substrate (150), an uppermost interlayer insulating layer (210U) disposed on the uppermost gate electrode of the gate stack structure (270), and middle interlayer insulating layers (210M) disposed between the gate electrodes of the gate stack structure (270).

The gate electrodes of the gate stack structure (270) may be stacked while being spaced apart from each other within the memory cell array region (20) on the upper substrate (150), and may extend into an extension region (22) on the upper substrate (150) to have pad regions (P) within the extension region (22). Among the gate electrodes of the gate stack structure (270), each of the gate electrodes positioned below the uppermost gate electrode may include an overlapping region that overlaps with a gate electrode positioned relatively above it and a non-overlapping region that does not overlap with the gate electrode positioned relatively above it. The non-overlapping region may be the pad region (P).

The above memory cell array region (20) may be a region in which the memory blocks (BLK) including the plurality of memory cells (MC of FIG. 2) as described with reference to FIGS. 1 and 2 are formed, and the extension region (22) may be a region in which pad regions (P) formed by extending gate electrodes of the gate stack structure (270) formed within the memory cell array region (20) are arranged. Here, the pad regions (P) may be regions of gate electrodes that can come into contact with gate contact plugs (280g) formed to electrically connect with the row decoder (32 of FIG. 1).

In the embodiments, the direction from the memory cell array region (20) in the plane toward the extension region (22) is referred to as a first direction (X), the direction perpendicular to the first direction (X) is referred to as a second direction (Y), and the direction perpendicular to the surface of the upper substrate (150) in the cross section is referred to as a third direction (Z).

In one example, the gate electrodes of the gate stack structure (270) may include a lower gate electrode (GE_L), middle gate electrodes (GE_M) on the lower gate electrode (GE_L), and upper gate electrodes (GE_U) on the middle gate electrodes (GE_M).

In one example, the gate electrodes of the gate stack structure (270) may include a dummy gate electrode (GE_D1) between the lower gate electrode (GE_L) and the middle gate electrodes (GE_M), and a buffer gate electrode (GE_D2) between the middle gate electrodes (GE_M) and the upper gate electrodes (GE_U). Here, the buffer gate electrode (GE_D2) may also be referred to as a dummy gate electrode.

In one example, the lower gate electrode (GE_L) can be the first selection line (SL1 of FIG. 2) described in FIG. 2 and the ground selection line (GSL of FIG. 1) described in FIG. 1, the dummy gate electrode (GE_D1) can be the first dummy line (DL1) described in FIG. 2, the middle gate electrodes (GE_M) can be the word lines (WL of FIGS. 1 and 2) described in FIGS. 1 and 2, the buffer gate electrode (GE_D2) can be the second dummy line (DL2 of FIG. 2) described in FIG. 2, and the upper gate electrodes (GE_U) can be the second selection line (SL1 of FIG. 2) described in FIG. 2 and the string selection line (SSL of FIG. 1) described in FIG. 1.

The above extension region (22) may include a first step region (22a), a second step region (22c), and a buffer region (22b) between the first and second step regions (22a, 22c).

The first step region (22a) may be a region in which the pad regions (P) of the upper gate electrodes (GE_U) are arranged in a step shape, and the second step region (22c) may be a region in which the pad regions (P) of the intermediate gate electrodes (GE_M), the pad region (P) of the dummy gate electrode (GE_D1), and the pad region (P) of the lower gate electrode (GE_L) are arranged in a step shape.

An exemplary three-dimensional semiconductor device (10) may include a first pad penetration region (TH1) penetrating the gate stack structure (270). The first pad penetration region (TH1) may overlap the first gapfill layer (160a).

In one example, the first pad penetration region (TH1) can penetrate the gate electrodes of the gate stack structure (270) within the buffer region (22b) between the first and second step regions (22a, 22c) and can penetrate the intermediate interlayer insulating layers (210M) between these gate electrodes. Furthermore, the first pad penetration region (TH1) can penetrate the lower interlayer insulating layer (210L).

In one example, the first pad penetration region (TH1) may include a lower penetration region (TH1_L) and an upper penetration region (TH1_U) on the lower penetration region (TH1_L). The upper penetration region (TH1_U) may have a wider width than the lower penetration region (TH1_L).

In one example, the side surface of the upper penetration area (TH1_U) may not be vertically aligned with the side surface of the lower penetration area (TH1_L).

In one example, the vertical length of the upper penetration region (TH1_U) may be greater than the vertical length of the lower penetration region (TH1_L).

In one example, the first pad penetration area (TH1) may have a side including a stepped portion (S1). The stepped portion (S1) may be positioned closer to the lower surface of the gate stack structure (270) than to the upper surface of the gate stack structure (270).

An exemplary three-dimensional semiconductor device (10) may include an upper insulating layer (230) covering a portion of the gate stack structure (270). The upper insulating layer (230) may be positioned below an uppermost gate electrode among the gate electrodes of the gate stack structure (270) and may cover the gate electrodes positioned on the extended region (22). Accordingly, the upper insulating layer (230) may be disposed on the extended region (22).

In one example, the upper insulating layer (230) covers an upper portion of the first pad penetration area (TH1) and may be formed integrally with the first pad penetration area (TH1). The first pad penetration area (TH1) and the upper insulating layer (230) may be formed of silicon oxide.

An exemplary three-dimensional semiconductor device (10) may include vertical channel structures (VS) penetrating through the gate stack structure (270) and penetrating through the upper interlayer insulating layer (210U), the middle interlayer insulating layers (210M), and the lower interlayer insulating layer (210L). The vertical channel structures (VS) may be connected to the upper substrate (150). The vertical channel structures (VS) may be disposed on the memory cell array region (20).

In the above gate stack structure (270), the pad regions (P) arranged in the second step region (22c) may be arranged in a step shape. Here, the step shape in the second step region (22c) defined by a pair of adjacent first main separation structures (MS1) and a second main separation structure (MS2) arranged between the pair of first main separation structures (MS1) will be described with reference to FIG. 3b. Such a step shape may be a step shape in a pair of adjacent memory blocks (BLK). Hereinafter, the pad regions (P) of the gate electrodes arranged in a step shape will be described as “steps.”

It may include first stair groups (SG1) close to the first main separation structures (MS1), a second stair group (SG2) arranged in a middle portion between the first stair groups (SG1), and third stair groups (SG3) arranged between the first stair groups (SG1) and the second stair group (SG2). The third stair groups (SG3) may be close to the first stair groups (SG1). The second stair group (SG2) may be separated by the second main separation structure (MS2).

In one example, dummy areas (DA) may be placed between the second step group (SG2) and the third step groups (SG3). The dummy areas (DA) may be areas where steps are not formed.

The steps of each of the first step groups (SG1) may be increased to a first height in a direction away from the first main separation structures (MS1). Here, the first height may be a height difference between two adjacent gate electrodes among the gate electrodes spaced apart in a direction perpendicular to the surface of the upper substrate (150).

The steps of the first step groups (SG1) may be lowered to a second height greater than the first height in a direction away from the memory cell array region (20). For example, the second height may be a height difference between the first and third gate electrodes among the first, second, and third gate electrodes that are arranged in the vertical direction in sequence.

At least some of the steps of the second step groups (SG2) may be arranged closer to the upper substrate (150) than the steps of the first step groups (SG1). At least some of the steps of the third step groups (SG3) may be arranged closer to the upper substrate (150) than the steps of the second step groups (SG2). The steps of the third step groups (SG3) may be arranged closer to the upper substrate (150) than the steps of the first step groups (SG1).

In a modified example, the dummy areas (DA) arranged between the second step group (SG2) and the third step groups (SG3) as described above may be replaced with second pad penetration areas (TH2 of FIGS. 6A and 6B). Such a modified example will be described with reference to FIGS. 6A and 6B. FIG. 6A is a plan view conceptually illustrating a modified example of a three-dimensional semiconductor device (10a) according to an embodiment of the present invention. FIG. 6B is a perspective view conceptually illustrating a modified example of a three-dimensional semiconductor device (10a) according to an embodiment of the present invention.

Referring to FIGS. 6A and 6B, as described above, the dummy areas (DA in FIGS. 3A and 3B) arranged between the second step group (SG2) and the third step groups (SG3) may be replaced with second pad penetration areas (TH2) as in FIGS. 6A and 6B. Accordingly, the upper substrate (150) may include a gapfill layer (160b) arranged in an area overlapping the second pad penetration areas (TH2).

Next, exemplary examples of the vertical channel structure (VS) described above will be described with reference to FIGS. 7A and 7B, respectively. FIG. 7A is a cross-sectional view conceptually illustrating one vertical channel structure together with a gate in a three-dimensional semiconductor device according to an embodiment of the present invention in order to explain exemplary examples of the vertical channel structure and the gate.

Referring to FIG. 7a, the vertical channel structure (VS) can be positioned within a channel hole (234) penetrating the gate stack structure (270), the lower interlayer insulating layer (210L), the middle interlayer insulating layer (210M), and the upper interlayer insulating layer (210U).

In one example, the vertical channel structure (VS) may include an insulating core layer (248) extending in a direction perpendicular to a surface of the upper substrate (150) and penetrating the gate stack structure (270), a channel semiconductor layer (246) covering side surfaces and a bottom surface of the insulating core layer (248), a first gate dielectric (240) surrounding an outer side of the channel semiconductor layer (246), and a pad layer (250) disposed on the insulating core layer (248) and electrically connected to the channel semiconductor layer (246).

The above channel semiconductor layer (246) may be electrically connected to the upper substrate (150). The channel semiconductor layer (246) may be formed of a semiconductor material such as silicon. The pad layer (250) may be formed of doped polysilicon having an N-type conductivity. The insulating core layer (248) may be formed of an insulating material such as silicon oxide.

An exemplary three-dimensional semiconductor device (10a) may include a second gate dielectric (268) interposed between the gate electrodes of the gate stack structure (270) and the vertical channel structure (VS) and extending to the lower and upper surfaces of the gate electrodes.

Either of the first and second gate dielectrics (240, 269) may include a layer capable of storing information. For example, the first gate dielectric (240) may include a layer capable of storing information. However, the technical idea of the present invention is not limited thereto. For example, the second gate dielectric (268) may include a layer capable of storing information. Hereinafter, an example in which the first gate dielectric (240) includes a layer capable of storing information will be described.

The first gate dielectric (240) may include a tunnel dielectric (242), an information storage layer (243), and a blocking dielectric (244). The information storage layer (243) may be disposed between the tunnel dielectric (242) and the blocking dielectric (244). The tunnel dielectric (242) may be close to the channel semiconductor layer (246), and the blocking dielectric (244) may be close to the gate stacked structure (270). The tunnel dielectric (242) may be disposed between the channel semiconductor layer (246) and the information storage layer (243), and the blocking dielectric (244) may be disposed between the channel semiconductor layer (246) and the gate stacked structure (270).

The tunnel dielectric (242) may include silicon oxide and/or impurity-doped silicon oxide. The blocking dielectric (244) may include silicon oxide and/or a high-k dielectric. The information storage layer (243) may be a layer for storing information between the channel semiconductor layer (256) and the intermediate gate electrodes (GE_M). For example, the information storage layer (243) may be formed of a material, such as silicon nitride, which can trap and retain electrons injected from the channel semiconductor layer (246) through the tunnel dielectric (242) or erase trapped electrons within the information storage layer (243), depending on the operating conditions of a nonvolatile memory device, such as a flash memory device. The second gate dielectric (268) may include a high-k dielectric (e.g., AlO, etc.).

The information storage layer (243) can store information in regions facing the intermediate gate electrodes (GE_M) that can correspond to the word lines (WL of FIGS. 1 and 2) described in FIGS. 1 and 2 among the gate stacked structure (270). Regions capable of storing information in the information storage layer (243) in the vertical channel structure (VS) can be arranged in a direction perpendicular to the surface of the upper substrate (150) and can configure the memory cells (MC) described in FIG. 2.

The above channel semiconductor layer (246) may be directly connected to the upper substrate (150), but the technical idea of the present invention is not limited thereto. A variation example of the cell vertical structure (VS) will be described with reference to FIG. 7b. FIG. 7b is a conceptual cross-sectional view for explaining a variation example of the vertical channel structure in a three-dimensional semiconductor device according to an embodiment of the present invention.

Referring to FIG. 7b, among the gate electrodes of the gate stack structure (270), the distance between the lower gate electrode (GE_L) closest to the upper substrate (150) and the dummy gate electrode (GE_D1) on the lower gate electrode (GE_L) may be greater than the distance between other gate electrodes.

The vertical channel structure (VS') may be arranged in the channel hole (234) as described in FIG. 7a. The vertical channel structure (VS') may include a lower channel semiconductor layer (235) disposed below the channel hole (234) and facing the lower gate electrode (GE_L), an insulating core layer (248) disposed on the lower channel semiconductor layer (235), an upper channel semiconductor layer (246') covering side surfaces and a bottom surface of the insulating core layer (248), a first gate dielectric (240) surrounding an outer side of the upper channel semiconductor layer (246'), and a pad layer (250) disposed on the insulating core layer (248) and electrically connected to the channel semiconductor layer (246). The lower channel semiconductor layer (235) may be directly connected to the upper substrate (150) and may be formed as an epitaxial semiconductor layer. The upper channel semiconductor layer (246') may be formed of a semiconductor material such as silicon. The first gate dielectric (240) may be the same as that described in FIG. 7a. In addition, a second gate dielectric (268) the same as that described in FIG. 7a may be disposed between the vertical channel structure (VS') and the gate stacked structure (270) and extending to the upper and lower surfaces of the gate electrodes of the gate stacked structure (270).

Again, referring to FIGS. 3a to 5, the exemplary three-dimensional semiconductor device (10a) may include the upper interlayer insulating layer (210U) and a first capping insulating layer (255) disposed on the upper insulating layer (230). The first capping insulating layer (255) may be formed of silicon oxide.

An exemplary three-dimensional semiconductor device (10a) may include main isolation structures (MS) crossing the memory cell array region (20) and the extended region (22). Each of the memory blocks (BLK in FIG. 1) within the memory cell array region (20) described in FIG. 1 may be positioned between a pair of adjacent main isolation structures (MS).

An exemplary three-dimensional semiconductor device (10a) may include auxiliary separation structures (SS) arranged between the main separation structures (MS). Each of the auxiliary separation structures (SS) may be formed to have a length shorter than the length of each of the main separation structures (MS).

In one example, the auxiliary separation structures (SS) may include line-shaped auxiliary separation structures extending across the memory cell array region (20) to a portion of the extension region (22), and auxiliary structures arranged within the extension region (22). Accordingly, the auxiliary separation structures (SS) may be line-shaped and may be spaced apart in the longitudinal direction of the line shape within a portion of the extension region (22). Accordingly, any one of the intermediate gate electrodes positioned between a pair of adjacent main separation structures (MS) and positioned on the same plane is not completely separated by the auxiliary separation structures (SS), and thus may be used as one word line.

Between a pair of adjacent main separation structures (MS), the auxiliary separation structures (SS) can separate the upper gate electrode (GE_U) into multiple pieces.

In one example, an insulating line (232) may be arranged between a pair of adjacent main separating structures (MS) and between the auxiliary separating structures (SS) to separate the upper gate electrodes (GE_U) that are separated into multiple pieces. The insulating line (232) may be arranged at a higher level than the intermediate gate electrodes (GE_M).

The above main separation structures (MS) and the auxiliary separation structures (SS) are arranged on the upper substrate (150) and can penetrate the gate stacked structure (270). The above main separation structures (MS) and the auxiliary separation structures (SS) can penetrate the gate stacked structure (270), the lower interlayer insulating layer (210L), the middle interlayer insulating layers (210M), the upper interlayer insulating layer (210U), and the upper insulating layer (230).

Each of the above-described main separation structures (MS) and the above-described auxiliary separation structures (SS) may include a conductive pattern (276) and a spacer (274) covering a side surface of the conductive pattern (276). The spacer (274) may be formed of an insulating material, such as silicon oxide or silicon nitride. The spacer (274) may space the conductive pattern (276) and the gate stacked structure (270). The conductive pattern (276) may be formed of a conductive material including at least one of a metal nitride, such as doped polysilicon, titanium nitride, or the like, or a metal, such as tungsten. In one example, the conductive pattern (276) may also be referred to as a source contact plug.

The above main separation structures (MS) may include first main separation structures (MS1) and second main separation structures (MS2) between the first main separation structures (MS1).

In one example, the second main separation structure (MS2) may include a portion (MS2') that is divided into two lines from a single line and extends into the extension region (22) across the memory cell array region (20) as a single line and surrounds the first pad penetration region (TH1). The divided portion (MS2') of the second main separation structure (MS2) may be combined again into a single line to cross the remaining portion of the extension region (22).

In one example, the divided portion (MS2') of the second main separation structure (MS2) may include protruding portions extending from a portion surrounding the first pad penetration area (TH1) in a direction toward the auxiliary separation structures (SS).

In one example, the divided portion (MS2') of the second main separation structure (MS2) may be placed between at least some of the auxiliary separation structures (SS).

An exemplary three-dimensional semiconductor device (10a) may include impurity regions (272) in the upper substrate (150) below the main isolation structures (MS) and the auxiliary isolation structures (SS). The impurity regions (272) may be of N-type conductivity, and a portion of the upper substrate (150) adjacent to the impurity regions (272) may be of P-type conductivity. The impurity regions (272) may be the common source line (CSL of FIGS. 1 and 2) described with reference to FIGS. 1 and 2.

An exemplary three-dimensional semiconductor device (10a) may include a second capping insulating layer (278) covering the main isolation structures (MS) and the auxiliary isolation structures (SS) on the first capping insulating layer (255). The second capping insulating layer (278) may be formed of silicon oxide.

An exemplary three-dimensional semiconductor device (10a) may include bit line contact plugs (280b) that penetrate the first and second capping insulating layers (255, 278) and are electrically connected to the vertical channel structures (VS), and gate contact plugs (280g) that penetrate the first and second capping insulating layers (255, 278) and extend onto pad regions (P) of gate electrodes of the gate stack structure (270) and are electrically connected to the pad regions (P) of the gate electrodes.

An exemplary three-dimensional semiconductor device (10a) may include peripheral contact plugs that penetrate the first and second capping insulating layers (255, 278), penetrate the first pad penetration region (TH1), and extend downward to be electrically connected to the peripheral wirings (130) of the peripheral circuit (PCIR) within the lower structure (110). The peripheral contact plugs may include gate peripheral contact plugs (284g).

The gate peripheral contact plugs (284g) may penetrate the upper substrate (150). For example, the gate peripheral contact plugs (284g) may sequentially penetrate the gate stacked structure (270) and the gapfill layer (160a) and extend into the lower structure (110) to be electrically connected to the peripheral wirings (130).

An exemplary three-dimensional semiconductor device (10a) may include upper wirings arranged on the second capping insulating layer (278). The upper wirings may include bit lines (290b) electrically connected to the bit line contact plugs (280b), and gate connection wirings (290g) electrically connected to the gate contact plugs (280g).

In one example, at least some of the gate connection wires (290g) may be electrically connected to the gate peripheral contact plugs (284g). Accordingly, at least some of the gate electrodes of the gate stacked structure (270) may be electrically connected to the peripheral circuit (PCIR) under the upper substrate (150) through the first pad through-region (TH1). Alternatively, at least some of the gate electrodes of the gate stacked structure (270) may be electrically connected to the peripheral circuit (PCIR) under the upper substrate (150) through the first pad through-region (TH1) and the second pad through-region (TH2) described with reference to FIGS. 6A and 6B.

Next, the side of the first pad penetration region (TH1) described above and the pad region (P) of the gate electrodes of the gate stacked structure (270) will be described with reference to FIGS. 8A and 8B, respectively. Each of FIGS. 8A and 8B is an enlarged partial view of the region indicated by 'A1' and 'A2' of FIG. 4. Here, the region indicated by 'A1' may represent a stepped portion (S1) of the side of the first pad penetration region (TH1) described above, and the region indicated by 'A2' may represent the pad region (P) of the gate stacked structure (270).

First, referring to FIG. 4 and FIG. 8a, the horizontal width of the stepped portion (S1) of the side of the first pad penetration area (TH1) may be smaller than the horizontal width of the pad area (P) of the gate stack structure (270).

In an illustrative example, a portion of the gate electrode of the gate stacked structure (270) positioned in the stepped portion (S1) of the side of the first pad penetration region (TH1) and the pad region (P) of the gate stacked structure (270) may have an increased thickness. For example, the gate electrode of the gate stacked structure (270) may extend to a first thickness, and may increase to a second thickness that is thicker than the first thickness in the stepped portion (S1) of the side of the first pad penetration region (TH1) and the pad region (P) of the gate stacked structure (270). However, the technical idea of the present invention is not limited thereto. For example, as shown in FIG. 8b, a portion of the gate electrode of the gate stacked structure (270) positioned in the stepped portion (S1) of the side of the first pad penetration region (TH1) and the pad region (P) of the gate stacked structure (270) may have the same thickness as another portion of the gate.

Although the description has been made mainly with reference to FIGS. 3A to 5 above, focusing on one first pad penetration region (TH1) and one second main separation structure (MS2) disposed between a pair of first main separation structures (MS1), the technical idea of the present invention is not limited thereto. For example, each of the first pad penetration regions (TH1) and the second main separation structures (MS2) may be formed in multiple numbers. An exemplary example of a three-dimensional semiconductor device (10a) including the first pad penetration regions (TH1) that may be formed in multiple numbers and the second main separation structures (MS2) that may be formed in multiple numbers will be described with reference to FIG. 9. Here, the exemplary three-dimensional semiconductor device may include all of the components described with reference to FIGS. 3A to 5. Here, since the components described with reference to FIGS. 3A to 5 have been described above, a detailed description thereof will be omitted. FIG. 9 is a plan view conceptually illustrating a modified example of a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 3A to 5 and 9, one first pad penetration area (TH1) and one second main separation structure (MS2) described in FIGS. 3A to 5 can be repeatedly arranged in either direction. Accordingly, a plurality of first pad penetration areas (TH1) can be arranged.

The above plurality of first pad penetration regions (TH1) can be repeatedly arranged in a second "??*(Y) direction perpendicular to the first direction (X) toward the extension region (22) in the memory cell array region (20) on a plane such as FIG. 9. For example, as in FIG. 9, the second pad penetration regions (TH1) can be spaced apart from each other along the second direction (Y). Each of the first pad penetration regions (TH1) can have an elongated direction along the second direction (Y).

Each of the plurality of first pad penetration areas (TH1) may be surrounded by a segmented portion (MS2') of one second main separation structure (MS2), as described with reference to FIGS. 3A to 5. Accordingly, a plurality of the second main separation structures (MS2) may be arranged in proportion to the number of the plurality of first pad penetration areas (TH1).

Accordingly, the main separation structures (MS) may include a plurality of first main separation structures (MS1) and a plurality of second main separation structures (MS2). Each of the plurality of second main separation structures (MS2) may be disposed between a pair of adjacent first main separation structures (MS1) among the plurality of first main separation structures (MS1). Accordingly, the first main separation structure (MS1) and the second main separation structure (MS2) may be repeatedly arranged in the second direction (Y). For example, each of the first main separation structures (MS1) may have a line shape extending along the first direction (X) between two adjacent first pad penetration regions (TH1), and each of the second main separation structures (MS2) may extend along the first direction and surround one of the first pad penetration regions (TH1).

Each of the plurality of first pad penetration regions (TH1) may be used to electrically connect the gate electrodes of the gate stack structure (270) with the peripheral circuit (PCIR) under the upper substrate (150), as described with reference to FIGS. 3A to 5. According to an embodiment of the present invention, a memory penetration region (TH3 of FIGS. 9 and 10A) similar to the first pad penetration region (TH1) may be used to electrically connect the bit lines (290b) described with reference to FIGS. 3A to 5 with the peripheral circuit (PCIR) disposed under the upper substrate (150). An exemplary example of a semiconductor device (10a) including such a memory penetration region (TH3 of FIGS. 9 and 10A) will be described with reference to FIGS. 3A to 5 and FIG. 9, along with FIG. 10A. FIG. 10A is a cross-sectional view schematically illustrating a region taken along line III-III' of FIG. 9. Here, the components described with reference to FIGS. 3a to 5 and FIG. 9 have been described above, so a detailed description will be omitted.

Referring to FIG. 10A together with FIGS. 3A to 5 and FIG. 9, an exemplary three-dimensional semiconductor device may include a memory penetration region (TH3) disposed between the first main separation structure (MS1) and the second main separation structure (MS2) which are adjacent to each other among the main separation structures (MS) located within the memory cell array region (20). Accordingly, the memory blocks (BLK) are repeatedly arranged in the second direction (Y), as described above, and any one of the memory blocks (BLK) repeatedly arranged in this manner may be replaced with the memory penetration region (TH3). Accordingly, any one of the memory penetration regions (TH3) may be disposed between any pair of memory blocks (BLK). The memory penetration region (TH3) may have a line shape extending in the first direction (X).

The above memory penetration region (TH3) penetrates the gate stack structure (270) and can penetrate the lower interlayer insulating layer (210L), the middle interlayer insulating layer (210M), and the upper interlayer insulating layer (210U).

As described above with reference to FIGS. 3a to 5, the first pad penetration region (TH1) may be disposed within the extension region (22). In addition, the first pad penetration region (TH1) may penetrate the lower gate electrode (GE_L), the dummy gate electrode (GE_D1), the intermediate gate electrodes (GE_M) and the buffer gate electrode (GE_D2) of the gate stack structure (270) within the buffer region (22b) between the first and second step regions (22a, 22c).

The above memory penetration region (TH3) may be arranged within the memory cell array region (20) and may penetrate through the lower gate electrode (GE_L), the dummy gate electrode (GE_D1), the intermediate gate electrodes (GE_M), the buffer gate electrode (GE_D2), and the upper gate electrode (GE_U) of the gate stack structure (270). Accordingly, the first pad penetration region (TH1) may be spaced apart from the upper gate electrode (GE_U), and the memory penetration region (TH3) may penetrate further through the upper gate electrode (GE_U) than the first pad penetration region (TH1). The memory penetration region (TH3) may be formed of the same material as the first pad penetration region (TH1), for example, silicon oxide.

The above memory penetration region (TH3) may include a lower penetration region (TH3_L) and an upper penetration region (TH3_U) on the lower penetration region (TH3_U). In the memory penetration region (TH3), the upper penetration region (TH3_U) may have a wider width than the lower penetration region (TH3_L). The memory penetration region (TH3), like the first pad penetration region (TH1), may have a side including a stepped portion (S1).

A gap fill layer (161) overlapping the memory penetration area (TH3) may be arranged below the memory penetration area (TH3). The gap fill layer (161) may be formed of an insulating material that fills a substrate hole (155b) penetrating the upper substrate (150). The gap fill layer (161) may be formed of the same insulating material as the first gap fill layer (160a), for example, silicon oxide.

A bit line peripheral contact plug (284b) may be disposed to penetrate the memory penetration region (TH3), penetrate the first and second capping insulating layers (255, 278), and the second gapfill layer (160b), and extend into the lower structure (110) to be electrically connected to the peripheral wiring (130) of the peripheral circuit (TCIR). The bit line (290b) may be electrically connected to the bit line peripheral contact plug (284b). Accordingly, the bit line (290b) may be electrically connected to the peripheral circuit (PCIR) through the bit line peripheral contact plug (284b) penetrating the memory penetration region (TH3).

In one example, the memory penetration region (TH3) may have a similar shape to the first pad penetration region (TH1), but the memory penetration region (TH3) may be deformed into various shapes. For example, the memory penetration region (TH3) may penetrate further through the upper gate electrode (GE_U) than the first pad penetration region (TH1), and thus may be deformed into a different shape from the first pad penetration region (TH1). For example, the upper gate electrode (GE_U) may be stacked in a plurality of layers in a direction perpendicular to the surface of the upper substrate (150), and the plurality of such upper gate electrodes (GE_U) may have pad regions (P) arranged in a step shape in the extension region (22). In the patterning process of forming the step-shaped pad regions (P) of the plurality of upper gate electrodes (GE_U) as described above, the upper gate electrodes (GE_U) at the positions where the memory penetration regions (TH3) are to be formed can be patterned together to expose the buffer gate electrodes (GE_D2). In this state, the memory penetration regions (TH3) can be formed by the same process as the first pad penetration regions (TH1).

Depending on the shape of the upper gate electrode (GE_U) at the position where the memory penetration region (TH3) is to be formed, which is patterned to expose the buffer gate electrode (GE_D2), the shape of the memory penetration region (TH3) can be modified in various ways. Each of FIGS. 10b and 10c is a cross-sectional view illustrating an example of modification of the memory penetration region (TH3) in FIG. 10a.

First, referring to FIG. 10b, the memory penetration region (TH3') may further include a stepped portion (S2) at an upper portion, together with the stepped portion (S1) described above. Among the stepped portions (S1, S2), the stepped portion (S1) located relatively lower may be a first step portion (S1), and the stepped portion (S2) located relatively upper may be a second step portion (S2). For example, in the upper region (TH3_U) of the memory penetration region (TH3'), the width of the upper region (TH3_U) whose width is limited by the uppermost gate electrode among the gate electrodes may be larger than the width of the upper region (TH3_U) whose width is limited by the intermediate gate electrodes (GE_M). For example, as in Fig. 10b, the memory penetration area (TH3') may have at least three vertical portions separated from each other by the first and second step portions (S1, S2). For example, the vertical portions of the memory penetration area (TH3') may have a width that increases as they go upward.

Next, referring to FIG. 10c, the memory penetration region (TH3") may have a side including a plurality of steps (S1').

The step shape and the first pad penetration region (TH1) in which the pad regions of the gate electrodes of the gate stack structure (270) described above are arranged are not limited to the above-described embodiments and may be modified in various forms. Exemplary examples in which the step shape and the first pad penetration region (TH1) may be modified will be described with reference to FIGS. 11A and 11B. FIG. 11A is a perspective view conceptually showing a modified example of a three-dimensional semiconductor device according to an embodiment of the present invention, and FIG. 11B is a cross-sectional view conceptually showing a part of FIG. 11A cut in the direction from the memory cell array region (20) toward the extension region (22). Here, the description will focus on the modified example of the step shape and the pad penetration region (TH1), and since the remaining components can be understood by being replaced with the contents described above, a detailed description will be omitted.

Referring to FIGS. 11A and 11B, the lower substrate (105), the lower structure (110), and the upper substrate (150) similar to those described above may be arranged. The gate stacked structure (370) arranged on the upper substrate (150) may include gate electrodes that are stacked while being spaced apart from each other in a direction (Z) perpendicular to the surface of the upper substrate (150). The gate electrodes of the gate stacked structure (370) may be stacked while being spaced apart from each other within the memory cell array region (20), as described above, and may extend into the extension region (22) to have pad regions (P) within the extension region (22). The gate electrodes of the above gate stack structure (370) may include a lower gate electrode (GE_L), a dummy gate electrode (GE_D1) on the lower gate electrode (GE_L), intermediate gate electrodes (GE_M) on the dummy gate electrode (GE_D1), a buffer gate electrode (GE_D2) on the intermediate gate electrodes (GE_M), and upper gate electrodes (GE_U) on the buffer gate electrode (GE_D2). The extended region (22) may include a first step region (22a), a second step region (22c), and a buffer region (22b) between the first and second step regions (22a, 22c) as described above.

The above first step region (22a) may be a region in which the pad regions (P) of the upper gate electrodes (GE_U) are sequentially lowered to form steps.

The second step region (22c) may be a region where pad regions (P) are arranged in a step shape that is lowered to a first height in a first direction toward the extension region (22) in the memory cell array region (20) and lowered to a second height smaller than the first height in a second direction perpendicular to the first direction, or in a step shape that is formed by a pongee.

The pad penetration region (TH1') can penetrate the gate stack structure (370) of the buffer region (22b). A gap fill layer (160a) can be arranged to overlap the pad penetration region (TH1') and penetrate the upper substrate (150).

The above pad penetration area (TH1') may have a side including the stepped portions (S1). Accordingly, the pad penetration area (TH1') may have a side formed by a plurality of steps. The pad penetration area (TH1') may have a shape in which the width gradually increases as it goes upward. A height difference in which the plurality of steps in the pad penetration area (TH1') decreases may be substantially the same as a height difference in which the pad areas (P) of the second step area (22c) decrease in a first direction from the memory cell array area (20) toward the extension area (22).

Next, an exemplary example in which the step shape and the pad penetration region (TH1) can be modified will be described with reference to FIG. 12. FIG. 12 is a cross-sectional view showing an example of modification of a three-dimensional semiconductor device according to an embodiment of the present invention. Here, the description will focus on an example of modification of the step shape and the pad penetration region (TH1), and the detailed description of the remaining components will be omitted because they can be understood by being replaced with the contents described above.

Referring to FIG. 12, pad regions of gate electrodes of the gate stack structure (470) may be arranged in a step shape that decreases to a first height in a direction away from the memory cell array region. The pad regions arranged in a step shape in this way may be steps of the gate electrodes.

The pad penetration region (TH1") penetrating the gate stacked structure (470) may have a shape in which the width increases as it goes upward. For example, the side of the pad penetration region (TH1") may include steps (S1) corresponding to the step shape of the gate electrodes of the gate stacked structure (470). For example, when the steps of the gate electrodes of the gate stacked structure (470) are gradually lowered to a first height, the steps of the side of the pad penetration region (TH1") may also be gradually lowered to the first height.

Next, examples of modifications of the upper substrate (150) and/or the main separation structures (MS) described above will be described with reference to FIGS. 13A and 13B. FIG. 13A is a cross-sectional view showing a region taken along line I-I' of FIG. 3A, and FIG. 13B is a cross-sectional view showing a region taken along line II-II' of FIG. 3A. Here, examples of modifications of the upper substrate (150) and/or the main separation structures (MS) will be described, and the remaining components can be understood by being replaced with the contents described above, so a detailed description thereof will be omitted.

Referring to FIGS. 13a and 13b, the upper substrate (150') may include a first region (150a) and a second region (150b) on the first region (150a). The first region (150a) may be formed of a conductive material. For example, the conductive material of the first region (150a) may include a metal nitride (e.g., TiN or WN, etc.), a metal silicide (e.g., WSi or TiSi, etc.), or a metal (e.g., W, etc.). The second region (150b) may be formed of polysilicon. For example, at least a portion of the second region (150b) may include polysilicon having an N-type conductivity type. At least a portion of the second region (150b) may be the common source line (CSL) of FIGS. 1 and 2. The first region (150a) may be spaced apart from the vertical channel structures (VS). The second region (150b) may be in contact with a portion of each of the vertical channel structures (VS).

In a variant example, the main separation structures (MS') may be formed of an insulating material. For example, the main separation structures (MS) may be formed of an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride.

As described above with reference to FIGS. 3A to 13B, in the exemplary example, a plurality of pad penetration regions (TH1) may be arranged in an extended region (22) on either side of the memory cell array region (20). However, the technical idea of the present invention is not limited thereto. A variation example of the arrangement of the pad penetration regions (TH1) will be described with reference to FIG. 14. FIG. 14 is a plan view showing a variation example of a three-dimensional semiconductor device according to an embodiment of the present invention.

Referring to FIG. 14, the extension regions (22) may be arranged on both sides of the memory cell array region (20). Accordingly, one memory cell array region (20) may be arranged between a pair of extension regions (22). The above-described first pad penetration regions (TH1) may be arranged in a zigzag pattern within the pair of extension regions (22) with the memory cell array region (20) interposed therebetween.

As described above in FIGS. 3A to 14, each of the first pad penetration regions (TH1) may be arranged to be surrounded by a divided portion (MS2') of the second main separation structure (MS2). However, the technical idea of the present invention is not limited thereto. Such a modified example will be described with reference to FIG. 15. FIG. 15 is a plan view showing a modified example of a three-dimensional semiconductor device according to an embodiment of the present invention.

Referring to FIG. 15, an extension region (22) may be arranged on both sides of a memory cell array region (20). As described above, the main separation structures (MS) may cross the memory cell array region (20) and the extension region (22). The main separation structures (MS) may be formed in a line shape that is parallel to and spaced apart from each other. The first pad penetration regions (TH1) may be arranged within the extension region (22) on either side of the memory cell array region (20). The first pad penetration regions (TH1) may be arranged between the line-shaped main separation structures (MS) within the extension region (22).

The first pad penetration regions (TH1) arranged between the main separation structures (MS) formed in a line shape like this may be arranged within an extension region (22) located on either side of the memory cell array region (20), but the technical idea of the present invention is not limited thereto and may be modified. An example of a modified arrangement shape of the first pad penetration regions (TH1) arranged like this will be described with reference to FIG. 16. FIG. 16 is a plan view showing an example of a modified arrangement of a three-dimensional semiconductor device according to an embodiment of the present invention.

Referring to FIG. 16, the first pad penetration regions (TH1) may be arranged between main separation structures (MS) formed in a line shape and may be arranged in a zigzag manner within the extension regions (22) located on both sides of the memory cell array region (20).

As described with reference to FIGS. 15 and 16, respectively, the first pad penetration regions (TH1) may be arranged between main separation structures (MS) formed in a line shape within the extension region (22). An exemplary example of the penetration region arranged between such main separation structures (MS) will be described with reference to FIG. 17. FIG. 17 is a plan view showing a modified example of a three-dimensional semiconductor device according to an embodiment of the present invention.

Referring to FIG. 17, the memory penetration region (TH3) as described in FIG. 9 may be arranged between the main separation structures (MS) formed in a line shape within the memory cell array region (20). Accordingly, the memory penetration region (TH3) may be arranged together with the first pad penetration regions (TH1) as described with reference to FIGS. 15 and 16, respectively, between the main separation structures (MS).

An exemplary example of a method for forming a structure of an exemplary three-dimensional semiconductor device described above will be described with reference to FIGS. 19 to 24, together with FIGS. 18A and 18B. FIGS. 18A and 18B are process flow diagrams showing an exemplary example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. FIGS. 19 to 24 are perspective views conceptually showing an exemplary example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. Since the material types or structures of the components mentioned below can be understood with the contents described with reference to FIGS. 3A to 5, a detailed description thereof will be omitted. Therefore, a detailed description of the main components of the semiconductor device (10a) described with reference to FIGS. 3A to 5 will be omitted below, and a description will be focused on a method for forming such main components.

Referring to FIG. 19 together with FIGS. 18a and 18b, a lower structure (110) including a peripheral circuit (PCIR) can be formed on a lower substrate (105) (S5). An upper substrate (150) can be formed on the lower structure (110) (S10). Forming the upper substrate (150) may include forming a polysilicon substrate, patterning the polysilicon substrate to form substrate holes, forming a first gapfill layer (160a) and a second gapfill layer (160b) that fill the substrate holes, and forming an intermediate insulating layer (162) on a side surface of the patterned polysilicon substrate. Here, the patterned polysilicon substrate may be the upper substrate (150).

A mold structure (205) including interlayer insulating layers (210) and sacrificial layers (207) alternately and repeatedly laminated on the upper substrate (150) can be formed (S15).

Among the interlayer insulating layers (210) and the sacrificial layers (207), the uppermost interlayer insulating layer and the uppermost sacrificial layer may be patterned to form a first step (211a). The first step (211a) may have a shape corresponding to the step shape of the gate electrode (GE_U) located at the uppermost part of the gate stack structure (270) described in FIGS. 3A to 5.

Next, among the interlayer insulating layers (210) and the sacrificial layers (207), the upper interlayer insulating layer and the upper sacrificial layer may be patterned to form a first step (211a) with an increased number of steps and uppermost mold patterns (211b). The uppermost mold patterns (211b) may be formed within an extended region (22) on the upper substrate (150) and may be spaced apart from each other.

As described in FIGS. 3A to 5, in a plane, the direction from the memory cell array region (20) toward the extension region (22) is defined as a first direction (X), the direction perpendicular to the first direction (X) is defined as a second direction (Y), and in a cross-section, the direction perpendicular to the surface of the upper substrate (150) is defined as a third direction (Z).

The mold structure (205) in the portion where the first step (211a) and the uppermost mold patterns (211b) are not formed can have a relatively lower height.

In a modified example, while etching some of the interlayer insulating layers and some of the sacrificial layers to form the first step (211a) and the uppermost mold patterns (211b), some of the interlayer insulating layers and some of the sacrificial layers of the mold structure (205) located in the memory cell array region (20) where the memory penetration region (TH3 of FIG. 9) described in FIG. 9 is to be formed can be etched together.

Referring to FIG. 20 together with FIGS. 18a and 18b, the mold structure (205) may be patterned to form steps (211c) that gradually lower in the first direction (X). Such steps (211c) may be formed starting from a portion of the uppermost mold patterns (211b) close to the memory cell array region (20) to a portion of the uppermost mold patterns (211b) that is far from the memory cell array region (20). Here, the steps (211c) that gradually lower in the first direction (X) may be lowered by the thickness of two sacrificial layers and two interlayer insulating layers. Among the steps (211c) that gradually lower in the first direction (X), the steps located in the region overlapping with the uppermost mold patterns (211b) may be relatively higher than the remaining steps. The steps may be steps of the sacrificial layers.

Referring to FIG. 21 together with FIGS. 18a and 18b, a first photoresist pattern (213) having a first through opening (213a) and a first step opening (213b) may be formed on the mold structure (205). The first through opening (213a) may be positioned between the uppermost mold patterns (211b) and the first step (211a). The first through opening (213a) may be formed at a position where the first pad through opening (TH1) described with reference to FIGS. 3a to 5 is to be formed. In a modified example, a plurality of first through openings (213a) may be formed at a position where the memory through opening (TH3 of FIG. 9) described with reference to FIG. 9 is to be formed.

Referring to FIG. 22 together with FIGS. 18a and 18b, the first photoresist pattern (213 of FIG. 21) may be used as an etching mask to partially etch the mold structure (205) to form a first through recess region (214a) and a first step recess region (214b). The first through recess region (214a) may be formed by partially etching the mold structure (205) positioned below the first through opening (213a of FIG. 21), and the first step recess region (214b) may be formed by partially etching the mold structure (205) positioned below the first step opening (213b of FIG. 21).

Referring to FIG. 23 together with FIGS. 18a and 18b, a second photoresist pattern (215) having a second through opening (215a) and second step openings (215b) can be formed on the mold structure (205). The second through opening (215a) can be formed with a larger width than the first through recess region (214a) while fully exposing the first through recess region (214a). The second step openings (215b) can be spaced apart from each other in the second direction (Y). The second step openings (215b) can be formed such that both side surfaces of the first step recess region (214b) parallel to the first direction (X) are positioned at the center portion of the second step openings (215b).

Referring to FIG. 24 together with FIGS. 18a and 18b, the second photoresist pattern (215) may be used as an etching mask to etch the mold structure (205) exposed by the second through opening (215a) and the second step openings (215b). Etching the mold structure (205) may include etching the mold structure (205) until the upper substrate (150) is exposed at one portion and/or until the first gapfill layer (160a) is exposed. The sacrificial layers (207) in the mold structure (205) formed by this process may be formed to have steps having a shape corresponding to the step shape of the pad regions of the gate electrodes of the gate electrode structure (270) described with reference to FIGS. 3a to 5. In addition, a through hole (220) can be formed by etching the mold structure (205) exposed by the second through opening (215a). A plurality of such through holes can be formed.

Accordingly, as described above, the mold structure (205) can be patterned to form the through holes and steps penetrating the mold structure (S20).

Again, referring to FIGS. 3A to 5, together with FIGS. 18A and 18B, an insulating layer may be formed that fills the through holes while covering the steps (S25). In the case where a plurality of through holes are formed, the insulating layer that fills the plurality of through holes may form the upper insulating layer (230) while forming the first pad through-hole area (TH1) and/or the memory through-hole area (TH3) as described with reference to FIGS. 3A to 5. Vertical channel structures (VS) penetrating the mold structure (205) may be formed (S30). The vertical channel structures (VS) may be the vertical channel structures (VS) as described with reference to FIGS. 3A to 5.

Next, a first capping insulating layer (255) as described with reference to FIGS. 3A to 5 may be formed, and isolation trenches penetrating the first capping insulating layer (255) and the mold structure (205) and exposing the sacrificial layers (207) may be formed (S35). The sacrificial layers (207) may be removed to form spaces (S40). Gates may be formed in the spaces (S45). The gates may be gate electrodes of the gate stack structure (270) described with reference to FIGS. 6 to 13B and the second gate dielectric (268). The impurity regions (272) described with reference to FIGS. 3A to 5 may be formed below the isolation trenches. Isolation structures may be formed in the isolation trenches (S50). The above separation structures may be the main separation structures (MS) and the auxiliary separation structures (SS) described with reference to FIGS. 3 to 13b.

Next, the second capping insulating layer (278) described with reference to FIGS. 3A to 5 may be formed. Next, the insulating layer in the through hole, i.e., the through region (TH1) and peripheral contact plugs that penetrate the upper substrate (150) and are electrically connected to the peripheral circuit (PCIR), may be formed (S55). The peripheral contact plugs may be gate peripheral contact plugs (284g) and/or bit line peripheral contact plugs (284b). Next, upper wirings such as those described with reference to FIGS. 3A to 5 may be formed. The upper wirings may be gate connection wirings (290g) and bit lines (290b).

Next, with reference to FIGS. 25a to 31b, an exemplary example of a method for forming the width of the steps in one direction described in FIGS. 3 to 13b and the width of the stepped portion of the through area in one direction are different sizes from each other will be described. In FIGS. 25a to 31b, FIGS. 25a, 26a, 27a, 28a, 29a, 30a, and 31a are cross-sectional views conceptually illustrating a portion of a step area (STR) to illustrate an exemplary example of a method for forming a portion of steps, and FIGS. 25b, 26b, 27b, 28b, 29b, 30b, and 31b are cross-sectional views conceptually illustrating a portion of a through area to illustrate an exemplary example of a method for forming one side of the through area (THR). It can be understood that in the exemplary method of forming a three-dimensional semiconductor device described with reference to FIGS. 18a to 24 described above, the shape and size of the gate electrodes and the penetration regions are determined according to the patterned shape of the sacrificial layers (207) of the mold structure (205). Therefore, although the method of patterning the sacrificial layers (207) will be mainly described below, the shape of the penetration regions penetrating the gate electrodes of the three-dimensional semiconductor device described above and the steps of the gate electrodes can be understood from this method.

First, referring to FIGS. 25a and 25b, an upper substrate (150) having a first gapfill layer (160a) formed thereon can be prepared. A mold structure (205) including interlayer insulating layers (210) and sacrificial layers (207) that are alternately and repeatedly laminated can be formed on the upper substrate (150). A first photoresist pattern (415a) can be formed on the mold structure (205). A portion of the mold structure (205) can be etched using the first photoresist pattern (415a) as an etching mask. Although FIGS. 25a and 25b illustrate that four sacrificial layers (207) that are sequentially laminated are etched, the technical idea of the present invention is not limited thereto. For example, depending on the desired step shape to be formed, one sacrificial layer may be etched, or a different number of sacrificial layers may be etched.

Referring to FIGS. 26a and 26b, portions of the mold structure (205) may be stepwise etched while gradually reducing the size of the first photoresist patterns (415a) to form first pad steps (416a) and first through steps (417a). The first photoresist patterns (415a, 415b, 415c, 415d) whose sizes are gradually reduced may be reduced in size according to the size of the width of the steps to be formed.

The first photoresist patterns (415a, 415b, 415c, 415d) whose sizes are gradually reduced above can be removed after the first pad steps (416a) and the first through steps (417a) are formed.

Referring to FIGS. 27a, 28a, 29a, 30a and 27b, 28b, 29b and 30b, a second photoresist pattern (420a) is formed on a mold structure (205) on which the first pad steps (416a) and the first through steps (417a) are formed, and a step formation process can be performed using substantially the same method as the method described with reference to FIGS. 25a to 26b.

Similarly to the first photoresist patterns (415a, 415b, 415c, 415d of FIGS. 25a to 26b) whose sizes are gradually reduced as described above in FIGS. 25a to 26b, second photoresist patterns (420a, 420b, 420c, 420d) whose sizes are gradually reduced can be sequentially formed, and an etching process using each of the second photoresist patterns (420a, 420b, 420c, 420d) whose sizes are gradually reduced in this way as etching masks can be performed to stepwise etch a portion of the mold structure (205).

The second photoresist patterns (420a, 420b, 420c, 420d) whose sizes are gradually reduced above may be formed so as not to overlap the first pad steps (416a) and may be formed so as to partially overlap the first through steps (417a).

Accordingly, second pad steps (416b) that do not overlap with the first pad steps (416a) are formed by the second photoresist patterns (420a, 420b, 420c, 420d) whose sizes are gradually reduced, so that pad steps (425a) composed of the first and second pad steps (416a, 416b) can be formed.

Additionally, through-steps (421b) having a horizontal width smaller than that of the first through-steps (417a) can be formed by the second photoresist patterns (420a, 420b, 420c, 420d) whose sizes are gradually reduced.

Additionally, in the above-described through steps (421b), the horizontal length (L2) between the top step and the bottom step may be smaller than the horizontal length (L1) between the top step and the bottom step in the above-described pad steps (425a).

According to an embodiment of the present invention, a three-dimensional semiconductor device may include, as described above, the memory cell array region (20), extension regions (22) on one or both sides of the memory cell array region (20), main isolation structures (MS) that extend across the memory cell array region (20) and the extension regions (22) and define memory blocks (BLK), gate stacked structures (270, 370) that are arranged in the memory blocks (BLK) and extend into the extension regions (22), vertical channel structures (VS) that are arranged between the main isolation structures (MS) and penetrate the gate stacked structure (270) in the memory cell array region (20), and at least one through region (TH1, TH3) that is arranged in the memory cell array region (20) or the extension regions (22) and penetrates the gate stacked structure (270). The above-described penetration area (TH1, TH3) can have a side including at least one step (S1, S2, S, S'). Here, the steps (S1, S2, S, S') of the side of the penetration area (TH1, TH3) can be described as a stepped portion. The above-described penetration area (TH1, TH3) can have a lower region and an upper region on the lower region. Here, the upper region of the penetration area (TH1, TH3) can have a larger width than the lower region.

In embodiments, the through-regions (TH1, TH3) may be formed using a process for forming pad regions (P) of the gate stack structure (270). Accordingly, a separate process for forming the through-regions (TH1, TH3) may be omitted, thereby reducing production costs and improving productivity of semiconductor devices. In addition, since the through-regions (TH1, TH3) may have a width that gradually increases in a vertical direction away from the upper substrate (150), the insulating material constituting the through-regions (TH1, TH3) may be formed without defects such as voids.

Above, while the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

BLK: Memory Block MC: Memory Cell
WL: Wordline BL: Bitline
CSL: Common Source Line SSL: String Selection Line
S: memory string DS: dummy string
20: Memory cell array area 22: Extension area
22a: 1st step area 22b: Buffer area
22c: 2nd step area 105: lower substrate
110 : Substructure 115 : Isolation area
120 : Active Area PTR : Peripheral Transistor
130: Peripheral wiring PCIR: Peripheral circuits
140 : Lower insulation layer 150 : Upper substrate
155a, 155b: substrate hole 160a, 160b, 161: gap fill layer
162: Middle insulation layer 270, 370: Gate laminate structure
GE_L: Lower gate electrode GE_D1: Dummy gate electrode
GE_D2: Buffer gate electrode GE_M: Middle gate electrodes
GE_U : Top gate electrode 205 : Mold structure
207: Sacrificial layer 210L: Lower interlayer insulation layer
210M: Middle interlayer insulation layer 210U: Upper interlayer insulation layer
210: Interfloor insulation layer 211a: First staircase
211b: Top mold pattern 213, 313, 215: First photoresist pattern
213a: First through-hole opening 213b: First stair opening
214a: First through-hole recess area 214b: First step recess area
215a: Second through opening 215b: Second stair opening
TH1: 1st pad penetration area TH1_L: Lower penetration area
TH1_U: Upper penetration area TH2: Second pad penetration area
TH3: Memory penetration area SG1: 1st step group
SG2: 2nd step group SG3: 3rd step group
DA: Dummy area 230: Upper insulation layer
232: Insulating Line VS: Vertical Channel Structure
235: Lower channel semiconductor layer 240: First gate dielectric
242: Tunnel dielectric 243: Information storage layer
244: Blocking dielectric 246, 246': Channel semiconductor layer
248: Insulating core layer 250: Pad layer
255: First capping insulating layer 268: Second gate dielectric
MS: Main Separation Structures MS1: First Main Separation Structure
MS2: Second main separation structure MS2': Divided part
SS: Auxiliary separation structures 272: Impurity region
274 : Spacer 276 : Challenge Pattern
278: Second capping insulation layer 280g: Gate contact plugs
280b: Bitline contact plugs 284g: Gate peripheral contact plugs
284b: Bitline peripheral contact plug 290b: Bitline
290g: Gate connection wiring 415a - 415d: Photoresist patterns
416a: 1st pad steps 417a: 1st through steps

Claims (20)

upper substrate;
A gate stack structure disposed on the upper substrate and including gate electrodes, the gate electrodes being stacked while being spaced apart from each other in a vertical direction perpendicular to a surface of the upper substrate within a memory cell array region and extending into an extension region adjacent to the memory cell array region and having pad regions arranged in a step shape within the extension region;
At least one through-hole region penetrating the gate stack structure in the vertical direction within the extended region;
Main separation structures defining each memory block across the memory cell array region and the extended region; and
A vertical channel structure is disposed between the above main separation structures and within the memory cell array region, and penetrates the gate stack structure in the vertical direction.
wherein said at least one penetration region comprises a lower region and an upper region over said lower region, said upper region having a width greater than that of said lower region;
A side of at least one of the above penetration areas comprises a stepped portion,
A three-dimensional semiconductor device wherein at least one of the penetration regions is positioned between the main separation structures.
upper substrate;
A lower substrate disposed below the upper substrate;
A lower structure disposed between the lower substrate and the upper substrate and including a peripheral circuit; and
A gapfill layer disposed within a substrate hole penetrating the upper substrate;
A laminated structure disposed on the upper substrate and including gate electrodes, the gate electrodes being laminated while being spaced apart from each other in the vertical direction within a memory cell array region and having pad regions extending into an extension region adjacent to the memory cell array region in a first direction and arranged in a step shape within the extension region;
Separating structures penetrating the above laminated structure in the vertical direction;
A vertical channel structure disposed between the above separation structures and penetrating the above laminated structure in the vertical direction;
A penetration region disposed between the separation structures within the extended region, penetrating the laminated structure in the vertical direction, and vertically overlapping the gapfill layer; and
Including a peripheral contact plug penetrating the above penetration area in the vertical direction,
A three-dimensional semiconductor device wherein the above separation structures include portions spaced apart from each other in the first direction within the extended region between the memory cell array region and the through region.
In the second paragraph,
A three-dimensional semiconductor element including a stepped portion on the side of the above penetration region.
In the third paragraph,
A three-dimensional semiconductor device in which the stepped portion is closer to the lower surface of the laminated structure than to the upper surface of the laminated structure.
In paragraph 1,
The side of said at least one penetration area is formed in a step shape,
A three-dimensional semiconductor device in which the at least one through-hole region has a width that gradually increases toward the top of the at least one through-hole region according to the step shape of the side.
upper substrate;
A gate stack structure disposed on the upper substrate and including gate electrodes, the gate electrodes being stacked while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate within a memory cell array region and extending into an extension region adjacent to the memory cell array region and having pad regions arranged in a step-like shape within the extension region; and
At least one through-hole region penetrating the gate stack structure within the memory cell array region or the extended region,
wherein said at least one penetration region comprises a lower region and an upper region over said lower region, said upper region having a width greater than that of said lower region;
The above extension region includes a first step region, a second step region, and a buffer region between the first and second step regions,
A three-dimensional semiconductor device wherein at least one of the through-hole regions comprises a first pad through-hole region penetrating the gate stack structure of the buffer region.
In paragraph 6,
Among the above pad regions, the pad regions arranged in the first step region have a lower height in the first direction from the memory cell array region toward the extension region and are arranged at the same height in the second direction perpendicular to the first direction.
A three-dimensional semiconductor device in which, among the above pad regions, at least some of the pad regions arranged in the second step region have a height that decreases as they go in the first direction and are arranged at different heights in the second direction.
In paragraph 7,
Among the above gate electrodes, the gate electrodes having the pad regions arranged in the first step region include upper selection gate electrodes,
Among the above gate electrodes, the gate electrodes having the pad regions arranged in the second step regions include word lines,
A three-dimensional semiconductor device in which the first pad penetration region is positioned between the pad regions of the upper selection gate electrodes and the pad regions of the word lines.
Substructure containing peripheral circuits;
A laminated structure disposed on the above-described lower structure and including gate electrodes, the gate electrodes being laminated while being spaced apart from each other in the vertical direction within a memory cell array region and having pad regions extending into an extension region adjacent to the memory cell array region in a first direction and arranged in a step shape within the extension region;
Separating structures penetrating the above laminated structure in the vertical direction;
Penetration regions penetrating the laminated structure in the vertical direction within the extended region;
A vertical channel structure disposed between the separation structures within the memory cell array region and penetrating the stacked structure in the vertical direction; and
Including peripheral contact plugs penetrating the above penetration areas in the vertical direction,
The above penetration regions include a first penetration region and a second penetration region spaced apart from each other in the first direction,
A three-dimensional semiconductor device wherein the above separation structures include first portions spaced apart from each other in the first direction between the first through-hole region and the second through-hole region.
In Article 9,
a bit line extending in a direction intersecting the above separation structures; and
Further comprising a bitline contact plug electrically connecting the bitline and the vertical channel structure between the bitline and the vertical channel structure,
A three-dimensional semiconductor device wherein the above separation structures further include second portions spaced apart from each other within the extension region between the first through-hole region and the memory cell array region.
In Article 10,
A three-dimensional semiconductor device wherein the above penetration regions further include a memory penetration region disposed between a pair of adjacent separation structures among the separation structures within the memory cell array region.
lower substrate;
A substructure disposed on the lower substrate and including peripheral circuitry;
An upper substrate disposed on the above lower structure;
A gapfill layer within the substrate hole within the upper substrate;
A gate stacked structure disposed on the upper substrate, the gate stacked structure including gate electrodes that are vertically stacked within a memory cell array region and spaced apart from each other, extending within an extension region adjacent to the memory cell array region, and arranged to have a step shape within the extension region;
A first through-hole region and a second through-hole region each vertically penetrating the gate stack structure within the extended region;
Main separation structures defining each memory block across the memory cell array region and the extended region; and
A vertical channel structure is disposed between the above main separation structures and within the memory cell array region, and penetrates the gate stack structure in the vertical direction.
The side of the penetration region adjacent to the gate stack structure includes a stepped portion,
The first penetration region and the second penetration region are spaced apart from each other in the first direction,
The above first direction is a direction away from the memory cell array region,
A three-dimensional semiconductor device wherein the first through-hole region and the second through-hole region are positioned between the main separation structures.
In Article 12,
The above penetration area includes a lower area and an upper area above the lower area,
A three-dimensional semiconductor device wherein the upper region has a larger width than the lower region.
In Article 12,
A peripheral contact plug extending through the above penetration region and the gapfill layer and into the lower structure to be electrically connected to the peripheral circuit; and
Including the gate stack structure and upper wirings on the penetration region,
A three-dimensional semiconductor device, wherein at least one of the upper wirings is electrically connected to the peripheral contact plug.
In Article 14,
The upper wirings include upper gate wirings electrically connected to pad regions of the gate electrodes, and bit lines electrically connected to the vertical channel structures,
A three-dimensional semiconductor device, wherein at least some of the upper gate wirings or the bit lines are electrically connected to the peripheral contact plug.
memory cell array area;
An extended region adjacent to the memory cell array region in the first direction;
Main separation structures crossing the above memory cell array region and the extension region;
A gate stack structure disposed within the memory cell array region and extending into the extension region;
Auxiliary separation structures between the above main separation structures;
Vertical channel structures disposed between the above main separation structures and vertically penetrating the gate stack structure within the memory cell array region; and
At least one through-hole region disposed within the extended region and penetrating the gate stack structure in the vertical direction,
A side of said at least one penetration region comprises at least one step,
wherein at least one of the above penetration regions is disposed between the main separation structures,
The above auxiliary separation structures penetrate the above gate stack structure in the vertical direction,
Each of the above auxiliary separation structures is formed with a shorter length than each of the above main separation structures,
A three-dimensional semiconductor device, wherein the above auxiliary separation structures include a first auxiliary separation structure and a second auxiliary separation structure spaced apart from the first auxiliary separation structure in the first direction.
In Article 16,
lower substrate;
A substructure disposed on the lower substrate and including peripheral circuitry;
an upper substrate on the above substructure; and
Further comprising a gap fill layer within the substrate hole penetrating the upper substrate,
The above gap fill layer overlaps the above penetration area,
The above gate stack structure and the above main separation structures are arranged on the upper substrate,
The above gate stack structure includes gate electrodes that are stacked and spaced apart from each other in the vertical direction perpendicular to the surface of the upper substrate within the memory cell array region and extend into the extension region,
The above gate electrodes include pad regions arranged in a step shape within the extended region,
A three-dimensional semiconductor device wherein the width of the step in the above penetration region is smaller than the width of any one of the above pad regions.
memory cell array area;
Extension regions on both sides of the above memory cell array region;
Main separation structures crossing the above memory cell array region and the extension regions;
A gate stack structure disposed within the memory cell array region and extending into the extension regions;
Vertical channel structures disposed between the above main separation structures and penetrating the gate stack structure within the memory cell array region; and
At least one through-hole region disposed within the memory cell array region or the extended regions and penetrating the gate stack structure,
The above penetration region has a side including at least one step,
The above main separation structures include a pair of first main separation structures adjacent to each other and a second main separation structure disposed between the pair of first main separation structures,
The above penetration region is disposed between the pair of first main separation structures and within at least one of the extension regions,
A three-dimensional semiconductor device wherein the second main separation structure includes a portion divided so as to cross the memory cell array region in a single line shape and surround the through region within at least one of the extension regions.
In Article 18,
Further comprising auxiliary separation structures between the above main separation structures,
The above auxiliary separation structures are arranged within the memory cell array region and the extension regions.
A three-dimensional semiconductor device in which each of the above auxiliary separation structures is formed with a shorter length than each of the above main separation structures.
In Article 16,
The above gate stack structure includes gate electrodes,
The above gate electrodes include a lower gate electrode, intermediate gate electrodes on the lower gate electrode, a buffer gate electrode on the intermediate gate electrodes, and one or more upper gate electrodes on the buffer gate electrode,
The one or more upper gate electrodes have an upper pad region within the extended region,
The above intermediate gate electrodes have intermediate pad regions within the extended region,
A three-dimensional semiconductor element in which the above penetration region is positioned between the upper pad region and the middle pad region and penetrates the buffer gate electrode.

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