KR102733505B1 - Pseudo-static random access memory - Google Patents

Abstract

[Task] Provide a pseudo-static random access memory capable of reliably executing a refresh operation in response to each of one or more refresh requests generated during a transaction.
[Solution] A pseudo-static random access memory has a control unit (10) that controls, when a memory refresh request is generated during a first transaction, to execute a memory refresh operation as many times as the number of refresh requests generated during the first transaction between the end of the first transaction and the start of a second transaction after the first transaction.

Description

Pseudo-static random access memory {PSEUDO-STATIC RANDOM ACCESS MEMORY}

The present invention relates to a pseudo-static random access memory (pSRAM).

pSRAM is a semiconductor memory device having an interface compatible with SRAM (Static Random Access Memory) (e.g., Patent Document 1).

Referring to Fig. 1, an example of a refresh operation in a conventional pSRAM is described. In the example shown in Fig. 1, when a chip select signal (CS#) transitions from negate (high level) to assert (low level), a read or write transaction is initiated. Then, when an access signal (RD/WR) for accessing data to a memory cell array transitions from negate (low level) to assert (high level), a read or write access of data to the memory cell array is performed. Thereafter, when the chip select signal (CS#) transitions from assert (low level) to negate (high level), the read or write transaction is terminated. Then, when the access signal (RD/WR) transitions from assert (high level) to negate (low level), the read or write access of data to the memory cell array is terminated.

In addition, inside the pSRAM, a refresh request signal (Ref request) for requesting a refresh operation is generated at a predetermined generation interval (tREFI). Here, the pSRAM is configured to perform a refresh operation by immediately asserting (at a high level) the refresh signal (REF) for performing the refresh operation when the refresh request signal (Ref request) is generated (at a high level) while the chip select signal (CS#) is negated (at a high level). On the other hand, if the pSRAM generates the refresh request signal (Ref request) (at a high level) while the chip select signal (CS#) is asserted (at a low level) (during a read or write access), the pSRAM waits for execution of the refresh operation because a read or write access is being performed. And, pSRAM performs a refresh operation when the chip select signal (CS#) is negated (high level) and the access signal (RD/WR) transitions from asserted (high level) to negated (low level).

JP 2020-135914 A

In such pSRAMs, if the period (tCSL) during which the chip select signal (CS#) is asserted (low level) is longer than the generation interval (tREFI) of the refresh request signal (Ref request) (i.e., tCSL > tREFI), there is a concern that the refresh operation will not be performed because the refresh request is ignored. For example, in the example shown in Fig. 1, two refresh request signals (Ref request) are generated during the period (tCSL) during which the chip select signal (CS#) is asserted (low level), but the refresh operation can be performed only once while the chip select signal (CS#) is negated (high level), so the second refresh request is ignored. As a result, since the refresh operation is not performed in response to each of one or more refresh requests generated during the transaction, it may become difficult to retain data.

On the other hand, when tCSL<tREFI, it is possible to suppress the refresh request from being ignored. However, in this case, since the period (tCSL) during which the chip select signal (CS#) is asserted (low level) is shortened, the amount of data that can be transmitted and received in one transaction is reduced. There is a concern that the data transfer rate may be reduced due to this.

In order to solve the above problem, the present invention provides a pseudo-static random access memory having a control unit that, when a memory refresh request is generated during a first transaction, controls a refresh operation of the memory to be executed as many times as the number of refresh requests generated during the first transaction between the end of the first transaction and the start of a second transaction after the first transaction.

According to this invention, during the period between the end of the first transaction and the start of the second transaction, the refresh operation is executed as many times as the number of refresh requests generated during the first transaction. As a result, even if, for example, the period during which the chip select signal is asserted (low level) is longer than the generation interval of the refresh request signal, the refresh operation can be reliably executed in response to each of one or more refresh requests generated during the first transaction. Therefore, the data retention characteristic can be maintained.

According to the pseudo-static random access memory of the present invention, a refresh operation can be reliably executed in response to each of one or more refresh requests generated during a transaction.

Figure 1 is a time chart showing an example of the time course of a signal in a conventional pSRAM.
FIG. 2 is a block diagram showing an example of a configuration of a pSRAM according to the first embodiment of the present invention.
Fig. 3 is a time chart showing an example of the time course of a signal in a pSRAM according to the first embodiment.
FIG. 4 is a block diagram showing an example of a configuration of a pSRAM according to a second embodiment of the present invention.
Fig. 5 is a time chart showing an example of the time course of a signal in a pSRAM according to the second embodiment.

(First embodiment)

Fig. 2 is a block diagram showing an example of a configuration of a pSRAM (pseudo-static random access memory) (10) according to a first embodiment of the present invention. The pSRAM (10) is configured to execute a refresh operation of the memory as many times as the number of refresh request signals (Ref_request) generated during the first transaction, between the end of the first transaction and the start of a second transaction after the first transaction, when a refresh request signal (Ref_request) of the memory is generated during the first transaction.

In addition, the pSRAM according to the present embodiment may be a clock-synchronous pseudo-static random access memory in which a signal is input or output in synchronization with a clock signal. In addition, the pSRAM according to the present embodiment may be a pSRAM of an address data multiplex interface type having an address data terminal configured so that each of an address signal and a data signal is input.

As shown in Fig. 2, pSRAM (10) has an oscillator (11), a control unit (12), an arbiter (13), and a command generation unit (14).

The generator (11) generates a refresh request signal (Ref_request) at predetermined intervals (e.g., the generation interval (tREFI) shown in Fig. 1) and outputs it to the control unit (12).

The control unit (12) is equipped with a counter (12a), a counter (12b), a comparator (12c), an inverter (12d), and an AND circuit (12e).

The counter (12a) is configured to count the number of refresh request signals (Ref_request). Specifically, the counter (12a) counts the number of input refresh request signals (Ref_request) each time a refresh request signal (Ref_request) is input from the oscillator (11). Then, the counter (12a) outputs a signal (Cnt_req) indicating the number of refresh request signals (Ref_request) to the comparator (12c).

Additionally, the value of the signal (Cnt_req) may be reset to an initial value (e.g., 0) whenever a transaction is initiated (the chip select signal (CS#) transitions from negated (high level) to asserted (low level)).

The counter (12b) is configured to count the number of refresh operations executed between the end of the first transaction and the start of the second transaction. Specifically, the counter (12b) counts the number of input refresh signals (REF) each time a refresh signal (REF) for executing the refresh operation is input from the command generation unit (14). Then, the counter (12b) outputs a signal (Cnt_exe) indicating the number of refresh signals (REF) to the comparator (12c).

Additionally, the value of the signal (Cnt_exe) may be reset to an initial value (e.g., 0) whenever a transaction ends (the chip select signal (CS#) transitions from asserted (low level) to negated (high level)).

The comparator (12c) is configured to compare the number of refresh request signals (Ref_request) counted by the counter (12a) with the number of refresh signals (REF) counted by the counter (12b). Specifically, the comparator (12c) compares the value of the signal (Cnt_req) input from the counter (12a) with the value of the signal (Cnt_exe) input from the counter (12b). Then, the comparator (12c) outputs a high-level output signal to the AND circuit (12e) when Cnt_req > Cnt_exe. On the other hand, the comparator (12c) outputs a low-level output signal to the AND circuit (12e) when Cnt_req ≤ Cnt_exe.

The inverter (12d) logically inverts the refresh signal (REF) input from the command generation unit (14) and outputs the logically inverted signal to the AND circuit (12e).

An output signal output from a comparator (12c) is input to one input terminal of an AND circuit (12e). In addition, a signal output from an inverter (12d) is input to the other input terminal of the AND circuit (12e). The AND circuit (12e) performs an AND operation based on the input signal, and outputs a signal (Cmp_ref) which is the result of the operation to the arbiter (13). Here, the signal (Cmp_ref) is an example of a "refresh control signal" of the present invention.

The arbiter (13) arbitrates (adjusts) between the chip select signal (CS#) and the signal (Cmp_ref) and adjusts the timing at which the signal (Cmp_ref) is output to the command generation unit (14). In addition, in the present embodiment, the arbiter (13) is configured to output the refresh control signal (signal (Cmp_ref)) to the command generation unit (14) every time the refresh control signal (signal (Cmp_ref)) is input from the control unit (12) between the end of the first transaction and the start of the second transaction.

Specifically, the arbiter (13) may output a high-level signal (Cmp_ref) to the command generation unit (14) if a high-level signal (Cmp_ref) is input from the control unit (12) while the chip select signal (CS#) is negated (at a high level) (i.e., between the end of the first transaction and the start of the second transaction). In addition, the arbiter (13) may not output a high-level signal (Cmp_ref) to the command generation unit (14) if a high-level signal (Cmp_ref) is input from the control unit (12) while the chip select signal (CS#) is asserted (at a low level) (i.e., during a transaction).

The command generation unit (14) generates a refresh signal (REF) for executing a refresh operation based on the control by the control unit (12). In addition, each time the command generation unit (14) generates a refresh signal (REF), it outputs the refresh signal (REF) to the counter (12b). Specifically, when the chip select signal (CS#) is negated (high level) and the access signal (RD/WR) for accessing data to the memory cell array is low level, the command generation unit (14) generates a high-level refresh signal (REF) when a high-level signal (Cmp_ref) is input from the arbiter (13) and outputs it to the memory cell array (not shown) and the counter (12b) and inverter (12d) of the control unit (12).

In addition, when a read or write command is input from the outside during each transaction (while the chip select signal (CS#) is asserted (low level)), the command generation unit (14) generates a high level access signal (RD/WR) and outputs it to the memory cell array.

In addition, when a high-level refresh signal (REF) is input to the memory cell array, a refresh operation of the memory is executed, and when a high-level access signal (RD/WR) is input to the memory cell array, a read or write process of data for the memory cell array is performed.

Next, a refresh operation in the pSRAM according to the present embodiment will be described with reference to Fig. 3. In addition, as an example, a case in which the period (tCSL) during which the chip select signal (CS#) is asserted (low level) is longer than the generation interval (tREFI) of the refresh request signal (Ref_request) will be described.

First, when a read or write command is input from the outside after the chip select signal (CS#) transitions from negate (high level) to assert (low level) and the first transaction is initiated, the command generation unit (14) generates a high-level access signal (RD/WR) and outputs it to the memory cell array.

Here, at time t1, when a high-level refresh request signal (Ref_request) is generated by the oscillator (11), the counter (12a) of the control unit (12) increases the count value for counting the refresh request signal (Ref_request) from 0 to 1 and outputs a signal (Cnt_req) indicating that the count value is 1 to the comparator (12c). In addition, the comparator (12c) compares the value of the signal (Cnt_req) with the value of the signal (Cnt_exe) (here, the case of 0 is assumed), and since the value of the signal (Cnt_req) is greater than the value of the signal (Cnt_exe), the comparator outputs a high-level output signal to the AND circuit (12e). In addition, the AND circuit (12e) performs an AND operation on the output signal from the comparator (12c) and the signal output from the inverter (12d) (since the initial refresh signal (REF) is at a low level, the signal output from the inverter (12d) becomes a high level) and outputs a high level signal (Cmp_ref) to the arbiter (13).

Here, since the chip select signal (CS#) is asserted (low level) at time t1, the arbiter (13) does not output the received high level signal (Cmp_ref) to the command generation unit (14). In addition, as described above, the command generation unit (14) generates a high level access signal (RD/WR) and outputs it to the memory cell array.

Next, at time t2 after a predetermined interval (tREFI) from time t1, when a high-level refresh request signal (Ref_request) is generated by the oscillator (11), the counter (12a) of the control unit (12) increases the count value from 1 to 2 and outputs a signal (Cnt_req) indicating that the count value is 2 to the comparator (12c). Furthermore, since the value of the signal (Cnt_req) is greater than the value of the signal (Cnt_exe), the comparator (12c) outputs a high-level output signal to the AND circuit (12e). Furthermore, the AND circuit (12e) outputs a high-level signal (Cmp_ref) to the arbiter (13), as in the case of time t1. Then, the operations of the arbiter (13) and the command generation unit (14) at time t2 are the same as those at time t1.

When the chip select signal (CS#) transitions from assert (low level) to negate (high level) after time t2, the arbiter (13) outputs a high-level signal (Cmp_ref) to the command generation unit (14). On the other hand, when the access signal (RD/WR) becomes low level at time t3, the command generation unit (14) generates a high-level refresh signal (REF) according to the high-level signal (Cmp_ref) input from the arbiter (13) at time t4, and outputs it to the memory cell array and the counter (12b) and inverter (12d) of the control unit (12).

When a high-level refresh signal (REF) is input, the counter (12b) of the control unit (12) increases the count value from 0 to 1 and outputs a signal (Cnt_exe) indicating that the count value is 1 to the comparator (12c). In addition, at time t4, since the value of the signal (Cnt_req) is still greater than the value of the signal (Cnt_exe), the comparator (12c) outputs a high-level output signal to the AND circuit (12e). In addition, the signal (Cmp_ref) output from the AND circuit (12e) becomes a low level when a high-level refresh signal (REF) is output from the command generation unit (14), but becomes a high level again when the refresh operation is completed and the refresh signal (REF) becomes a low level. At this time, the arbiter (13) outputs a high level signal (Cmp_ref) to the command generation unit (14).

Then, at time t5 after a period (tRFC) (refresh interval) has elapsed from time t4, the command generation unit (14) generates a high-level refresh signal (REF) again according to the high-level signal (Cmp_ref) input from the arbiter (13), and outputs it to the memory cell array and the counter (12b) and inverter (12d) of the control unit (12). Here, when the high-level refresh signal (REF) is input, the counter (12b) of the control unit (12) increases the count value from 1 to 2, and outputs a signal (Cnt_exe) indicating that the count value is 2 to the comparator (12c). In addition, since the value of the signal (Cnt_req) and the value of the signal (Cnt_exe) are equal, the comparator (12c) outputs a low-level output signal to the AND circuit (12e). In this case, when the signal (Cmp_ref) becomes low level and then the refresh signal (REF) transitions to low level again, the signal (Cmp_ref) output from the AND circuit (12e) maintains the low level. Then, after executing two refresh operations according to two refresh request signals (Ref_request) generated during the transaction, the transaction ends.

Also, in the example shown in Fig. 3, after the chip select signal (CS#) transitions from a low level to a high level and then becomes low again after a period (tCSH) has elapsed, the second transaction is initiated. However, in this example, at the time when the second transaction is initiated, the second refresh operation is in full swing. Therefore, the command generation unit (14) may wait until the second refresh operation is completed (the second refresh signal (REF) transitions to a low level) before asserting the access signal (RD/WR) in response to the initiation of the second transaction (high level).

As described above, according to the pSRAM of the present embodiment, even if, for example, the period (tCSL) during which the chip select signal (CS#) is asserted (low level) is longer than the generation interval (tREFI) of the refresh request signal (Ref_request), the refresh operation can be reliably executed in response to each of one or more refresh requests generated during the transaction. In addition, in this case, it is possible to suppress a decrease in the data transfer rate and maintain the data retention characteristic.

(Second embodiment)

Hereinafter, a second embodiment of the present invention will be described. The pSRAM of this embodiment differs from the first embodiment in that it has a plurality of memory banks that are accessed in an interleaved manner. Hereinafter, a configuration different from the first embodiment will be described.

In the present embodiment, the pSRAM (10) has a plurality of memory banks (20) (for example, n (n is an integer greater than or equal to 2)) accessed in an interleaved manner, as shown in Fig. 4. Each memory bank (20) has a control unit (12), an arbiter (13), and a command generation unit (14).

In the present embodiment, when a memory bank (20) selected from among a plurality of memory banks (20) is accessed in the first transaction and a memory refresh request is generated during the first transaction, the control unit (12) of each memory bank (20) controls the refresh operation in the selected memory bank (20). Specifically, after the first transaction is terminated, the control unit (12) of the memory bank (20) controls to execute the refresh operation corresponding to the number of refresh request signals (Ref_request) generated during the first transaction, and the control unit (12) of the memory bank (20) other than the selected memory bank (20) controls to execute the refresh operation in the control unit (12) of the other memory bank (20) in the first transaction in response to the generated refresh request signals (Ref_request).

For example, in the first transaction, if the i-th (0 ≤ i ≤ n-1) memory bank (20) among the plurality of memory banks (20) is accessed and a memory refresh request is generated during the first transaction, in the i-th memory bank (20), after the first transaction is terminated, a refresh operation corresponding to the number of refresh request signals (Ref_request) generated during the first transaction is executed. Meanwhile, a refresh operation in a memory bank (20) other than the i-th among the plurality of memory banks (20) is executed during the first transaction in response to the generated refresh request signals (Ref_request).

It should be noted that in the present embodiment, a plurality of memory banks (20) are accessed in an interleaved pattern. Therefore, in one example, when a refresh operation is performed on the i-th memory bank (20) after the first transaction is terminated, access to other memory banks (20) can be performed simultaneously, thereby improving the processing performance of the pSRAM. However, in another example, the present invention, as shown in the first embodiment, performs only the refresh operation on the i-th memory bank (20) between the termination of the first transaction and the start of the second transaction, and it is possible to start the second transaction after the refresh operation on the i-th memory bank (20) is terminated.

In this embodiment, the arbiter (13) of each memory bank (20) receives, in addition to the chip select signal (CS#) and the signal (Cmp_ref), a bank address signal (Bank address). In this case, the arbiter (13) may operate in the same manner as in the first embodiment when the input bank address signal (Bank address) indicates the memory bank in which it is installed. In addition, the bank address signal (Bank address) may be generated by, for example, an address decoder circuit (not shown) installed in the pSRAM (10).

In addition, in this embodiment, the command generation unit (14) of each memory bank (20) receives a bank address signal (Bank address) in addition to the chip selection signal (CS#) and the signal (Cmp_ref). In this case, the command generation unit (14) may operate in the same manner as in the first embodiment when the input bank address signal (Bank address) indicates the memory bank in which it is installed.

The operation of the pSRAM according to the present embodiment will be described with reference to FIG. 5. In addition, as an example, a case in which the 0th (i=0) memory bank (20) is accessed in the first transaction and the 1st (i=1) memory bank (20) is accessed in the second transaction will be described.

Here, when the 0th (i=0) memory bank (20) is accessed in the first transaction, the operations of the control unit (12), the arbiter (13) and the command generation unit (14) of the 0th memory bank (20) at each of times t11, t12, t13, t14 and t15 are the same as the operations of the control unit (12), the arbiter (13) and the command generation unit (14) at each of times t1, t2, t3, t4 and t5 shown in Fig. 2. That is, each of the access signal (RD/WR_0), refresh signal (REF_0), signal (Cnt_req_0), signal (Cnt_exe_0), and signal (Cmp_ref_0) of the 0th memory bank (20) shown in Fig. 5 is similar to each of the access signal (RD/WR), refresh signal (REF), signal (Cnt_req), signal (Cnt_exe), and signal (Cmp_ref) shown in Fig. 2.

By this, when a memory refresh request is generated during the first transaction, the refresh operation in the 0th memory bank (20) is executed the number of refresh request signals (Ref_request) generated during the first transaction (2 times in the example of the drawing) between the end of the first transaction and the start of the second transaction.

Next, the refresh operation in the first (i=1) memory bank (20) of the first transaction will be described. First, when the chip select signal (CS#) transitions from negate (high level) to assert (low level) and the first transaction is initiated, the command generation unit (14) of the first memory bank (20) generates a low-level access signal (RD/WR) and outputs it to the memory cell array because the first memory bank (20) is not an access target.

At time t11, when a high-level refresh request signal (Ref_request) is generated by the oscillator (11), the counter (12a) of the first memory bank (20) increases the count value from 0 to 1 and outputs a signal (Cnt_req_1) indicating that the count value is 1 to the comparator (12c). In addition, the comparator (12c) of the first memory bank (20) compares the value of the signal (Cnt_req_1) with the value of the signal (Cnt_exe_1) (here, the case of 0 is assumed), and since the value of the signal (Cnt_req_1) is greater than the value of the signal (Cnt_exe_1), the comparator (12c) outputs a high-level output signal to the AND circuit (12e) of the first memory bank (20). In addition, the AND circuit (12e) of the first memory bank (20) performs an AND operation on the output signal from the comparator (12c) and the signal output from the inverter (12d) (which becomes a high level because the refresh signal (REF_1) is at a low level) and outputs a high-level signal (Cmp_ref_1) to the arbiter (13) of the first memory bank (20).

At time t11, since the first memory bank (20) is not an access target, the arbiter (13) outputs a high-level signal (Cmp_ref_1) to the command generation unit (14). In addition, the command generation unit (14) of the first memory bank (20) generates a high-level refresh signal (REF_1) according to the high-level signal (Cmp_ref_1) input from the arbiter (13), and outputs it to the memory cell array and the counter (12b) and inverter (12d) of the first memory bank (20). As a result, the first refresh operation is performed in the first memory bank (20) during the first transaction.

When a high-level refresh signal (REF_1) is input, the counter (12b) of the first memory bank (20) increases the count value from 0 to 1 and outputs a signal (Cnt_exe_1) indicating that the count value is 1 to the comparator (12c). In this case, since the value of the signal (Cnt_req_1) becomes equal to the value of the signal (Cnt_exe_1), the comparator (12c) of the first memory bank (20) outputs a low-level output signal to the AND circuit (12e). As a result, the signal (Cmp_ref_1) output from the AND circuit (12e) of the first memory bank (20) becomes low-level.

Next, at time t12, when a high-level refresh request signal (Ref_request) is generated by the oscillator (11), the control unit (12), the arbiter (13), and the command generation unit (14) of the first memory bank (20) operate in the same manner as at time t11. As a result, the second refresh operation is performed in the first memory bank (20) during the first transaction.

In addition, all memory banks (20) other than the 0th memory bank (20) among the plurality of memory banks (20) can perform a refresh operation like the 1st memory bank (20).

In this way, when a memory refresh request is generated during the first transaction, a refresh operation in a memory bank (20) other than the 0th among multiple memory banks (20) is executed during the first transaction according to the generated refresh request signal (Ref_request).

As described above, according to the pSRAM of the present embodiment, for the selected memory bank (20) (the 0th memory bank (20)) that is the access target in the first transaction, it is possible to execute a refresh operation equal to the number of refresh requests generated during the first transaction between the end of the first transaction and the start of the second transaction. On the other hand, for the memory bank (20) (the 1st memory bank (20)) that is not selected in the first transaction, it is possible to immediately execute a refresh operation when a refresh request is generated during the first transaction. Thereby, the refresh operation for each of the plurality of memory banks (20) can be appropriately executed depending on whether or not it is the selected memory bank (20) in the transaction. In addition, in this case, it is possible to shorten the period (tCSH) from the end of the first transaction (for the 0th memory bank (20)) to the start of the second transaction (for the 1st memory bank (20)), thereby improving the processing performance of pSRAM.

Each embodiment described above has been described to facilitate understanding of the present invention, and is not described to limit the present invention. Accordingly, each element disclosed in each embodiment above is intended to include all design changes and equivalents that fall within the technical scope of the present invention.

For example, in each of the above-described embodiments, as shown in FIGS. 2 and 4, the case where the control unit (12) includes a counter (12a), a counter (12b), a comparator (12c), an inverter (12d), and an AND circuit (12e) has been described as an example, but the configuration of the control unit (12) may be appropriately changed, and various other configurations may be adopted.

In addition, in the second embodiment described above, a case in which a control unit (12) is installed in each of a plurality of memory banks (20) has been described as an example, but the present invention is not limited to this case. For example, one control unit (12) installed in a pSRAM (10) may control the refresh operation in each memory bank (20).

In addition, in the second embodiment described above, the case where the control unit (12), the arbiter (13), and the command generation unit (14) are installed in each of the plurality of memory banks (20) has been described as an example, but the present invention is not limited to this case. For example, the control unit (12), the arbiter (13), and the command generation unit (14) may be installed one by one, and the refresh operation in each memory bank (20) may be controlled by utilizing the control unit (12), the arbiter (13), and the command generation unit (14).

10… Pseudo-static random access memory (pSRAM)
11… Generator
12…Control Unit
12a… counter
12b… counter
12c… comparator
13… Arbiter
14… Command generation section
20… Memory Bank

Claims (10)

As a pseudo-static random access memory,
A control unit that controls the memory refresh operation to be executed as many times as the number of refresh requests generated during the first transaction between the end of the first transaction and the start of the second transaction after the first transaction, when a memory refresh request is generated during the first transaction.
A pseudo-static random access memory, including: In the first paragraph,
The above control unit,
A first counter for counting the number of refresh requests generated during the first transaction;
A second counter that counts the number of refresh operations executed between the end of the first transaction and the start of the second transaction;
A pseudo-static random access memory that controls execution of a refresh operation until the number of refresh operations counted by the second counter reaches the number of refresh requests counted by the first counter. In the second paragraph,
The above control unit,
A pseudo-static random access memory, comprising a comparator for comparing the number of refresh requests counted by the first counter with the number of refresh operations counted by the second counter. In the second paragraph,
A command generation unit for generating a refresh command for executing a refresh operation based on control by the above control unit,
The above command generation unit is a pseudo-static random access memory that outputs the refresh command to the second counter every time the refresh command is generated. In paragraph 4,
The above command generation unit is a pseudo-static random access memory that generates an access command for accessing data to a memory cell array during the first transaction. In paragraph 4,
An arbiter is included that outputs the refresh control signal to the command generation unit whenever a refresh control signal is input from the control unit between the end of the first transaction and the start of the second transaction,
The above command generation unit is a pseudo-static random access memory that generates the refresh command whenever the refresh control signal is input. In the first paragraph,
Containing multiple memory banks accessed in an interleaved manner,
The above control unit,
In the case where a memory bank selected from among the plurality of memory banks is accessed in the first transaction, and a memory refresh request is generated during the first transaction,
Controlling the refresh operation in the selected memory bank to be executed as many times as the number of refresh requests generated during the first transaction between the end of the first transaction and the start of the second transaction;
A pseudo-static random access memory that controls a refresh operation in a memory bank other than the selected memory bank among the plurality of memory banks to be executed during the first transaction according to a generated refresh request. In Article 7,
A pseudo-static random access memory, wherein each of said plurality of memory banks includes said control unit. In any one of claims 1 to 8,
The above pseudo-static random access memory is a pseudo-static random access memory of the clock-synchronous type in which signals are input or output in synchronization with a clock signal. In any one of claims 1 to 8,
The above pseudo-static random access memory is a pseudo-static random access memory of an address data multiplex interface type.