KR102728019B1 - Test Board And Test Apparatus Using The Same - Google Patents

Abstract

The purpose of the present invention is to provide a test board and a test device using the same, which can selectively use vector pattern data stored in a vector pattern memory and auxiliary pattern data stored in an auxiliary pattern memory to generate a test pattern, and to this end, a test board according to the present invention includes: a receiving unit which receives vector pattern data and auxiliary pattern data; a vector pattern memory which stores the vector pattern data and selection signals; an auxiliary pattern memory which stores the auxiliary pattern data; a selection unit which selects the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and an output unit which generates test patterns using the pattern data received from the selection unit and outputs the test patterns to a test target element.

Description

Test Board And Test Apparatus Using The Same

The present invention relates to a test board and a test device using the same.

A test device is used to test the performance of a memory device or semiconductor device. A memory device or semiconductor device tested by a test device is called a device under test.

A test board equipped with a test device can generate various test patterns and transmit them to a device under test, analyze patterns and various signals received from the device under test to analyze the performance of the device under test, and provide the analysis results to the user.

The test board can generate test patterns using pattern data stored in the vector pattern memory (VPM) of the test board.

Therefore, when the test patterns to be transmitted to the device under test are changed, the pattern data stored in the vector pattern memory (VPM) of the test board must be changed.

However, since the total capacity of pattern data stored in the vector pattern memory (VPM) is very large, it takes a lot of time to change all of the pattern data stored in the vector pattern memory.

That is, when the pattern data stored in the vector pattern memory is changed, recompiling and reloading the vector pattern memory are required, which requires a lot of time.

In particular, since recompilation and reloading of the entire vector pattern memory are required even when only some of the pattern data stored in the vector pattern memory are changed, it is difficult to perform rapid testing of test target elements using a conventional test board and a test device using the same.

An object of the present invention to solve the above-described problem is to provide a test board and a test device using the same, which can generate a test pattern by selectively using vector pattern data stored in a vector pattern memory and auxiliary pattern data stored in an auxiliary pattern memory.

According to the present invention for achieving the above-described purpose, a test board includes: a receiving unit for receiving vector pattern data and auxiliary pattern data; a vector pattern memory for storing the vector pattern data and selection signals; an auxiliary pattern memory for storing the auxiliary pattern data; a selection unit for selecting the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and an output unit for generating test patterns using the pattern data received from the selection unit and outputting the test patterns to a test target element.

The above-described receiving unit converts raw pattern data received through an external system into vector pattern data that can be used in the vector pattern memory through a compilation process and then transmits the vector pattern data to the vector pattern memory, or transmits vector pattern data received through a compilation process from the external system to the vector pattern memory.

The above auxiliary pattern data are used to generate test patterns including correction information to be input to the test target device, or are used to generate test patterns for changing the ID of the test target device.

The above vector pattern memory is a data memory that stores the vector pattern data; and stores selection signals for controlling the selection unit.

The above selection unit, when a first selection signal is received from the selection signal memory at the kth timing, transmits the vector pattern data to the first to mth pins connected to the output unit, and when a second selection signal is received from the selection signal memory at the kth timing, transmits the auxiliary pattern data to the first to mth pins.

In the above vector pattern memory, the first selection signal or the second selection signal to be transmitted to the selection unit at the k-th timing is stored in a manner matching the first to m-th vector pattern data to be transmitted to the first to m-th pins at the k-th timing.

The number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins corresponds to the number of the second selection signals.

A test device according to the present invention for achieving the above-described purpose includes: the test board; a high-fix board connected to the test board; a probe interface board connected to the high-fix board; and a pogo board for transmitting test patterns received from the test board through the high-fix board and the probe interface board to a device under test.

According to the present invention, vector pattern data is stored in a vector pattern memory that requires recompilation and reloading when the stored data is changed, auxiliary pattern data to be used instead of some of the vector pattern data can be stored in an auxiliary pattern memory that enables rapid upload, and the vector pattern data and the auxiliary pattern data can be selectively used to generate test patterns.

Therefore, according to the present invention, when a change in some of the test patterns is required, auxiliary pattern data can be quickly stored in the auxiliary memory. Accordingly, rapid testing of the device under test can be performed.

Figure 1 is an exemplary diagram showing a test system to which a test device according to the present invention is applied.
Figure 2 is an exemplary diagram showing the configurations of a test board according to the present invention.
Figure 3 is an example diagram showing output pattern data generated from a test board according to the present invention.

Throughout the specification, the same reference numerals refer to substantially identical components. In the following description, if it is not related to the core configuration of the present invention, detailed descriptions of the configurations and functions known in the technical field of the present invention may be omitted. The meanings of the terms described in this specification should be understood as follows.

The advantages and features of the present invention, and the method for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete, and to fully inform a person having ordinary skill in the art to which the present invention belongs of the scope of the invention.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the matters illustrated. The same reference numerals refer to the same components throughout the specification. In addition, in explaining the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

In the present specification, when the words "includes," "has," and "consists of," are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes the plural unless there is a special explicit description.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on ~', 'upper ~', 'lower ~', 'next to ~', etc., one or more other parts may be located between the two parts, unless 'right' or 'directly' is used.

When describing a temporal relationship, for example, when describing a temporal relationship using phrases such as 'after', 'following', 'next to', or 'before', it can also include cases where there is no continuity, as long as 'right away' or 'directly' is not used.

Although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component referred to below may also be a second component within the technical concept of the present invention.

“X-axis direction”, “Y-axis direction” and “Z-axis direction” should not be interpreted as merely geometric relationships in which the relationship between them is perpendicular to each other, but may mean a wider directionality within the range in which the configuration of the present invention can function functionally.

The term "at least one" should be understood to include all combinations that can be represented from one or more of the associated items. For example, the meaning of "at least one of the first, second, and third items" can mean not only each of the first, second, or third items, but also all combinations of items that can be represented from two or more of the first, second, and third items.

The individual features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings.

Figure 1 is an exemplary diagram showing a test system to which a test device according to the present invention is applied.

A test system to which the present invention is applied includes a test target device (20) and a test device (10) that tests the test target device by transmitting a test pattern to the test target device, as shown in FIG. 1.

The test device (10) can perform the function of testing the quality of a device under test (DUT).

The device under test (DUT) (20) may include a solid state drive (SSD), a hard disk drive (HDD), a double data rate (DDR), and a system on chip (SoC).

In particular, the test device (10) can be used for testing SoCs that use high-speed signals. The SoC may include a PMIC (Power Management Integrated Circuit), an AP (Application Processor), a DDI (Display Driver Integrated Circuit), a Power IC, a CIS (CMOS Image Sensor), etc. When the test target device (20) is an SoC, the test target device (20) may be configured in a wafer form.

As described above, in order for the test device (10) to test the quality of the device under test (DUT) (20), the test device (10) includes, as shown in FIG. 1, a test board (100), a HiFix board (200) connected to the test board, a probe interface board (300) connected to the HiFix board, and a pogo board (400) that transmits test patterns received from the test board through the HiFix board and the probe interface board to the device under test (20).

First, the test board (100) can perform a function of transmitting test patterns to a device under test (20), analyzing test signals received from the device under test (20), or transmitting test patterns to the device under test (20) and then analyzing test signals received from the device under test.

The present invention relates to a test board that generates test patterns. Accordingly, the test board (100) according to the present invention can only perform the function of generating test patterns and transmitting them to a device under test (20), and in this case, test signals generated in the device under test (20) by the test patterns can be analyzed in another test board. However, the test board (100) according to the present invention can also directly analyze test signals received from the device under test by the test patterns after generating test patterns and transmitting them to the device under test.

The specific structure and function of the test board (100) according to the present invention are described in detail below with reference to FIGS. 2 and 3.

Next, the high-fix board (200) performs the function of connecting the test board (100) and the probe interface board (300).

A test board can be mounted on the HiFix board (200), and the HiFix board (200) can perform the function of supporting the probe interface board (300).

Next, the probe interface board (300) transmits test patterns to the device under test (DUT), and converts test signals transmitted from the device under test (20) into signals recognizable by the test board (100) and transmits them to the test board (100).

Next, the pogo board (400) is mounted on the probe interface board, and the test target element (20) is connected to the pogo board (400).

That is, the pogo board (400) can directly contact the device under test (20), transmit test patterns to the device under test (20), and receive test signals from the device under test (20).

Finally, the external system (30) can transmit vector pattern data and auxiliary pattern data to the test board (100).

In particular, an external system may compile input raw pattern data and then transmit the compiled vector pattern data to the test board (100).

That is, the external system can perform a function of converting raw pattern data input through the input section of the external system into vector pattern data that can be used in the test board (100), and this process is called compilation.

However, this compilation process may also be performed on a test board (100).

That is, an external system can transmit raw pattern data input through the input section to the test board (100), and the test board (100) can perform a compilation process on the raw pattern data to convert the raw pattern data into vector pattern data.

To explain further, the format of data used in the manufacturing of the test target device (20) by the manufacturer may be different from the format of data used in the test device (10). Therefore, the raw pattern data provided by the manufacturer of the test target device for testing the test target device (20) may be difficult to use directly in the test device (10).

In this case, an external system (30) or a test board (100) can compile raw pattern data to generate vector pattern data, and the vector pattern data can be used in a test device (10).

Accordingly, when the test patterns used for testing the test target element (20) are changed, a compilation process is performed on new row pattern data, vector pattern data is generated, and the vector pattern data is stored in the test board (100).

In addition, even if some of the test patterns are changed, a compilation process must be performed on all row pattern data including some of the row pattern data that require changes, and all vector pattern data for which the compilation process has been performed must be stored again on the test board (100).

However, while the compilation process for the raw pattern data is being performed, the operation of the test device (10) must be stopped or some of the functions of the test device (10) must be stopped. This causes a delay in the test process and therefore, can cause enormous damage to the company operating the test device (10).

To prevent this, the present invention stores vector pattern data in the vector pattern memory of the test board (100), and stores auxiliary pattern data corresponding to test patterns to be changed in the auxiliary pattern memory. Accordingly, the present invention can generate a test pattern to be changed by using the auxiliary pattern data stored in the auxiliary pattern memory instead of the vector pattern data stored in the vector pattern memory at a timing when a test pattern to be changed is required.

Therefore, according to the present invention, when test patterns to be changed are generated, there is no need to perform a recompile process for all vector pattern data stored in the vector pattern memory.

Therefore, rapid testing can be performed on a large number of test target elements (20).

During the process of conducting tests on test target devices (20), the reasons for changing some test patterns may vary depending on the test device and the test target device.

For example, after a primary test is performed on a test target device (20), in order to resolve a defect or error of the test target device (20), specific information, i.e., correction information, needs to be input to the test target device (20). The correction information can also be referred to as test patterns. In this case, if the entire vector pattern data needs to be changed for the correction information, the problem described above may occur. However, according to the present invention, auxiliary pattern data corresponding to the correction information can be managed separately from the vector pattern data, and therefore, when test patterns corresponding to the auxiliary pattern data are needed, the test patterns can be generated using the auxiliary pattern data instead of the vector pattern data.

In addition, a unique ID for each of the test target devices (20) needs to be input into the test target device, and therefore, whenever the test target device (20) is changed, the test patterns corresponding to the ID of the corresponding test target device (20) need to be changed. In other words, the IDs corresponding to the test target devices can also be said to be test patterns. In this case, if the entire vector pattern data needs to be changed whenever the test target device is changed for the ID required for each test target device, the problem described above may occur. However, according to the present invention, the auxiliary pattern data corresponding to the ID can be managed separately from the vector pattern data, and therefore, when the test target device is changed, the test patterns corresponding to the ID can be generated using the auxiliary pattern data instead of the vector pattern data.

That is, as described above, the test patterns applied to the present invention may include not only signals having a specific pattern, but also various pieces of information, for example, information for resolving defects or errors in the test target device (20), and IDs corresponding to the test target device (20).

FIG. 2 is an exemplary diagram showing the configurations of a test board according to the present invention. In FIG. 2, for convenience of explanation, the test board (100) is illustrated as directly transmitting a test pattern to a test target device (20). However, as described above, a high-fix board (200), an interface board (300), and a pogo board (400) may be further provided between the test board (100) and the test target device. In the following description, the same or similar contents as those described with reference to FIG. 1 are omitted or briefly described.

As described above, the test device (10) according to the present invention includes a test board (100), a high-fix board (200), an interface board (300), and a pogo board (400) according to the present invention, as shown in FIG. 1.

Among these, the test board (100) according to the present invention includes, as illustrated in FIG. 2, a receiving unit (110) that receives vector pattern data and auxiliary pattern data, a vector pattern memory (120) that stores vector pattern data and selection signals, an auxiliary pattern memory (130) that stores auxiliary pattern data, a selection unit (140) that selects vector pattern data or auxiliary pattern data according to a selection signal received from the vector pattern memory (120), and an output unit (150) that generates test patterns using the pattern data received from the selection unit (140) and outputs the test patterns to the test target element (20).

First, the receiving unit (110) can change raw pattern data received through an external system (30) into vector pattern data that can be used in a vector pattern memory (120) through a compile process as described above with reference to FIG. 1, and then transmit the vector pattern data to the vector pattern memory (120).

Additionally, the receiving unit (110) may transmit vector pattern data received through a compilation process from an external system (30) to the vector pattern memory (120).

Additionally, the receiver (110) can transmit auxiliary pattern data transmitted from an external system (30) to the auxiliary pattern memory (130).

Next, auxiliary pattern data is stored and managed in the auxiliary pattern memory (130).

The auxiliary pattern data may be used to generate test patterns including correction information to be input to a test target device (200), as described with reference to FIG. 1, or may be used to generate test patterns for changing the ID of a test target device.

Next, the vector pattern memory (120) includes a data memory (121) that stores vector pattern data and a selection signal memory (122) that stores selection signals to control the selection unit.

For example, in Fig. 2, PCO and PC1, etc. represent output timing, and data stored matching with the PCO represent vector pattern data that are simultaneously output at the timing of the PCO.

Therefore, for example, at the 0th timing (PC0), vector pattern data of [111111 ? 11] are output to the selection unit (140), and at the 5th timing (PC5), vector pattern data of [10XX01 ? 00] are output to the selection unit (140).

In addition, selection signals are stored in the selection signal memory (122) in Fig. 2. The selection signal is illustrated as 'Mux Sel'. For example, the selection signal can be 0 or 1. In the following description, selection signal 0 is referred to as the first selection signal, and selection signal 1 is referred to as the second selection signal.

That is, the first selection signal or the second selection signal can be matched and stored for each timing in the selection signal memory (122).

Next, when the selection unit (140) receives the first selection signal from the selection signal memory (122) at the kth timing, it transmits vector pattern data stored in the data memory to the first to mth pins connected to the output unit (150).

In addition, when the second selection signal is received from the selection signal memory at the kth timing, the selection unit (140) transmits auxiliary pattern data stored in the auxiliary pattern memory (130) to the first to mth pins (k and m are natural numbers).

Accordingly, the output unit (150) may generate and output pattern data using vector pattern data at the kth timing, or may generate and output pattern data using auxiliary pattern data at the kth timing.

The number of the first to mth pins, i.e., m, may be equal to the number of data (111111 ? 11) stored in accordance with the PCO of the data memory (121) illustrated in FIG. 2.

That is, at the 0th timing (PC0), m vector pattern data (111111 ? 11) can be transmitted from the selection unit (140) to the output unit (150) through the first to mth pins. In this case, the data memory (121) and the selection unit (140) may also be provided with the first to mth pins.

To explain in more detail, in the vector pattern memory (120), the first selection signal or the second selection signal to be transmitted to the selection unit (140) at the kth timing is stored in a manner matched with the first to mth vector pattern data to be transmitted to the first to mth pins at the kth timing.

In this case, the number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins may correspond to the number of second selection signals.

For example, if auxiliary pattern data are output at n timings while vector pattern data stored in the data memory (121) are sequentially output during the 0th to xth timings, the number of second selection signals stored in the selection signal memory (122) can be n (x is a natural number, n is a natural number smaller than x). In this case, the number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins can also be n.

That is, auxiliary pattern data output n times can be stored in the auxiliary pattern memory (130).

Hereinafter, the operation method of the test device according to the present invention is described with reference to FIGS. 1 to 3.

Figure 3 is an example diagram showing output pattern data generated from a test board according to the present invention.

First, when the raw pattern data is converted into vector pattern data through the compilation process, the vector pattern data is stored in the vector pattern memory (120). In this case, the second selection signal is matched and stored at a timing when the auxiliary pattern data is required, and the first selection signal is matched and stored at a timing when the auxiliary pattern data is not required. The storage of the first selection signal and the second selection signal can be simply performed without the compilation process.

That is, since the first selection signal and the second selection signal are simple control signals, they can be quickly and simply modified by the user during the test process of the test target elements (20).

Next, auxiliary pattern data to be output at the timing corresponding to the second selection signal are sequentially stored in the auxiliary pattern memory (130) through the receiving unit (110).

As described above, the storage process for auxiliary pattern data can also be simply performed without a compilation process.

In addition, even if a compilation process is required for the auxiliary pattern data, since the auxiliary pattern data are independent data from the vector pattern data used in the test currently in progress, the compilation process can be performed independently for the auxiliary pattern data. Accordingly, after the independent compilation process is performed for the auxiliary pattern data, the auxiliary pattern data can be stored in the auxiliary pattern memory (130). That is, even if the operation of storing the auxiliary pattern data in the auxiliary pattern memory (130) is in progress, the test for the test board (20) can be continuously performed.

In addition, even if the test for the test board (20) is stopped while the auxiliary pattern data are stored in the auxiliary pattern memory (130), the compilation process for the auxiliary pattern data having a number less than the number of vector pattern data can proceed more quickly than the compilation process for the entire vector pattern data.

Therefore, according to the present invention, the period during which the test is stopped may be eliminated or may be reduced compared to the prior art.

Next, while a test is in progress for the test target board (20), when the selection unit (140) receives a first selection signal from the selection signal memory (122), it transmits vector pattern data transmitted from the data memory (121) to the output unit (150) through the first to mth pins.

The output unit (150) generates test patterns using vector pattern data received through the first to mth pins, and transmits the generated test patterns to the test target element (20) through the high-fix board (200), the interface board (300), and the pogo board (400).

Accordingly, testing can be performed on the test target element (20).

Finally, while a test is in progress for the test target board (20), when the selection unit (140) receives a second selection signal from the selection signal memory (122), it transmits vector pattern data transmitted from the auxiliary pattern memory (130) to the output unit (150) through the first to mth pins.

The output unit (150) generates test patterns using auxiliary pattern data received through the first to mth pins, and transmits the generated test patterns to the test target element (20) through the high-fix board (200), the interface board (300), and the pogo board (400).

Accordingly, testing can be performed on the test target element (20).

For example, as illustrated in FIG. 3, when a second selection signal (1) is received at a second timing (PC2), the selection unit (140) can output auxiliary pattern data (101111 ? 11) that matches the second timing (PC2) among the auxiliary pattern data stored in the auxiliary pattern memory (130) to the output unit (150).

For this purpose, auxiliary pattern data (101111 ? 11) are stored in the auxiliary pattern memory (130) at an address (Ox00) corresponding to the second timing (PC2).

In addition, as illustrated in FIG. 3, when the second selection signal (1) is received at the third timing (PC3), the selection unit (140) can output auxiliary pattern data (111000 ? 11) that matches the third timing (PC3) among the auxiliary pattern data stored in the auxiliary pattern memory (130) to the output unit (150).

For this purpose, auxiliary pattern data (111000 ? 11) are stored in the auxiliary pattern memory (130) at an address (Ox01) corresponding to the third timing (PC3).

Therefore, according to the present invention as described above, when a change to a test pattern is required, the test process can be continuously performed using the changed test pattern without a recompile process for the entire vector pattern data. Accordingly, the test process can be performed quickly, and more test target devices can be tested.

It should be understood that the embodiments described above are exemplary in all respects and are not restrictive. The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

10: Test device 20: Test target device
100: Test Board 200: High Fix Board
300: Probe interface board 400: Pogo board

Claims (8)

A receiving unit for receiving vector pattern data and auxiliary pattern data;
A vector pattern memory storing the above vector pattern data and selection signals;
Auxiliary pattern memory for storing the above auxiliary pattern data;
A selection unit for selecting the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and
Generates test patterns using pattern data received from the above selection unit, and includes an output unit that outputs the test patterns to the test target element.
A test board in which the above auxiliary pattern data is used to generate test patterns including correction information to be input to the test target device, or to generate test patterns for changing the ID of the test target device. In paragraph 1,
The above-mentioned receiving unit is a test board that converts raw pattern data received through an external system into vector pattern data that can be used in the vector pattern memory through a compilation process and then transmits the vector pattern data to the vector pattern memory, or transmits vector pattern data received through a compilation process from the external system to the vector pattern memory. delete A receiving unit for receiving vector pattern data and auxiliary pattern data;
A vector pattern memory storing the above vector pattern data and selection signals;
Auxiliary pattern memory for storing the above auxiliary pattern data;
A selection unit for selecting the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and
Generates test patterns using pattern data received from the above selection unit, and includes an output unit that outputs the test patterns to the test target element,
The above vector pattern memory is,
Data memory for storing the above vector pattern data; and
A test board including a selection signal memory that stores selection signals to control the above selection unit. In paragraph 4,
The above selection section,
At the kth timing, when the first selection signal is received from the selection signal memory, the vector pattern data is transmitted to the first to mth pins connected to the output unit,
A test board that transmits the auxiliary pattern data to the first to mth pins when a second selection signal is received from the selection signal memory at the kth timing. In paragraph 5,
In the above vector pattern memory,
A test board in which the first selection signal or the second selection signal to be transmitted to the selection unit at the k-th timing is matched and stored with the first to m-th vector pattern data to be transmitted to the first to m-th pins at the k-th timing. In paragraph 5,
A test board in which the number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins corresponds to the number of the second selection signals. A test board as described in any one of claims 1, 2, and 4 to 7;
A high-fix board connected to the above test board;
A probe interface board connected to the above-mentioned high-fix board; and
A test device including a pogo board for transmitting test patterns received from the test board through the high-fix board and the probe interface board to the device under test.

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