KR102716444B1 - Non-volatile memory device performing a mac operation - Google Patents

Abstract

A nonvolatile memory device according to the present technology includes a memory cell array including a plurality of nonvolatile memory elements storing a plurality of weights and a plurality of bit lines connected to the plurality of nonvolatile memory elements according to a plurality of input signals; and an operation output circuit outputting an operation signal from voltages induced in the plurality of bit lines according to a plurality of input signals.

Description

{NON-VOLATILE MEMORY DEVICE PERFORMING A MAC OPERATION}

The present invention relates to a nonvolatile memory device capable of performing a multiplication and accumulation (MAC) operation.

Neural networks are widely used in artificial intelligence fields such as image recognition and self-driving cars.

A neural network contains an input layer, an output layer, and one or more internal layers between them.

Each layer contains one or more neurons, and neurons in adjacent layers are connected to each other through synapses, and each synapse is assigned a weight.

The weights assigned to synapses are determined through training operations.

The values of neurons included in the input layer are determined from the input values, and the values of neurons included in the internal layers and output layers are obtained from the results of operations using the values of neurons included in the previous layer and the weights assigned to the synapses.

In neural network operations, multiplication and accumulation (MAC) operations are frequently performed, and the importance of operation circuits that can perform them efficiently is increasing.

CN 108446097 US 9430735 KR 10-2010-0034614 A

The present technology provides a non-volatile memory device capable of performing multiplication and accumulation (MAC) operations.

A nonvolatile memory device according to one embodiment of the present invention includes a memory cell array including a plurality of nonvolatile memory elements storing a plurality of weights and a plurality of bit lines connected to the plurality of nonvolatile memory elements according to a plurality of input signals; and an operation output circuit outputting an operation signal from voltages induced in the plurality of bit lines according to a plurality of input signals.

A nonvolatile memory device according to the present technology can easily perform an inner product operation between a weight vector and an input vector by storing information corresponding to weights in memory cells.

FIG. 1 is a block diagram showing a flash memory device according to one embodiment of the present invention.
Figure 2 is a block diagram showing an output circuit according to one embodiment of the present invention.
FIG. 3 is a circuit diagram showing a flash cell array and an output circuit according to one embodiment of the present invention.
Figure 4 is an explanatory diagram showing the operation of a flash memory cell.
Figure 5 is a timing diagram showing the operation of an input circuit according to one embodiment of the present invention.
FIG. 6 is a timing diagram showing an operational operation of a flash memory device according to one embodiment of the present invention.
Figures 7 and 8 are explanatory diagrams explaining the operation when the weight is 2 bits.

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings.

In the following disclosure, a nonvolatile memory device according to an embodiment of the present invention is disclosed using a flash memory device as an example, but the type of the memory device is not necessarily limited to a flash memory device.

FIG. 1 is a block diagram showing a flash memory device (1) according to one embodiment of the present invention.

The flash memory device (1) according to the present embodiment includes a command decoder (100), an output circuit (200), a flash cell array (300), an input circuit (400), and a word line control circuit (500).

The flash cell array (300) may be referred to as a memory cell array.

The command decoder (100) basically controls read operations, program operations, and erase operations, similar to a command decoder included in a conventional flash memory device.

In this embodiment, the command decoder (100) additionally performs control operations necessary for the operational operation.

The flash memory device according to the present embodiment has a memory operation mode and an operation operation mode.

In memory operation mode, it performs the operations of a general flash memory device. In operation operation mode, it performs MAC operation.

The command decoder (100) can distinguish between the memory operation mode (MODE = 0) and the operation operation mode (MODE = 1) by outputting a mode signal (MODE).

The output circuit (200) is connected to a bit line (BL) of a flash cell array (300) and outputs a data signal (VOUT) in a memory operation mode and an operation signal (VMAC) in an operation operation mode.

Figure 2 is a block diagram showing an output circuit (200) according to one embodiment of the present invention.

The output circuit (200) includes a first switch (201), a second switch (202), an operation output circuit (210), and a data output circuit (220).

In this embodiment, the first switch (201) is turned on when the mode signal (MODE) is at a high level, and the second switch (202) is turned on when the mode signal (MODE) is at a low level.

The operation output circuit (210) outputs an operation signal (VMAC) from a signal output from a bit line (BL).

The data output circuit (220) outputs a data signal (VOUT) from a signal output from a bit line (BL).

The configuration and operation of the data output circuit (220) are substantially the same as those of a conventional flash memory device, so a detailed description is omitted.

The configuration and operation of the operation output circuit (210) are specifically disclosed with reference to FIG. 3 together with the configuration of the flash cell array (300).

The input circuit (400) provides input signals (X1, X2, ..., Xn) to the flash cell array (300) according to the mode signal (MODE).

In memory operation mode, input signals (X1, X2, ..., Xn) are provided as is to the flash cell array (300) to control the bit line selection switch.

In memory operation mode, the input signals (X1, X2, ..., Xn) are each 1-bit signals and can be used as bit line selection signals.

In the operation mode, input signals (X1, X2, ..., Xn) are converted into pulse input signals (PX1, PX2, ..., PXn) and provided.

In the computational operation mode, the input signals (X1, X2, ..., Xn) can each be provided as multi-bit signals.

In this embodiment, the pulse input signals (PX1, PX2, ..., PXn) are pulse signals having a width corresponding to the values of the corresponding input signals (X1, X2, ..., Xn).

FIG. 5 is a timing diagram showing the operation of an input circuit (400) according to one embodiment of the present invention in an operation operation mode.

In Figure 5, X1 = "1111", X2 = "1000", X3 = "0100", and X4 = "0010".

When the period of the clock signal (CLK) is T, PX1 is a pulse with a width of 15T, PX2 is a pulse with a width of 8T, PX3 is a pulse with a width of 4T, and PX4 is a pulse with a width of 2T.

The word line control circuit (500) provides a plurality of word line voltages (VW1, VW2, ..., VWn) to the flash cell array (300).

The word line control circuit (500) can additionally provide a source line select signal (CSL).

The configuration of the word line control circuit (500) is substantially the same as the word line control circuit (500) used in a conventional flash memory device.

For example, during a read operation, each of the multiple word line voltages has a level of read voltage (VRead) or pass voltage (VPass).

In the operation mode, the word line control circuit (500) can control read operations, program operations, and erase operations, and at this time, the operation of the word line control circuit (500) is substantially the same as in the memory operation mode.

Accordingly, the specific configuration of the word line control circuit (500) is not disclosed.

FIG. 3 is a circuit diagram showing a flash cell array (300) and an output circuit (200) according to one embodiment of the present invention in an operation mode.

In the operation mode, the first switch (201) of Fig. 2 is turned on and the second switch (202) is turned off.

Accordingly, the illustrations of the first switch (201), the second switch (202), and the data output circuit (220) in Fig. 3 are omitted.

The flash cell array (300) includes a plurality of NAND strings (310-1, 310-2, ..., 310-n).

A NAND string (310-1) is connected between a corresponding bit line (BL) and a source line (SL) and includes a plurality of flash cells (F1, F2, ..., Fm) connected in series.

Hereinafter, a NAND string may be referred to as a cell string, and a flash cell may be referred to as a memory cell.

A NAND string (310-1) includes a bit line selection switch (N1) connecting a flash cell (F1) and a bit line (BL) and a source line selection switch (N2) connecting a flash cell (Fm) and a source line (SL).

In this embodiment, the bit line selection switch (N1) and the source line selection switch (N2) are NMOS transistors.

A number of flash cells (F1, F2, ..., Fm) are floating gate flash cells or charge trap flash cells.

Each flash cell stores a weight, and the operation of storing the weight can be performed in a program operation of the flash memory device (1).

In this embodiment, a flash cell stores a 1-bit weight. A flash cell can also store a multi-bit weight, which will be specifically disclosed below with an example of storing a 2-bit weight.

Figure 4 is an explanatory diagram showing the operation of a flash cell.

Flash cells have either a low or high threshold voltage depending on whether charge is injected into the floating gate or charge trap region.

In this embodiment, a low threshold voltage corresponds to a case where the weight is 1, and a high threshold voltage corresponds to a case where the weight is 0.

At this time, when the read voltage (VRead) is set to a voltage between the low threshold voltage and the high threshold voltage and applied to the gate of the flash cell, the drain-source voltage (Vds) of the flash cell changes depending on the threshold voltage.

For example, if the threshold voltage is programmed low and a read voltage is applied to the flash cell, the flash cell enters a low-resistance state, lowering the drain-source voltage.

Conversely, when the threshold voltage is programmed high and a read voltage is applied to the flash cell, the flash cell enters a high-resistance state and the drain-source voltage increases.

The pass voltage (VPass) is a voltage higher than the high threshold voltage, and the flash cell to which the pass voltage is applied is always in a low resistance state.

In this embodiment, a read voltage (VRead) is applied to one of a plurality of flash cells (F1, F2, ..., Fm) and a pass voltage (VPass) is applied to the rest.

In this embodiment, since a single bit of weight is stored in a flash cell, the same read voltage (VRead) is applied to multiple NAND strings (310-1, 310-2, ..., 310-n) in FIG. 3.

When flash cells store multi-level weights, multiple different levels of read voltages can be provided for each NAND string. This is disclosed in embodiments with reference to FIGS. 7 and 8.

In this embodiment, the bit line selection switch (N1) is turned on and off by a pulse input signal (PX1), and the source line selection switch (N2) is turned on and off by a source line selection signal (CSL).

The source line select signal (CSL) can be turned on when the NAND string (310-1) is selected.

In this embodiment, the source line selection signal (CSL) may be provided by the word line control circuit (500), but the configuration for providing the source line selection signal (CSL) may be changed in various ways.

The bit line selection switch (N1) is turned on in a section where the pulse input signal (N1) is at a high level to connect the bit line (BL) to a number of flash cells (F1, F2, .., Fm).

At this time, the voltage (VIwp1) of the bit line (BL) is determined according to the weight programmed in the flash cell (F1) to which the read voltage (VRead) is applied.

The operation output circuit (200) includes a plurality of multiplication output circuits (211-1, 211-2, ..., 211-n) corresponding to a plurality of NAND strings (310-1, 310-2, ..., 310-n).

Each of the multiple output circuits outputs a current corresponding to the product of a corresponding pulse input signal and a weight programmed into the flash cell.

For example, the multiplication output circuit (211-1) outputs a multiplication current (I1) corresponding to the product of a pulse input signal (PX1) and a weight (W1) programmed in a flash cell (F1).

The multiplication output circuit (211-1) is connected to the bit line (BL) through the first switch (201) of Fig. 2. As described above, the first switch (201) is omitted in Fig. 3.

The multiplication output circuit (211-1) includes a buffer (221) that buffers the voltage (VIwp1) of the bit line (BL) and outputs a buffer output voltage (Vbuf1), and a current source (P1) that outputs a multiplication current (I1) according to the buffer output voltage (Vbuf1).

In this embodiment, the current source (P1) is a PMOS transistor, the gate of which is applied with a buffer output voltage (Vbuf1), the source of which is connected to the power supply voltage (VDD), and the drain of which outputs a multiplication current (I1).

The current source (P1) may further include a resistor (R2) connected between the power supply (VDD) and the source of the PMOS transistor (P1).

A resistor (R1) can be connected between the input terminal of the buffer (221) and the power supply (VDD).

At this time, the input voltage of the buffer (221), i.e., the bit line voltage (VIwp1), corresponds to the voltage obtained by distributing the power supply voltage (VDD) by the resistance ratio of the NAND string (310-1) and the resistor (R1).

When the pulse input signal (PX1) is at a low level, the bit line selection switch (N1) is turned off, so the bit line voltage (VIwp1) is pulled up to the power supply voltage (VDD). At this time, the buffer output voltage (Vbuf1) becomes a high level.

When the pulse input signal (PX1) is at a high level, the bit line selection switch (N1) is turned on, so that the bit line voltage (VIwp1) becomes a voltage close to the power supply voltage (VDD) or a voltage close to the source line voltage, i.e., the ground voltage, depending on the program state of the flash cell (F1).

For example, if the flash cell (F1) is programmed in a high resistance state (high threshold voltage state, W1 = 0), the resistance of the NAND string (310-1) becomes a large value, the bit line voltage (VIwp1) becomes a voltage close to the power supply voltage (VDD), and the buffer output voltage (Vbuf1) becomes a high level.

If the flash cell (F1) is programmed in a low resistance state (low threshold voltage, W1 = 1), the resistance of the NAND string (310-1) becomes a small value and the bit line voltage (VIwp1) becomes a voltage close to the ground voltage, so the buffer output voltage (Vbuf1) becomes a low level.

When the buffer output voltage (Vbuf1) becomes high, the PMOS transistor (P1) turns off and the multiplication current (I1) becomes 0.

When the buffer output voltage (Vbuf1) becomes low level, the PMOS transistor (P1) turns on and the multiplication current (I1) becomes a value greater than 0.

The operation output circuit (210) further includes an addition capacitor (212) and a reset switch (213).

The addition capacitor (212) is charged by a plurality of multiplication currents (I1, I2, ..., In) and outputs an operation voltage (VMAC).

The reset switch (213) discharges the addition capacitor (212) according to the reset signal (RESET).

FIG. 6 is a timing diagram showing an operational operation of a flash memory device according to one embodiment of the present invention.

In Fig. 6, it is assumed that both the weight (W1) corresponding to the pulse input signal (PX1) and the weight (W2) corresponding to the pulse input signal (PX2) are 1.

In Fig. 6, the pulse input signal (PX1) has a high level between T0 and T2, and accordingly, the buffer output voltage (Vbuf1) has a low level between T0 and T2.

Accordingly, the multiplication current (I1) is provided between T0 and T2 to charge the addition capacitor (212).

Additionally, the pulse input signal (PX2) has a high level between T0 and T1, and accordingly, the buffer output voltage (Vbuf2) has a low level between T0 and T1.

Accordingly, the multiplication current (I2) is provided between T0 and T1 to charge the addition capacitor (212).

The operational voltage (VMAC) increases rapidly between T0 and T1 when the multiplication currents (I1, I2) are provided, and then gradually increases between T1 and T2.

At T3, the reset signal (RESET) is activated and the addition capacitor (212) is discharged.

The operational voltage (VMAC) at T3 corresponds to the inner product of the input vector having input signals (X1, X2, ..., Xn) as elements and the weight vector having weight signals (W1, W2, ..., Wn) as elements.

The time from T0 to T3 can be referred to as the operation cycle.

Figure 3 assumes that a weight is programmed into the first flash cell (F1) of each NAND string.

In another embodiment, weights can also be programmed into other flash cells (F1) of the NAND string, in which case the flash cell array can store the entire weights contained in the weight matrix.

In this case, the result of the multiplication operation of the weight matrix and the input vector can be derived by performing the aforementioned operation operation for each row of the flash cell array.

The operation output circuit (210) may further include an analog-to-digital converter for converting the operation voltage (VMAC) into a digital signal.

The operation output circuit (210) may further include a circuit for controlling the level of the operation voltage (VMAC).

Figures 7 and 8 are explanatory diagrams explaining the operation when the weight is 2 bits.

Since the weight is 2 bits, the weight has four cases: “00”, “01”, “10”, and “11”.

In the present embodiment, when the weight is 2 bits, the operation operation shown in Fig. 6 is repeated three times to generate the final summed operation voltage.

That is, when the weight is 2 bits, the reset signal is activated after three operation cycles of Fig. 6 have elapsed.

In Fig. 7, (A), (B), and (C) correspond to three operation operations, and in each case, the level of the read voltage is adjusted.

In the first stage operation illustrated in (A), the read voltage is set to the first voltage (VRead1) that can distinguish between “10” and “01”.

In the second stage operation illustrated in (B), the read voltage is set to a second voltage (VRead2) that can distinguish between “11” and “10”.

In the third step operation illustrated in (C), the read voltage is set to a third voltage (VRead3) that can distinguish between “01” and “00”.

Figure 8 illustrates the process of multiplying X2 and W2.

First, as shown in Fig. 5, since X2 is 8, PX2 is displayed in the form of a pulse with a width of 8T, and PX2 remains the same in the first to third steps.

In Fig. 8, the weight W2 is assumed to be 10”.

In the first stage operation, the read voltage is set to the first voltage (VRead1), so the weight is recognized as 1 while the first stage operation is in progress.

In the second stage operation, the read voltage is set to the second voltage (VRead2), so the weight is recognized as 0 while the second stage operation is in progress.

In the third stage operation, the read voltage is set to the third voltage (VRead3), so the weight is recognized as 1 while the third stage operation is in progress.

Since the final operation voltage corresponds to the result of adding the operation voltages generated while performing the 1st to 3rd stage operation operations, the weight W2 is ultimately recognized as 2.

In Fig. 8, only the product of X2 and W2 is illustrated, but similar operations can be performed simultaneously for X1 to Xn and W1 to Wn, so that the final MAC operation result can be output.

For weights greater than 3 bits, the operation is performed similarly to above, except that the number of steps performed increases.

When the number of bits of the weight is K, the operation result is derived after performing a total of ^2K -1 steps. In each case, the read voltage is set differently for each step, and at this time, the read voltage is set to a voltage that can distinguish between two adjacent weights.

Since other operations can be easily derived by a person skilled in the art from the above-mentioned contents, their specific disclosure is omitted.

The scope of the present invention is not limited to the above disclosure. The scope of the present invention should be interpreted based on the scope literally described in the claims and the equivalent scope thereof.

1: Nonvolatile memory device, flash memory device
100: Command Decoder
200: Output circuit
210: Operation output circuit
211-1, 211-2, 211-n: Multiplication Output Circuit
212: Addition capacitor
213: Reset switch
220: Data output circuit
300: Memory cell array, flash cell array
310-1, 310-2, 310-n: Cell string, NAND string
400: Input circuit
500: Wordline control circuit

Claims (14)

A memory cell array including a plurality of nonvolatile memory elements storing a plurality of weights and a plurality of bit lines connected to the plurality of nonvolatile memory elements according to a plurality of input signals;
An operation output circuit that outputs an operation signal from a voltage induced in the plurality of bit lines according to the plurality of input signals; and
An input circuit that converts the plurality of input signals into a plurality of pulse input signals;
Including, but not limited to,
The above memory cell array
a plurality of cell strings, each of which comprises one of the plurality of non-volatile memory elements; and
A plurality of bitline selection switches connecting the plurality of cell strings and the plurality of bitlines according to the plurality of input signals.
Including,
The above bitline selection signal connects the above multiple cell strings and the above multiple bitlines according to the above multiple pulse input signals,
A nonvolatile memory device wherein each of the plurality of pulse input signals is a pulse signal having a pulse width corresponding to the value of the corresponding input signal. delete In claim 1, each of the plurality of cell strings is
A nonvolatile memory device comprising a plurality of memory cells having word line signals applied to the gate and having sources and drains connected in series in sequence. A nonvolatile memory device according to claim 1, wherein the memory cell array further includes a plurality of source line selection switches that connect the plurality of cell strings to source lines according to a plurality of source line selection signals. delete delete A memory cell array including a plurality of nonvolatile memory elements storing a plurality of weights and a plurality of bit lines connected to the plurality of nonvolatile memory elements according to a plurality of input signals; and
An operation output circuit that outputs an operation signal from a voltage induced in the plurality of bit lines according to the plurality of input signals.
Including, but not limited to,
The above operation output circuit includes a plurality of multiplication output circuits,
The above multiple multiplication output circuits each generate a multiplication current corresponding to the product of a corresponding input signal and a corresponding weight signal,
A nonvolatile memory device wherein each of the plurality of multiplication output circuits includes a current source that generates the multiplication current according to the voltage of any one bit line among the plurality of bit lines. In claim 7, each of the plurality of multiplication output circuits
a resistor connected between the power supply voltage and one of the bit lines; and
A buffer for generating a buffer output voltage by buffering the voltage of the common node of the above resistor and one of the above bit lines;
A nonvolatile memory device further comprising: A nonvolatile memory device according to claim 8, wherein the current source is a PMOS transistor whose gate voltage is adjusted according to the buffer output voltage, whose source is connected to a power supply voltage, and from which the multiplication current is output. A nonvolatile memory device according to claim 9, wherein the current source further includes a resistor connected between the power supply voltage and the source. A nonvolatile memory device according to claim 7, wherein the operation output circuit further includes a capacitor that charges the multiplication current output from the plurality of multiplication output circuits. A nonvolatile memory device according to claim 11, wherein the operation output circuit further includes a reset switch that discharges the capacitor in response to a reset signal. In claim 1, the nonvolatile memory device is a NAND flash memory device. A ^nonvolatile memory device according to claim 7, wherein each of the plurality of weights is a K (K is a natural number) bit signal, and each of the plurality of multiplication output circuits generates the multiplication current by performing 2 ^K -1 operation steps, wherein the magnitude of a read voltage applied to any one of the plurality of nonvolatile memory elements is set differently for each of the 2 K -1 operation steps.

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