KR102716123B1 - Package substrate and semiconductor package including the same - Google Patents

Abstract

The package substrate may include an insulating substrate, a first pad array, a second pad array, and a dummy array. The first pad array may include a plurality of first pads arranged at a first pitch on a surface of the insulating substrate. The second pad array may include second pads arranged at a second pitch wider than the first pitch on the surface of the insulating substrate and having a size identical to that of the first pads. The dummy array may extend continuously between the second pads without a discontinuity. Accordingly, a deficient area of the second pad array with respect to the first pad array can be supplemented by the dummy array, so that conductive bumps mounted on the package substrate can have a uniform thickness.

Description

{PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME}

The present invention relates to a package substrate and a semiconductor package including the same. More specifically, the present invention relates to a pad structure of a package substrate and a 2.5D stacked semiconductor package including the package substrate.

In general, a 2.5D stacked semiconductor package may include a package substrate, an interposer, a first semiconductor chip, and a second semiconductor chip. The package substrate and the interposer may be electrically connected via a plurality of conductive bumps. The package substrate may include pads on which the conductive bumps are mounted.

According to related technologies, the pitch between pads can be determined according to the bump pitch of the interposer. That is, when the interposer has different bump pitches, the pitches between the pads can also be set differently. In this case, a thickness difference can occur between conductive bumps arranged on pads arranged with a fine pitch and conductive bumps arranged on pads arranged with a relatively coarse patch. This thickness difference between the conductive bumps can cause a defect in the packaging process.

The present invention provides a package substrate capable of reducing the thickness difference between challenging bumps.

In addition, the present invention provides a semiconductor package including the above-described package substrate.

According to one aspect of the present invention, a package substrate may include an insulating substrate, a first pad array, a second pad array, and a dummy array. The first pad array may include a plurality of first pads arranged at a first pitch on a surface of the insulating substrate. The second pad array may include second pads arranged at a second pitch wider than the first pitch on the surface of the insulating substrate and having a size identical to that of the first pads. The dummy array may extend continuously between the second pads without a disconnected portion.

According to another aspect of the present invention, a semiconductor package may include a package substrate, an interposer, a first conductive bump array, a second conductive bump array, a dummy bump array, at least one first semiconductor chip, and at least one second semiconductor chip. The package substrate may include an insulating substrate, a first pad array, a second pad array, and a dummy array. The first pad array may include a plurality of first pads arranged at a first pitch on a surface of the insulating substrate. The second pad array may include second pads arranged at a second pitch wider than the first pitch on the surface of the insulating substrate and having a size identical to that of the first pads. The dummy array may extend continuously between the second pads without a disconnected portion. The interposer may be disposed on an upper portion of the package substrate. The first conductive bump array may be disposed between the first pad array and the interposer. The second conductive bump array may be disposed between the second pad array and the interposer. The dummy bump array may be disposed between the dummy array and the interposer. The first semiconductor chip may be disposed on an upper surface of the interposer. The second semiconductor chip may be disposed on an upper surface of the interposer.

According to the present invention described above, a dummy array can be arranged continuously without a discontinuity within a second pad array arranged at a second pitch wider than a first pitch of the first pad array. The insufficient area of the second pad array with respect to the first pad array can be supplemented by the dummy array. Accordingly, conductive bumps mounted on the package substrate can have a uniform thickness.

FIG. 1 is a plan view showing a package substrate according to one embodiment of the present invention.
Figure 2 is a cross-sectional view taken along line AA' of Figure 1.
FIG. 3 is a plan view showing a package substrate according to another embodiment of the present invention.
FIG. 4 is a plan view showing a package substrate according to another embodiment of the present invention.
FIG. 5 is a plan view showing a package substrate according to another embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a semiconductor package including the package substrate illustrated in FIG. 1.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a plan view showing a package substrate according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1.

Referring to FIGS. 1 and 2, a package substrate (100) according to the present embodiment may include an insulation substrate (110), a first pad array (120), a second pad array (130), a dummy array (140), and lower pads (190).

The insulating substrate (110) may have an approximately rectangular shape. However, the shape of the insulating substrate (110) is not limited to a rectangle and may have various other shapes. The insulating substrate (110) may include an insulating material. The insulating material of the insulating substrate (110) may not be limited to a specific material. In addition, the insulating substrate (110) may have a structure in which a plurality of insulating films are laminated. Conductive lines may be arranged on the laminated insulating films. As another embodiment, the insulating substrate (110) may be formed of a single insulating film.

The lower pads (190) may be arranged on the lower surface of the insulating substrate (110). The lower pads (190) may be connected to the lower ends of the conductive lines. The lower pads (190) may include a conductive material such as copper (Cu). However, the material of the lower pads (190) may not be limited to a specific conductive material.

A lower insulating pattern (180) may be formed on a lower surface of the insulating substrate (110). The lower insulating pattern (180) may have openings exposing the lower pads (190). The lower insulating pattern (180) may include a solder resist.

The first pad array (120) may include a plurality of first pads (122). The first pads (122) may be arranged on an upper surface of an insulating substrate (110). The first pads (122) may be connected to upper ends of conductive lines of the insulating substrate (110). The first pads (122) may be arranged with equal left-right spacing.

In this embodiment, the first pads (122) may be arranged at a first pitch (P1). In another embodiment, the spacing between the left and right sides of the first pads (122) may not be the same. The first pads (122) may include a conductive material such as copper (Cu). However, the material of the first pads (122) may not be limited to a specific conductive material.

The second pad array (130) may include a plurality of second pads (132). The second pads (132) may be arranged on an upper surface of the insulating substrate (110). The second pads (132) may be connected to upper ends of conductive lines of the insulating substrate (110). The second pads (132) may be arranged at equal intervals on the left and right sides. The size of each of the second pads (132) may be substantially the same as the size of each of the first pads (122). The second pads (132) may include a conductive material such as copper (Cu). However, the material of the second pads (132) may not be limited to a specific conductive material.

In the present embodiment, the second pads (132) may be arranged at a second pitch (P2). The second pitch (P2) may be wider than the first pitch (P1). Accordingly, the first pads (122) may be arranged more densely than the second pads (132). Accordingly, since the first pads (122) and the second pads (132) have substantially the same area, the total area occupied by the first pads (122) within the same area of the upper surface of the insulating substrate (110) may be wider than the total area occupied by the second pads (132). That is, the area of the first pad array (120) may be wider than the area of the second pad array (130).

The upper insulating pattern (170) may be formed on the upper surface of the insulating substrate (110). The upper insulating pattern (170) may have openings exposing the first pads (122) and the second pads (132). The upper insulating pattern (170) may include a solder resist.

The difference in the area of the first pad array (120) and the second pad array (130) may cause a difference in the thickness of the upper insulating pattern (170). For example, when the area of the first pad array (120) is larger than that of the second pad array (130), the thickness of the upper insulating pattern (170) formed on the upper side of the first pad array (120) may be thicker than the thickness of the upper insulating pattern (170) formed on the upper side of the second pad array (130). This difference in the thickness of the upper insulating pattern (170) may cause a difference in the height of conductive bumps to be formed on the first pads (122) and the second pads (132) through a plating process. The difference in the height of the conductive bumps may act as an error factor in the semiconductor package process.

To provide a uniform height to the conductive bumps, a dummy array (140) may be placed inside the second pad array (130). The dummy array (140) may not be connected to the conductive patterns within the insulating substrate (110). The dummy array (140) may be exposed through openings in the upper insulating pattern (170).

The dummy array (140) may have a role of supplementing the insufficient area of the second pad array (130) for the area of the first pad array (120). Therefore, the dummy array (140) may include a material substantially the same as the material of the second pad array (130). When the second pad array (130) includes copper, the dummy array (140) may also include copper. In particular, the dummy array (140) may have a structure that extends continuously without a disconnected portion between the second pads (132).

For example, the combined area of the area of the dummy array (140) and the area of the second pad array (130) may be 70% to 100% of the area of the first pad array (120). In particular, since the dummy array (140) has a structure that extends continuously without a disconnected portion, the insufficient area of the second pad array (130) with respect to the area of the first pad array (120) can be supplemented. Accordingly, the upper insulating pattern (170) formed on the upper portions of the first pad array (120) and the second pad array (130) can have a uniform thickness. As a result, the conductive bumps formed on the first pad array (120) and the second pad array (130) can also have a uniform height.

In the present embodiment, the dummy array (140) may include a plurality of dummy pads (142) and a plurality of dummy lines (144). Each of the dummy pads (142) may be positioned at a central portion between four adjacent second pads (132) among the second pads (132). In addition, each of the dummy pads (142) may have an approximately circular shape. The circular dummy pads (142) may be spaced apart from the second pads (132). The dummy lines (144) may extend from the circular dummy pads (142) through the second pads (132). Accordingly, the circular dummy pads (142) may be connected to each other by the dummy lines (144). The dummy lines (144) may extend along two orthogonal center lines of the circular dummy pads (142) to be orthogonal to each other. The dummy lines (144) may be spaced apart from the second pads (132). Additionally, the dummy lines (144) may have a uniform width. In another embodiment, the width of the dummy lines (144) may not be uniform.

A dummy array (140) having a shape as described above can be formed between the second pads (132). The dummy array (140) can be formed through a process of forming the second pads (132). In another embodiment, when a ground layer is formed between the second pads (132), the dummy array (140) can be formed by partially removing the ground layer.

FIG. 3 is a plan view showing a package substrate according to another embodiment of the present invention.

The package substrate (100a) according to the present embodiment may include components substantially identical to those of the package substrate (100) illustrated in FIG. 1, except for the dummy array. Accordingly, identical components are indicated by the same reference numerals, and further, repeated descriptions of identical components may be omitted.

Referring to FIG. 3, the dummy array (150) may include a plurality of dummy pads (152) and a plurality of dummy lines (154). Each of the dummy pads (152) may be positioned at a central portion between four adjacent second pads (132) among the second pads (132). In addition, each of the dummy pads (152) may have an approximately rectangular shape, specifically, a rhombus shape. The rhombus-shaped dummy pads (152) may be spaced apart from the second pads (132). The dummy lines (154) may extend from the vertices of the rhombus-shaped dummy pads (152) through the second pads (132) and be orthogonal to each other. The dummy lines (154) may be spaced apart from the second pads (132). In addition, the dummy lines (154) may have a uniform width. As another embodiment, the width of the dummy lines (154) may not be uniform.

FIG. 4 is a plan view showing a package substrate according to another embodiment of the present invention.

The package substrate (100b) according to the present embodiment may include components substantially identical to those of the package substrate (100) illustrated in FIG. 1, except for the dummy array. Accordingly, identical components are indicated by the same reference numerals, and further repetitive descriptions of identical components may be omitted.

Referring to FIG. 4, the dummy array (160) may include a plurality of first dummy lines (162) and a plurality of second dummy lines (164). The first dummy lines (162) may extend along a first direction between the second pads (132). The second dummy lines (164) may extend along a second direction orthogonal to the first direction between the second pads (132). Accordingly, the first dummy lines (162) and the second dummy lines (164) may be orthogonal to each other. That is, the first dummy lines (162) and the second dummy lines (164) may intersect each other at the center portions of four adjacent second pads (132). The first dummy lines (162) and the second dummy lines (164) may be spaced apart from the second pads (132). Additionally, the first dummy lines (162) and the second dummy lines (164) may have uniform widths. In another embodiment, the first dummy lines (162) and the second dummy lines (164) may have different widths.

FIG. 5 is a plan view showing a package substrate according to another embodiment of the present invention.

Referring to FIG. 5, a package substrate (100c) according to the present embodiment may include an insulating substrate (110), a first pad array (120c), a second pad array (130c), and lower pads (190).

The insulating substrate (110) may have a structure substantially the same as the structure of the insulating substrate (110) illustrated in FIG. 1. Therefore, a repeated description of the insulating substrate (110) of the present embodiment may be omitted. The lower pads (190) may be arranged on the lower surface of the insulating substrate (110). The lower pads (190) may be connected to the lower ends of the conductive lines.

The first pad array (120c) may include a plurality of first pads (122c). The first pads (122c) may be arranged on an upper surface of an insulating substrate (110). Each of the first pads (122c) may have a first size. The first pads (122c) may be connected to upper ends of conductive lines of the insulating substrate (110). The first pads (122c) may be arranged at a uniform left-right interval. In the present embodiment, the first pads (122c) may be arranged at a first pitch (P1). The first pads (122) may include a conductive material such as copper (Cu).

The second pad array (130c) may include a plurality of second pads (132c). The second pads (132c) may be arranged on an upper surface of the insulating substrate (110). The second pads (132c) may be connected to upper ends of conductive lines of the insulating substrate (110). The second pads (132c) may include a conductive material such as copper (Cu). The second pads (132c) may be arranged at a uniform left-right interval. The second pads (132c) may be arranged at a second pitch (P2). The second pitch (P2) may be wider than the first pitch (P1). Therefore, the first pads (122c) may be arranged more densely than the second pads (132c).

In the present embodiment, each of the second pads (132c) may have a second size. The second size may be wider than the first size. That is, the second pads (132c) may have a larger area than the first pads (122c). Although the second pads (132c) are arranged at a second pitch (P2) interval that is wider than the first pitch (P1) between the first pads (122c), since the size of the second pads (132c) is wider than the size of the first pads (122c), the total area occupied by the second pads (132c) within the same area of the upper surface of the insulating substrate (110) may be close to or substantially the same as the total area occupied by the first pads (122c).

For example, the area of the second pad array (130c) may be 70% to 100% of the area of the first pad array (120c). The upper insulating pattern (170) formed on the upper portions of the first pad array (120c) including the first pad (122c) having the first size and the second pad array (130c) including the second pad (132c) having the second size wider than the first size may have a uniform thickness. As a result, the conductive bumps formed on the first pad array (120c) and the second pad array (130c) may also have a uniform height.

FIG. 6 is a cross-sectional view showing a semiconductor package including the package substrate illustrated in FIG. 1.

Referring to FIG. 6, the semiconductor package (200) according to the present embodiment may include a 2.5D stacked package. Accordingly, the semiconductor package (200) may include a package substrate (100), an interposer (210), conductive bumps (220), dummy bumps (225), at least one first semiconductor chip (230), at least one second semiconductor chip (240), a molding member (250), a heat spreader (260), and external terminals (270).

The package substrate (100) illustrated in FIG. 6 may have a structure substantially identical to that of the package substrate (100) illustrated in FIG. 2. Therefore, a repeated description of the package substrate (100) illustrated in FIG. 6 may be omitted. As another embodiment, the semiconductor package (200) may include the package substrate (100a) illustrated in FIG. 3, the package substrate (100b) illustrated in FIG. 4, or the package substrate (100c) illustrated in FIG. 5.

An interposer (210) may be placed on an upper portion of a package substrate (100). The interposer (210) may include a plurality of upper pads (212), a plurality of lower pads (214), and conductive posts (216). The upper pads (212) may be placed on an upper surface of the interposer (210). The lower pads (214) may be placed on a lower surface of the interposer (210). The conductive posts (216) may be formed along a vertical direction within the interposer (210) to electrically connect the upper pads (212) and the lower pads (214).

Among the lower pads (214), the lower pads (214) arranged on the upper side of the first pad array (120) of the package substrate (100) may be arranged at a pitch corresponding to the first pitch (P1) of the first pad array (120). Among the lower pads (214), the lower pads (214) arranged on the upper side of the second pad array (130) of the package substrate (100) may be arranged at a pitch corresponding to the second pitch (P2) of the second pad array (130).

The conductive bumps (220) may be interposed between the package substrate (100) and the interposer (210) to electrically connect the package substrate (100) and the interposer (210). Specifically, the conductive bumps (220) may electrically connect the first pads (122) and the second pads (132) of the package substrate (100) to the lower pads (214) of the interposer (210). Accordingly, the conductive bumps (220) arranged on the first pads (122) may be arranged at a pitch corresponding to the first pitch (P1) of the first pads (122). In addition, the conductive bumps (220) arranged on the second pads (132) may be arranged at a pitch corresponding to the second pitch (P2) of the second pads (132).

Dummy bumps (225) may be arranged on the dummy array (140). The conductive bumps (220) may be formed through a plating process on the first pads (122) and the second pads (132) exposed through the openings of the upper insulating pattern (170). In addition, the dummy bumps (225) may also be formed through a plating process on the dummy array (140) exposed through the openings of the upper insulating pattern (170). That is, the conductive bumps (220) and the dummy bumps (225) may be formed simultaneously through one plating process.

As described above, since the combined area of the dummy array (140) and the area of the second pad array (130) is 70% to 100% of the area of the first pad array (120), the upper insulating pattern (170) can have a uniform thickness. Accordingly, the conductive bumps (220) formed on the first pads (122) and the second pads (132) can also have a uniform height. Accordingly, the electrical contact reliability between the lower pads (214) of the interposer (210) and the conductive bumps (220) can be improved.

A first semiconductor chip (230) may be placed on an upper surface of an interposer (210). The first semiconductor chip (230) may be electrically connected to upper pads of the interposer (210) via conductive bumps (235). The first semiconductor chip (230) may include a central processing unit (CPU), a graphic processing unit (GPU), and the like.

A second semiconductor chip (240) may be placed on an upper surface of the interposer (210). The second semiconductor chip (240) may be electrically connected to upper pads of the interposer (210) via conductive bumps (245). The second semiconductor chip (240) may include a buffer chip and a plurality of high bandwidth memory (HBM) chips that are sequentially stacked.

The molding member (250) may be formed on the upper surface of the interposer (210) and surround side surfaces of the first semiconductor chip (230) and the second semiconductor chip (240). Accordingly, the upper surfaces of the first semiconductor chip (230) and the second semiconductor chip (240) may be exposed upward. The molding member (250) may include an epoxy molding compound (EMC).

A heat spreader (260) can be attached to the upper surfaces of the first semiconductor chip (230) and the second semiconductor chip (240). The heat spreader (260) can quickly release heat generated from the first semiconductor chip (230) and the second semiconductor chip (240) to the outside of the semiconductor package (200).

External connection terminals (270) may be mounted on the lower pads (190) of the package substrate (100). The external connection terminals (270) may include solder balls.

Meanwhile, in this embodiment, the package substrates are exemplified as being applied to a 2.5D stacked semiconductor package (200), but the package substrates of this embodiment can also be applied to semiconductor packages having various structures other than the 2.5D stacked type.

According to the above-described embodiments, a dummy array can be arranged continuously without a break in a second pad array arranged at a second pitch wider than a first pitch of the first pad array. The insufficient area of the second pad array with respect to the first pad array can be supplemented by the dummy array. Accordingly, conductive bumps mounted on the package substrate can have a uniform thickness.

While the present invention has been described with reference to preferred embodiments thereof as described above, it will be understood by those skilled in the art that various modifications and changes may be made therein without departing from the spirit and scope of the present invention as set forth in the claims below.

110 ; Insulating substrate 120 ; First pad array
122; 1st pad 130; 2nd pad array
132 ; 2nd pad 140, 150, 160 ; dummy array
142, 152; dummy pad 144, 154; dummy line
162; 1st dummy line 164; 2nd dummy line
170 ; Upper insulation pattern 180 ; Lower insulation pattern
190 ; Lower pad 210 ; Interposer
212 ; upper pad 214 ; lower pad
216 ; Challenge Post 220 ; Challenge Bump
230; First semiconductor chip 235; Conductive bump
240; Second semiconductor chip 245; Conductive bump
250 ; Molding member 260 ; Heat spreader
270 ; External connection terminal

Claims (10)

insulating substrate;
A first pad array including a plurality of first pads arranged at a first pitch on a surface of the insulating substrate;
A second pad array including second pads arranged on the surface of the insulating substrate at a second pitch wider than the first pitch and having a size identical to that of the first pad; and
A package substrate comprising a dummy array extending continuously without a gap between the second pads. A package substrate in accordance with claim 1, wherein the sum of the area of the second pad array and the area of the dummy array is 70% to 100% of the area of the first pad array. In the first paragraph, the dummy array
Dummy pads arranged between adjacent second pads among the above second pads; and
A package substrate including dummy lines extending between the second pads and connecting the dummy pads to each other. In the third paragraph, a package substrate wherein each of the dummy pads is positioned in the central portion between the four neighboring second pads. In the third paragraph, a package substrate wherein each of the dummy pads has a circular or rectangular shape. In the third paragraph, the dummy lines are a package substrate that are orthogonal to each other. In the first aspect, the dummy arrays are a package substrate including a plurality of dummy lines extending between the second pads and intersecting each other. In the seventh paragraph, the dummy lines are a package substrate that are orthogonal to each other. A package substrate comprising: an insulating substrate, a first pad array including a plurality of first pads arranged at a first pitch on an upper surface of the insulating substrate, a second pad array including second pads arranged at a second pitch wider than the first pitch on an upper surface of the insulating substrate and having a size identical to that of the first pads, and a dummy array extending continuously between the second pads without a discontinuity;
An interposer disposed on the upper side of the package substrate;
A first conductive bump array disposed between the first pad array and the interposer;
A second conductive bump array disposed between the second pad array and the interposer;
A dummy bump array arranged between the dummy array and the interposer;
At least one first semiconductor chip disposed on the upper surface of the interposer; and
A semiconductor package comprising at least one second semiconductor chip arranged on an upper surface of the interposer. A semiconductor package in accordance with claim 9, further comprising an insulating pattern formed on an upper surface of the insulating substrate to expose the first and second pad arrays and the dummy array.

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