KR102707934B1 - Display device and method of manufacturing the display device - Google Patents

Abstract

A display device includes a substrate having a through hole formed within a display area in which pixels are arranged, and a groove member disposed in an area between the display area and the through hole, the groove member including a bottom portion, a first side wall portion on the display area side having a first step from the bottom portion, and a second side wall portion on the through hole side facing the first side wall portion and having a second step smaller than the first step from the bottom portion.

Description

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE

The present invention relates to a display device and a method for manufacturing the same. More specifically, the present invention relates to a display device for preventing impurities such as moisture and oxygen from being introduced and a method for manufacturing the same.

As the display field that visually expresses various electrical signal information is rapidly developing, various flat panel display devices with excellent characteristics such as thinness, lightness, and low power consumption are being used. Among flat panel display devices, liquid crystal display devices and organic light emitting display devices are widely commercialized due to their excellent resolution and image quality. In particular, organic light emitting display devices are receiving attention as next-generation flat panel display devices due to their fast response speed, low power consumption, and excellent viewing angles because they are self-luminous.

If impurities such as moisture and oxygen enter the interior of the display device from the outside, the lifespan of the electric elements included in the display device may be shortened, and in the case of an organic light-emitting display device, the light-emitting efficiency of the organic light-emitting layer may be reduced. In this case, problems such as deterioration of the light-emitting color of the organic light-emitting layer may occur.

One purpose of the present invention is to provide a display device that prevents the penetration of impurities such as moisture and oxygen.

Another object of the present invention is to provide a method for manufacturing the display device.

However, the purpose of the present invention is not limited to these purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention.

In order to achieve the above-described object of the present invention, a display device according to embodiments includes a substrate having a through hole formed in a display area in which pixels are arranged, and a groove member disposed in an area between the display area and the through hole, the groove member including a bottom portion, a first side wall portion on the display area side having a first step from the bottom portion, and a second side wall portion on the through hole side facing the first side wall portion and having a second step smaller than the first step from the bottom portion.

In one embodiment, each of the first and second sidewall portions may include a sidewall corresponding to an etched surface on which a plurality of insulating layers are etched, and may include an undercut that is concavely formed in a direction perpendicular to the etched surface.

In one embodiment, the display device includes a buffer layer disposed on the substrate, a semiconductor member disposed on the buffer layer, a first insulating layer disposed on the semiconductor member, a first conductive pattern disposed on the first insulating layer, a second insulating layer disposed on the first conductive pattern, a second conductive pattern disposed on the second insulating layer, and a third insulating layer disposed on the second conductive pattern, wherein the height of the sidewall can correspond to a stacking thickness of the first, second, and third insulating layers.

In one embodiment, the first sidewall portion may include a first undercut having a first width, and the second sidewall portion may include a second undercut having a second width smaller than the first width.

In one embodiment, the display device may include a third conductive pattern disposed on the third insulating layer, a first planarization layer disposed between the third insulating layer and the third conductive pattern, a fourth conductive pattern disposed on the third conductive pattern, a second planarization layer disposed between the third conductive pattern and the fourth conductive pattern, a pixel electrode disposed on the fourth conductive pattern, and a third planarization layer disposed between the fourth conductive pattern and the pixel electrode.

In one embodiment, the first width of the first undercut may correspond to a thickness of the second flattening layer of the display area.

In one embodiment, the display device may further include a protective insulating layer disposed between the second planarization layer and the fourth conductive pattern.

In one embodiment, the first width of the first undercut may correspond to a laminated thickness of the second planarization layer in the display area and a third planarization layer disposed on the second planarization layer.

In one embodiment, the display device may further include a protective insulating layer disposed between the third planarizing layer and the pixel electrode.

In one embodiment, the second width of the second undercut may correspond to the thickness of the second flattening layer.

In order to achieve the above-described object of the present invention, a method for manufacturing a display device according to embodiments includes a step of forming a through hole in a display area of a substrate on which pixels are arranged, and a step of forming a groove member including a bottom portion, a first sidewall portion on the display area side having a first step difference from the bottom portion, and a second sidewall portion on the through hole side facing the first sidewall portion and having a second step smaller than the first step difference from the bottom portion, in an area between the display area and the through hole.

In one embodiment, the method may further include the step of forming a first undercut having a first width in the first sidewall portion and forming a second undercut having a second width smaller than the first width in the second sidewall portion.

In one embodiment, the method may further include the steps of forming a buffer layer on the substrate, forming a semiconductor member on the buffer layer, forming a first insulating layer on the semiconductor member, forming a first conductive pattern on the first insulating layer, forming a second insulating layer on the first conductive pattern, forming a second conductive pattern on the second insulating layer, and forming a third insulating layer on the second conductive pattern.

In one embodiment, the method may further include the step of etching the first, second and third insulating layers to form a groove hole including a first sidewall, a second sidewall facing the first sidewall and a bottom portion exposing the buffer layer.

In one embodiment, the method may further include forming a third conductive pattern on the third insulating layer, forming a first planarization layer disposed between the third insulating layer and the third conductive pattern, forming a fourth conductive pattern on the third conductive pattern, forming a second planarization layer between the third conductive pattern and the fourth conductive pattern, forming a pixel electrode on the fourth conductive pattern, and forming a third planarization layer between the fourth conductive pattern and the pixel electrode.

In one embodiment, the method may further include forming a protective insulating layer between the second planarization layer and the fourth conductive pattern.

In one embodiment, the method may further include the steps of forming a first planarizing member within the groove hole, forming a second planarizing member partially overlapping the first planarizing member so as to cover a first end of the first planarizing member and expose a second end of the first planarizing member, forming the protective insulating layer so as to cover the first and second planarizing members, etching the protective insulating layer to form an etching hole exposing at least one of the first and second planarizing members, and removing the first and second planarizing members through the etching hole to form the groove member.

In one embodiment, the method may further include the step of forming a protective insulating layer between the third planarizing layer and the pixel electrode.

In one embodiment, the method may further include: forming a first planarizing member within the groove hole; forming a second planarizing member overlapping the first planarizing member so as to cover first and second ends of the first planarizing member; forming a third planarizing member partially overlapping the second planarizing member so as to cover the first end of the second planarizing member and expose a second end of the second planarizing member; forming a protective insulating layer so as to cover the second and third planarizing members; etching the protective insulating layer to form an etching hole exposing at least one of the second and third planarizing members; and removing the first, second and third planarizing members through the etching hole to form the groove member.

In one embodiment, the method may further include the steps of forming a first planarizing member within the groove hole, forming a second planarizing member partially overlapping the first planarizing member so as to cover a first end of the first planarizing member and expose a second end of the first planarizing member, forming a third planarizing member overlapping the second planarizing member so as to cover the first end of the second planarizing member, forming a protective insulating layer so as to cover the first, second and third planarizing members, etching the protective insulating layer to form an etching hole exposing at least one of the first, second and third planarizing members, and removing the first, second and third planarizing members through the etching hole to form the groove member.

In the display device and the manufacturing method thereof according to embodiments of the present invention, the groove member may be formed such that the first step of the first side wall portion corresponding to the display area side is larger than the second step of the second side wall portion corresponding to the through hole side, thereby enhancing the effect of blocking the path through which impurities such as moisture and acid water penetrate from the outside into the inside of the display device.

However, the effects of the present invention are not limited to the effects described above, and may be expanded in various ways without departing from the spirit and scope of the present invention.

FIG. 1 is a plan view illustrating a display device according to one embodiment of the present invention.
Figure 2 is an enlarged view of part A of Figure 1.
FIG. 3 is a cross-sectional view taken along line I-I' shown in FIG. 2 to explain a display device according to one embodiment of the present invention.
Figures 4 to 10 are cross-sectional views for explaining a method of manufacturing the display device illustrated in Figure 3.
FIG. 11 is a cross-sectional view illustrating a display device according to one embodiment of the present invention.
Figures 12 to 14 are cross-sectional views for explaining a method of manufacturing the display device illustrated in Figure 11.
FIG. 15 is a cross-sectional view illustrating a display device according to one embodiment of the present invention.
FIGS. 16 and 17 are cross-sectional views for explaining a method of manufacturing the display device illustrated in FIG. 15.

Fig. 1 is a plan view for explaining a display device according to one embodiment of the present invention. Fig. 2 is an enlarged view of part A of Fig. 1.

Referring to FIGS. 1 and 2, it includes a display area (DA), a shading area (BMA), and a non-display area (NDA).

The above display area (DA) is an area that displays an image, and a plurality of pixels (P) can be arranged.

Each of the plurality of pixels (P) may include a plurality of transistors and at least one capacitor connected to a gate line (GL), a data line (DL), a first power signal (ELVDD) and a second power signal (ELVSS).

For example, a pixel (P) may include a first transistor (TR1), a second transistor (TR2), a storage capacitor (CST), and an organic light-emitting diode (OLED).

The first transistor (TR1) includes a gate electrode connected to the gate line (GL), a source electrode connected to the data line (DL), and a drain electrode connected to a first node (N1). The second transistor (TR2) includes a gate electrode connected to the first node (N1), a source electrode connected to the first power signal (ELVDD), and a drain electrode connected to the organic light emitting diode (OLED).

The storage capacitor (CST) includes a first capacitor electrode connected to the first node (N1) and a second capacitor electrode connected to a first power signal (ELVDD). The organic light emitting diode (OLED) includes an anode connected to the second transistor (TR2) and a cathode connected to a second power signal (ELVSS).

When the first transistor (TR1) is turned on by the gate signal transmitted from the gate line (GL), the first transistor (TR1) transmits the data signal transmitted from the data line (DL) to the first node (N1). The second transistor (TR2) provides a driving current to the organic light emitting diode (OLED) based on a voltage between the first power signal (ELVDD) stored in the storage capacitor (CST) and the data signal applied to the first node (N1). The organic light emitting diode (OLED) emits light based on the driving current.

The above-mentioned shading area (BMA) is an area surrounding the edge of the display area (DA), and light can be blocked. Various driving circuits for driving the pixels (P) can be arranged in the above-mentioned shading area (BMA).

The above non-display area (NDA) is an area located within the display area (DA), where no pixels are arranged. The non-display area (NDA) may have a through hole cut into the display device to arrange external elements such as a camera and various functional sensors.

Referring to FIG. 2, the non-display area (NDA) may have various shapes, such as a circular shape, a rectangular shape, a polygonal shape, etc.

For example, the non-display area (NDA) may have a through hole (TH) and a groove member (UG) arranged. The groove member (UG) may be arranged to surround a cut surface of the through hole (TH) through which the display device is cut. The groove member (UG) may block a moisture permeation path through which impurities such as moisture and oxygen in the air permeate into the inside of the display device through the cut surface of the through hole (TH).

The groove member (UG) includes a bottom portion (B), a first side wall portion (W1) connected to the bottom portion (B), and a second side wall portion (W2) facing the first side wall portion (W1). The first side wall portion (W1) corresponds to the display area (DA) side and has a first step. The second side wall portion (W2) corresponds to the through hole (TH) side and has a second step smaller than the first step. Since the first step of the first side wall portion (W1) is formed larger than the second step of the second side wall portion (W2), the effect of blocking impurities such as moisture and acid water from penetrating into the display area (DA) can be improved.

FIG. 3 is a cross-sectional view taken along line I-I' shown in FIG. 2 to explain a display device according to one embodiment of the present invention.

Referring to FIGS. 2 and 3, the display device (1000) includes a base substrate (110), and the base substrate (110) may include a display area (DA) and a groove area (GA).

Pixels (P) are arranged in the display area (DA), and a groove member (Undercut Groove, UG) is arranged in the groove area (GA).

The above base substrate (110) may be formed of a transparent resin substrate having flexibility. An example of a transparent resin substrate that can be used as the above base substrate (110) is a polyimide substrate. In this case, the polyimide substrate may be composed of a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate may have a configuration in which a first polyimide layer, a barrier film layer, and a second polyimide layer are laminated on a rigid glass substrate.

Referring to the display area (DA) of the display device (1000), a buffer layer (120) may be arranged on the base substrate (110).

The buffer layer (120) can block impurities such as oxygen and moisture that penetrate through the base substrate (110). In addition, the buffer layer (120) can provide a flat surface on the upper portion of the base substrate (110). The buffer layer (120) can be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride. Alternatively, the buffer layer (120) can be optionally omitted.

A semiconductor member (AC) may be placed on the buffer layer (120). The semiconductor member (AC) may be formed of amorphous silicon, polycrystalline silicon, oxide semiconductor, etc. The semiconductor member (AC) may include a source region, a channel region, and a drain region.

A first insulating layer (130) may be placed on the above semiconductor member (AC).

The first insulating layer (130) may be disposed on the buffer layer (120) and may cover the semiconductor member (AC). The first insulating layer (130) may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

A first conductive pattern may be arranged on the first insulating layer (130). The first conductive pattern may include a gate electrode of a transistor arranged in the display area (DA), a first capacitor electrode (E1) of a storage capacitor (CST), and a signal line.

A second insulating layer (140) may be disposed on the first conductive pattern including the first capacitor electrode (E1). The second insulating layer (140) may cover the first conductive pattern and be disposed on the first insulating layer (130). The second insulating layer (140) may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

A second conductive pattern may be arranged on the second insulating layer (140).

The second challenge pattern may include a gate electrode (GE) of a transistor arranged in the display area (DA), a second capacitor electrode (E2) of a storage capacitor (CST), and a signal line.

A third insulating layer (150) may be disposed on the second conductive pattern including the gate electrode (GE) and the second capacitor electrode (E2). The third insulating layer (150) may cover the second conductive pattern and be disposed on the second insulating layer (140). The third insulating layer (150) may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

A first planarization layer (160) may be disposed on the third insulating layer (150). The first planarization layer (160) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin. The first planarization layer (160) may planarize an upper surface of the display area (DA) on which the second conductive pattern including the gate electrode (GE) and the second capacitor electrode (E2) is disposed.

A third challenge pattern can be placed on the first flattening layer (160).

The third challenge pattern may include a connection electrode (EE) and a signal line arranged in the display area (DA). For example, the connection electrode (EE) may be connected to the second electrode (E2) of the storage capacitor (CST) through a contact hole formed in the first planarization layer (160).

A second planarization layer (170) may be disposed on the third conductive pattern including the connection electrode (EE). The second planarization layer (170) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin. The second planarization layer (170) may flatten the upper surface of the display area (DA) on which the third conductive pattern is disposed.

A protective insulating layer (180) may be placed on the second flattening layer (170). The protective insulating layer (180) may be formed using an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, metal, or metal oxide.

A fourth conductive pattern may be placed on the above protective insulating layer (180).

The fourth conductive pattern may include a source electrode (SE), a drain electrode (DE), and a signal line of a transistor (TR) disposed in the display area (DA). Each of the source electrode (SE) and the drain electrode (DE) may be connected to a source region and a drain region of the semiconductor member (AC) through a contact hole formed in the first insulating layer (130), the second insulating layer (140), the third insulating layer (150), the first planarization layer (160), the second planarization layer (170), and the protective insulating layer (180). In addition, the source electrode (SE) may be connected to the connection electrode (EE) through a contact hole formed in the second planarization layer (170) and the protective insulating layer (180).

A third planarization layer (190) may be disposed on the fourth conductive pattern including the source electrode (SE) and the drain electrode (DE). The third planarization layer (190) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin. The third planarization layer (190) may planarize an upper surface of the display area (DA) on which the fourth conductive pattern is disposed.

A pixel electrode (PE) may be arranged on the third planarization layer (190). The pixel electrode (PE) may be connected to the drain electrode (DE) of the transistor (TR) through a hole formed in the third planarization layer (190). The pixel electrode (PE) may be formed using a conductive material such as a metal or a transparent conductive oxide.

A pixel defining film (230) may be disposed on the pixel electrode (PE). The pixel defining film (230) may cover an edge of the pixel electrode (PE) and may be disposed on the third planarization layer (190). The pixel defining film (230) may include an opening that exposes a portion of the pixel electrode (PE). The opening may define a light-emitting area of the pixel. The pixel defining film (230) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

Referring to the groove area (GA) of the above display device (1000), a buffer layer (120) may be arranged on the base substrate (110).

A groove member (UG) may be placed on the above buffer layer (120).

The groove member (UG) includes a bottom portion (BP), a first side wall portion (WP1) extending from a first end of the bottom portion (BP) and positioned on the display area (DA) side, and a second side wall portion (WP2) extending from a second end of the bottom portion (BP) and positioned on the through hole (TH) side. At least one of the first and second side wall portions (WP1, WP2) may include an undercut that is concavely recessed in a direction perpendicular to the etched surfaces of the insulating layers.

The above bottom portion (BP) can be defined on the exposed buffer layer (120).

The first sidewall portion (WP1) may include a first sidewall (W1) and a first undercut (U11). The first sidewall (W1) may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The first undercut (U11) may be defined by a space that is concave toward the display area (DA) between the first sidewall (W1) and the protective insulating layer (180) that protrudes toward the through hole (TH) more than the first sidewall (W1). The first undercut (U11) has a first width corresponding to the space between the third insulating layer (150) and the protective insulating layer (180).

The above first side wall portion (WP1) has a first step (H11) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the first undercut (U11).

The above second side wall portion (WP2) may include a second side wall (W2) and a second undercut (U12).

The second sidewall (W2) may face the first sidewall (W1) and may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The second undercut (U12) may be defined by a space that is concave toward the through hole (TH) between the second sidewall (W2) and the protective insulating layer (180) that protrudes toward the display area (DA) more than the second sidewall (W2). The second undercut (U12) has a second width corresponding to the space between the third insulating layer (150) and the protective insulating layer (180). The second width is smaller than the first width of the first undercut (U11).

The second side wall portion (WP2) has a second step (H12) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the second undercut (U12). The second step (H12) is smaller than the first step (H11).

As illustrated in FIG. 3, an organic light-emitting layer (EL), a common electrode layer (CE), and a thin film encapsulation member (TEF) can be formed entirely in the display area (DA) and the groove area (GA).

The above organic light-emitting layer (EL) may be provided with a hole injection layer (HIL) and/or a hole transport layer (HTL) having excellent hole transport properties and suppressing the movement of electrons that are not combined in the organic light-emitting layer (240) to increase the chance of recombination of holes and electrons.

The common electrode layer (CE) may be disposed on the base substrate (110) on which the organic light-emitting layer (EL) is formed. The common electrode layer (CE) may be an opposite electrode of the pixel electrode (PE). The common electrode layer (CE) may be formed using a conductive material such as a metal or a transparent conductive oxide. An organic light-emitting diode (OLED) of a pixel may be defined in a region where the pixel electrode (PE), the organic light-emitting layer (EL), and the common electrode layer (CE) overlap.

The above organic light-emitting layer (EL) and the common electrode layer (CE) are disconnected by the first and second undercuts (U11, U12) formed on the first and second sidewall portions (WP1, WP2) of the groove member (UG), so that only the bottom portion (BP) may be formed without being formed on the first and second sidewall portions (WP1, WP2). Accordingly, the path through which impurities in the air, such as moisture and oxygen, which may be introduced through the organic light-emitting layer (EL), penetrate into the display area (DA) can be blocked.

The above thin film encapsulation member (TFE) can be placed on the base substrate (110) on which the common electrode layer (CE) is formed.

The above thin film encapsulation member (TFE) can prevent penetration of external moisture and oxygen. The thin film encapsulation member (TFE) can have at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer can be alternately laminated with each other. For example, the thin film encapsulation member (TFE) can include two inorganic layers and one organic layer therebetween, but is not limited thereto. In another embodiment, a sealing substrate can be provided instead of the thin film encapsulation member.

As described above, the groove member (UG) can enhance the effect of blocking the penetration path of impurities such as moisture and oxygen by forming the first step (H11) of the first side wall portion (WP1) corresponding to the display area (DA) side to be larger than the second step (H12) of the second side wall portion (WP2) corresponding to the through hole side.

Figures 4 to 10 are cross-sectional views for explaining a method of manufacturing the display device illustrated in Figure 3.

Referring to Fig. 4, a buffer layer (120) is formed on a base substrate (110). A semiconductor layer is formed on the buffer layer (120), and a semiconductor member (AC) can be formed using the semiconductor layer as a first mask.

A first insulating layer (130) is formed on the base substrate (110) on which the semiconductor member (AC) is formed.

A first conductive layer can be formed on the first insulating layer (130), and a first conductive pattern, for example, a first storage electrode (E1), can be formed using the first conductive layer as a second mask.

A second insulating layer (140) is formed on the base substrate (110) on which the first conductive pattern including the first storage electrode (E1) is formed.

A second conductive layer can be formed on the base substrate (110) on which the second insulating layer (140) is formed, and a second conductive pattern, for example, a gate electrode (GE) and a second storage electrode (E2), can be formed on the second conductive layer using a third mask.

After forming the second conductive pattern including the gate electrode (GE) and the second storage electrode (E2), impurities are doped into the semiconductor member (AC) using the gate electrode (GE) as a mask. Accordingly, the semiconductor member (AC) can be divided into a source region, a channel region, and a drain region.

A third insulating layer (150) is formed on the base substrate (110) on which the second conductive pattern including the gate electrode (GE) and the second storage electrode (E2) is formed.

The first, second and third insulating layers (130, 140, 150) are etched using a fourth mask. As the first, second and third insulating layers (130, 140, 150) are etched, a plurality of first contact holes (CH1) may be formed in the display area (DA) and a groove hole (GH) may be formed in the groove area (GA). The plurality of first contact holes (CH1) may expose a source area and a drain area of the semiconductor member (AC). The groove hole (GH) exposes the buffer layer (120). The groove hole (GH) includes a bottom portion (BP), a first sidewall (W1) corresponding to the display area (DA) side, and a second sidewall (W2) corresponding to the through hole (TH) side. The first and second side walls (W1, W2) may have a step corresponding to the thickness of the first, second and third insulating layers (130, 140, 150) sequentially laminated with respect to the bottom portion (BP).

Next, the second insulating layer (140) and/or the third insulating layer (150) are etched using the fifth mask. As the second insulating layer (140) and/or the third insulating layer (150) are etched, a plurality of second contact holes (CH2) are formed in the display area (DA). For example, the second contact holes (CH2) may expose the second storage electrode (E2).

Referring to FIG. 5, a first planarization layer (160) is formed on the base substrate (110) on which the first contact holes (CH1), the second contact holes (CH2), and the groove hole (GH) are formed, and the first planarization layer (160) can be patterned using a sixth mask.

The first planarization layer (160) may include a plurality of holes corresponding to the first and second contact holes (CH1, CH2) of the display area (DA). The first planarization layer (160) may form a first planarization member (161) having a first thickness (t1) that fills the inside of the groove hole (GH). The first planarization member (161) may be formed to fill the groove hole (GH) and partially cover an upper portion of the third insulating layer (150) beyond the first and second sidewalls (W1, W2).

Referring to FIG. 6, a third conductive layer is formed on the base substrate (110) on which the first flattening layer (160) and the first flattening member (161) are formed, and a third conductive pattern, for example, the connecting electrode (EE) can be formed on the third conductive layer using a seventh mask.

A second planarization layer (170) can be formed on the base substrate (110) on which the third conductive pattern including the connecting electrode (EE) is formed, and the second planarization layer (170) can be patterned using an eighth mask.

The second planarization layer (170) may include a plurality of holes corresponding to the first contact holes (CH1) of the display area (DA) and a hole exposing the connection electrode (EE). The second planarization layer (170) may form a second planarization member (171) having a second thickness (t2) in the groove area (GA).

The second flattening member (171) partially overlaps the first flattening member (161). The second flattening member (171) partially overlaps the first flattening member (161) so as to cover the first end of the first flattening member (161) and expose the second end of the first flattening member (161).

The first end of the second flattening member (171) may cover the first end of the first flattening member (161) adjacent to the first side wall (W1) and may be disposed on the third insulating layer (150). The second end of the second flattening member (171) may be disposed at a central portion of the first flattening member (161) so that the second end of the first flattening member (161) is exposed.

Referring to Fig. 7, a protective insulating layer (180) is formed on the base substrate (110) on which the second flattening layer (170) and the second flattening member (171) are formed. The protective insulating layer (180) can be formed using an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, metal, or metal oxide.

The above protective insulating layer (180) is etched using the ninth mask. The etched protective insulating layer (180) may include a plurality of holes corresponding to the first contact holes (CH1) and the holes exposing the connection electrode (EE).

The above protective insulating layer (180) can be placed on the third insulating layer (150) to cover the first and second flattening members (161, 171) of the groove area (GA).

Referring to Fig. 8, the fourth conductive layer is formed on the protective insulating layer (180) in which the plurality of holes are formed, and a fourth conductive pattern is formed on the base substrate (110) using the tenth mask. The fourth conductive pattern may include a source electrode (SE) and a drain electrode (DE) respectively connected to the source region and the drain region of the semiconductor member (AC).

A third planarization layer (190) is formed on the base substrate (110) on which the fourth conductive pattern including the source electrode (SE) and the drain electrode (DE) is formed, and the third planarization layer (190) can be patterned using an 11th mask.

The third planarization layer (190) may include a hole exposing the drain electrode (DE) of the display area (DA). The third planarization layer (190) may be removed from the groove area (GA).

A pixel electrode layer can be formed on the third flattening layer (190), and the pixel electrode layer can be patterned using a 12th mask to form a pixel electrode (PE) connected to the drain electrode (DE).

A pixel definition layer (230) can be formed on the base substrate (110) on which the pixel electrode (PE) is formed, and the pixel definition layer (230) can be patterned using a 13th mask.

The pixel definition layer (230) may include a first opening (OP1) exposing the pixel electrode (PE) of the display area (DA) and a second opening (OP2) exposing the protective insulating layer (180) corresponding to the groove hole (GH) of the groove area (GA).

Referring to Fig. 9, the protective insulating layer (180) exposed by the second opening (OP2) of the groove area (GA) is etched using the 13th mask. An etching hole (EH) is formed in the etched protective insulating layer (180) of the groove area (GA) that exposes at least one of the first and second planarizing members (161, 171).

Next, the first and second planarizing members (161, 171) exposed to the etching hole (EH) can be removed. For example, the first and second planarizing members (161, 171) can be removed through a wet etching process.

Referring to FIG. 10, when the first and second flattening members (161, 171) are removed, a groove member (UG) can be formed in the groove area (GA).

The groove member (UG) includes a first side wall portion (WP1) extending from the first end of the bottom portion (BP) and located on the display area (DA) side, and a second side wall portion (WP2) extending from the second end of the bottom portion (BP) and located on the through hole (TH) side.

The above bottom portion (BP) can be defined on the exposed buffer layer (120).

The first sidewall portion (WP1) may include a first sidewall (W1) and a first undercut (U11). The first sidewall (W1) may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The first undercut (U11) may be defined by a space that is concavely formed toward the display area (DA) between the first sidewall (W1) and the protective insulating layer (180) that protrudes more toward the through hole (TH) than the first sidewall (W1). The first undercut (U11) may have a width corresponding to a second thickness (t2) of the second flattening member (171).

The above first side wall portion (WP1) has a first step (H11) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the first undercut (U11).

The second side wall portion (WP2) may include a second side wall (W2) and a second undercut (U12). The second side wall (W2) may face the first side wall (W1) and may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The second undercut (U12) may be defined by a space that is concavely formed toward the through hole (TH) between the second side wall (W2) and the protective insulating layer (180) that protrudes toward the display area (DA) more than the second side wall (W2). The second undercut (U12) may have a width corresponding to the thickness of the first flattening member (161) formed on the protective insulating layer (180).

The second side wall portion (WP2) has a second step (H12) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the second undercut (U12). The second step (H12) is smaller than the first step (H11).

In the following, components that are identical to those in the previous embodiment are given the same drawing reference numerals and repetitive descriptions are omitted.

FIG. 11 is a cross-sectional view illustrating a display device according to one embodiment of the present invention.

Referring to FIG. 11, the display device (1000_1) includes a base substrate (110), and the base substrate (110) may include a display area (DA) and a groove area (GA).

Referring to the display area (DA) of the display device (1000_1), a buffer layer (120) may be placed on the base substrate (110).

A semiconductor member (AC) may be placed on the buffer layer (120). The semiconductor member (AC) may be formed of amorphous silicon, polycrystalline silicon, oxide semiconductor, etc. The semiconductor member (AC) may include a source region, a channel region, and a drain region.

A first insulating layer (130) may be placed on the above semiconductor member (AC).

The first insulating layer (130) may be disposed on the buffer layer (120) and may cover the semiconductor member (AC). The first insulating layer (130) may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

A first conductive pattern may be arranged on the first insulating layer (130). The first conductive pattern may include a gate electrode of a transistor arranged in the display area (DA), a first capacitor electrode (E1) of a storage capacitor (CST), and a signal line.

A second insulating layer (140) may be disposed on the first conductive pattern including the first capacitor electrode (E1). The second insulating layer (140) may cover the first conductive pattern and be disposed on the first insulating layer (130). The second insulating layer (140) may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

A second conductive pattern may be arranged on the second insulating layer (140).

The second challenge pattern may include a gate electrode (GE) of a transistor arranged in the display area (DA), a second capacitor electrode (E2) of a storage capacitor (CST), and a signal line.

A third insulating layer (150) may be disposed on the second conductive pattern including the gate electrode (GE) and the second capacitor electrode (E2). The third insulating layer (150) may cover the second conductive pattern (GE, E2) and may be disposed on the second insulating layer (140). The third insulating layer (150) may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride.

A first planarization layer (160) may be placed on the third insulating layer (150). The first planarization layer (160) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

A third challenge pattern can be placed on the first flattening layer (160).

The third challenge pattern may include a connection electrode (EE) and a signal line arranged in the display area (DA). For example, the connection electrode (EE) may be connected to the second electrode (E2) of the storage capacitor (CST) through a contact hole formed in the first planarization layer (160).

A second planarization layer (170) may be disposed on the third conductive pattern including the above-mentioned connecting electrode (EE). The second planarization layer (170) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

A fourth challenge pattern can be placed on the second flattening layer (170).

The fourth challenge pattern may include a source electrode (SE), a drain electrode (DE), and a signal line of a transistor (TR) arranged in the display area (DA). Each of the source electrode (SE) and the drain electrode (DE) may be connected to a source region and a drain region of the semiconductor member (AC).

A third planarization layer (190) may be arranged on the fourth conductive pattern including the source electrode (SE) and the drain electrode (DE). The third planarization layer (190) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

A protective insulating layer (180) may be placed on the third flattening layer (190). The protective insulating layer (180) may be formed using an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, metal, or metal oxide.

A pixel electrode (PE) may be placed on the above protective insulating layer (180).

The above pixel electrode (PE) can be connected to the drain electrode (DE) of the transistor (TR) through a contact hole.

A pixel defining film (230) may be placed on the pixel electrode (PE). The pixel defining film (230) may cover an edge of the pixel electrode (PE) and may be placed on the protective insulating layer (180). The pixel defining film (230) may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

Referring to the groove area (GA) of the above display device (1000_1), a buffer layer (120) may be arranged on the base substrate (110).

A groove member (UG_1) may be placed on the above buffer layer (120).

The groove member (UG_1) includes a bottom portion (BP), a first side wall portion (WP1) extending from a first end of the bottom portion (BP) and located on the display area (DA) side, and a second side wall portion (WP2) extending from a second end of the bottom portion (BP) and located on the through hole (TH) side.

The above bottom portion (BP) can be defined on the exposed buffer layer (120).

The first sidewall portion (WP1) may include a first sidewall (W1) and a first undercut (U21). The first sidewall (W1) may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The first undercut (U21) may be defined by a space that is concavely formed toward the display area (DA) between the first sidewall (W1) and the protective insulating layer (180) that protrudes further toward the through hole (TH) than the first sidewall (W1). The width of the first undercut (U21) may be greater than the width of the first undercut (U11) according to the previous embodiment illustrated in FIG. 3.

The first side wall portion (WP1) has a first step (H21) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the first undercut (U21). The first step (H21) of the first side wall portion (WP1) may be greater than the first step (H11) of the first side wall portion (WP1) according to the previous embodiment illustrated in FIG. 3.

The above second side wall portion (WP2) may include a second side wall (W2) and a second undercut (U22).

The second side wall (W2) may face the first side wall (W1) and may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The second undercut (U22) may be defined by a space that is concavely formed toward the through hole (TH) between the second side wall (W2) and the protective insulating layer (180) that protrudes toward the display area (DA) more than the second side wall (W2).

The width of the second undercut (U22) may be greater than the width of the second undercut (U12) according to the previous embodiment illustrated in FIG. 3.

The second side wall portion (WP2) has a second step (H22) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the second undercut (U22). The second step (H22) is smaller than the first step (H21). The second step (H22) of the second side wall portion (WP2) may be larger than the second step (H21) of the second side wall portion (WP2) according to the previous embodiment illustrated in FIG. 3.

As illustrated in FIG. 11, an organic light-emitting layer (EL), a common electrode layer (CE), and a thin film encapsulation member (TEF) can be formed entirely in the display area (DA) and the groove area (GA).

The above organic light-emitting layer (EL) and the common electrode layer (CE) are disconnected by the first and second undercuts (U21, U22) formed on the first and second sidewall portions (WP1, WP2) of the groove member (UG_1), so that only the bottom portion (BP) may be formed without being formed on the first and second sidewall portions (WP1, WP2). Accordingly, the path through which impurities in the air, such as moisture and oxygen, which may be introduced through the organic light-emitting layer (EL), penetrate into the display area (DA) can be blocked.

As described above, the groove member (UG_1) can improve the blocking effect of a path through which impurities such as moisture and oxygen penetrate into the display device by forming the first step (H21) of the first side wall portion (WP1) corresponding to the display area (DA) side larger than the second step (H22) of the second side wall portion (WP2) corresponding to the through hole side.

In addition, the display device according to the present embodiment can improve the effect of blocking the moisture penetration path since the first and second steps of the first and second side wall portions are large compared to the display device according to the previous embodiment illustrated in FIG. 3.

Figures 12 to 14 are cross-sectional views for explaining a method of manufacturing the display device illustrated in Figure 11.

Referring to FIG. 12, a semiconductor member (AC) can be formed on a base substrate (110).

A first insulating layer (130) is formed on the base substrate (110) on which the semiconductor member (AC) is formed.

A first conductive pattern, for example, a first storage electrode (E1), can be formed on the first insulating layer (130).

A second insulating layer (140) is formed on the base substrate (110) on which the first conductive pattern including the first storage electrode (E1) is formed.

A second conductive pattern, for example, a gate electrode (GE) and a second storage electrode (E2), can be formed on the second insulating layer (140).

After forming the second conductive pattern including the gate electrode (GE) and the second storage electrode (E2), the semiconductor member (AC) is doped with impurities. Accordingly, the semiconductor member (AC) can be divided into a source region, a channel region, and a drain region.

A third insulating layer (150) is formed on the base substrate (110) on which the second conductive pattern including the gate electrode (GE) and the second storage electrode (E2) is formed.

The first, second and third insulating layers (130, 140, 150) are etched to form a plurality of contact holes in the display area (DA) and a groove hole (GH) in the groove area (GA). The groove hole (GH) includes a bottom portion (BP), a first sidewall (W1) corresponding to the display area (DA) side and a second sidewall (W2) corresponding to the through hole (TH) side. The first and second sidewalls (W1, W2) may have a step corresponding to the stacking thickness of the first, second and third insulating layers (130, 140, 150) that are sequentially stacked.

A first planarization layer (160) is formed on the base substrate (110) on which the plurality of contact holes and the groove hole (GH) are formed. The first planarization layer (160) may include a plurality of holes corresponding to the plurality of contact holes of the display area (DA). The first planarization layer (160) may include a first planarization member (161) filling the groove hole (GH). The first planarization member (161) may be formed with a first thickness (t1) that is thicker than the laminated thickness of the first, second, and third insulating layers (130, 140, 150), and may be formed to cover the third insulating layer (150) beyond the first and second sidewalls (W1, W2).

A third conductive pattern, for example, the connecting electrode (EE), can be formed on the base substrate (110) on which the first flattening layer (160) and the first flattening member (161) are formed.

A second planarization layer (170) is formed on the base substrate (110) on which the third conductive pattern including the connection electrode (EE) is formed. The second planarization layer (170) may include a plurality of holes corresponding to a plurality of contact holes of the display area (DA) and a hole exposing the connection electrode (EE). The second planarization layer (170) may include a second planarization member (171) formed in the groove area (GA).

The second flattening member (171) has a second thickness (t2) and is placed on the first flattening member (161) so as to completely cover the first flattening member (161) that fills the groove hole (GH).

A fourth conductive pattern including a source electrode (SE) and a drain electrode (DE) is formed on the base substrate (110) on which the second flattening layer (170) and the second flattening member (171) are formed.

A third planarization layer (190) is formed on the base substrate (110) on which the fourth conductive pattern including the source electrode (SE) and the drain electrode (DE) is formed.

The third planarization layer (190) may include a hole exposing the drain electrode (DE) in the display area (DA). The third planarization layer (190) may include a third planarization member (191) formed in the groove area (GA).

The third flattening member (191) has a third thickness (t3) and partially overlaps the second flattening member (171). The third flattening member (191) covers the first end of the second flattening member (171) and exposes the second end of the second flattening member (171).

The first end of the third flattening member (191) covers the first end of the second flattening member (171) adjacent to the first side wall (W1) and is disposed on the third insulating layer (150). The second end of the third flattening member (191) may be disposed at the central portion of the second flattening member (171) so that the second end of the second flattening member (171) is exposed.

A protective insulating layer (180) is formed on the base substrate (110) on which the third flattening layer (190) and the third flattening member (191) are formed. The protective insulating layer (180) can be formed using an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, metal, or metal oxide.

Referring to FIG. 13, a pixel electrode (PE) connected to the drain electrode (DE) can be formed on the protective insulating layer (180).

A pixel definition layer (230) is formed on the base substrate (110) on which the pixel electrode (PE) is formed.

The pixel definition layer (230) may include a first opening (OP1) exposing the pixel electrode (PE) of the display area (DA) and a second opening (OP2) exposing the protective insulating layer (180) corresponding to the groove hole (GH) of the groove area (GA).

Referring to Fig. 14, the protective insulating layer (180) exposed by the second opening (OP2) of the groove area (GA) is etched using a mask. An etching hole (EH) is formed in the etched protective insulating layer (180) of the groove area (GA) that exposes at least one of the first, second, and third planarizing members (161, 171, 191).

Next, the first, second and third planarizing members (161, 171, 191) exposed to the etching hole (EH) can be removed. For example, the first, second and third planarizing members (161, 171, 191) can be removed through a wet etching process.

By removing the first, second and third flattening members (161, 171, 191), a groove member (UG_1) can be formed in the groove area (GA).

The groove member (UG_1) includes a bottom portion (BP), a first side wall portion (WP1) extending from a first end of the bottom portion (BP) and located on the display area (DA) side, and a second side wall portion (WP2) extending from a second end of the bottom portion (BP) and located on the through hole (TH) side.

The above bottom portion (BP) can be defined on the exposed buffer layer (120).

The first sidewall portion (WP1) may include a first sidewall (W1) and a first undercut (U21). The first sidewall (W1) may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The first undercut (U21) may be defined by a space that is concavely formed toward the display area (DA) between the first sidewall (W1) and the protective insulating layer (180) that protrudes toward the through hole (TH) more than the first sidewall (W1). The width of the first undercut (U21) may correspond to the laminated thickness (t2+t3) of the second and third flattening members (171, 191). The width (t2+t3) of the first undercut (U21) may be larger than the width of the first undercut (U11) corresponding to the thickness (t2) of the second flattening member (171) according to the previous embodiment illustrated in FIG. 3.

The first side wall portion (WP1) has a first step (H21) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the first undercut (U21). The first step (H21) of the first side wall portion (WP1) may be greater than the first step (H11) of the first side wall portion (WP1) according to the previous embodiment illustrated in FIG. 3.

The above second side wall portion (WP2) may include a second side wall (W2) and a second undercut (U22).

The second side wall (W2) may face the first side wall (W1) and may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The second undercut (U22) may be defined by a space that is concavely formed toward the through hole (TH) between the second side wall (W2) and the protective insulating layer (180) that protrudes toward the display area (DA) more than the second side wall (W2).

The width of the second undercut (U22) may correspond to the laminate thickness (t2) of the second flattening member (171). The width (t2) of the second undercut (U22) may be larger than the width of the second undercut (U12) according to the previous embodiment illustrated in FIG. 3.

The second side wall portion (WP2) has a second step (H22) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the second undercut (U22). The second step (H22) is smaller than the first step (H21). The second step (H22) of the second side wall portion (WP2) may be larger than the second step (H21) of the second side wall portion (WP2) according to the previous embodiment illustrated in FIG. 3.

FIG. 15 is a cross-sectional view illustrating a display device according to one embodiment of the present invention.

Referring to FIG. 15, the display device (1000_2) includes a base substrate (110), and the base substrate (110) may include a display area (DA) and a groove area (GA).

Referring to the display area (DA) of the display device (1000_2), it may include substantially the same components as the display area (DA) of the display device (1000_1) according to the previous embodiment described with reference to FIG. 11. Therefore, a repeated description is omitted.

Meanwhile, referring to the groove area (GA) of the display device (1000_2), a buffer layer (120) may be placed on the base substrate (110).

A groove member (UG_2) may be placed on the above buffer layer (120).

The groove member (UG_2) includes a bottom portion (BP), a first side wall portion (WP1) extending from a first end of the bottom portion (BP) and located on the display area (DA) side, and a second side wall portion (WP2) extending from a second end of the bottom portion (BP) and located on the through hole (TH) side.

The above bottom portion (BP) can be defined on the exposed buffer layer (120).

The first sidewall portion (WP1) may include a first sidewall (W1) and a first undercut (U31). The first sidewall (W1) may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The first undercut (U31) may be defined by a space that is concavely formed toward the display area (DA) between the first sidewall (W1) and the protective insulating layer (180) that protrudes further toward the through hole (TH) than the first sidewall (W1). The width of the first undercut (U31) may be the same as the width of the first undercut (U21) according to the previous embodiment illustrated in FIG. 11.

The first side wall portion (WP1) has a first step (H31) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the first undercut (U31). The first step (H31) of the first side wall portion (WP1) is larger than the first step (H11) of the first side wall portion (WP1) according to the previous embodiment illustrated in FIG. 3, and may be the same as the first step (H21) of the first side wall portion (WP1) according to the previous embodiment illustrated in FIG. 11.

The above second side wall portion (WP2) may include a second side wall (W2) and a second undercut (U32).

The second side wall (W2) may face the first side wall (W1) and may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The second undercut (U32) may be defined by a space that is concavely formed toward the through hole (TH) between the second side wall (W2) and the protective insulating layer (180) that protrudes toward the display area (DA) more than the second side wall (W2).

The width of the second undercut (U32) may be the same as the second undercut (U12) according to the previous embodiment illustrated in FIG. 3.

The second side wall portion (WP2) has a second step (H32) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the second undercut (U32). The second step (H32) is smaller than the first step (H31). The second step (H32) of the second side wall portion (WP2) may be the same as the second step (H21) of the second side wall portion (WP2) according to the previous embodiment illustrated in FIG. 3.

The above organic light-emitting layer (EL) and the common electrode layer (CE) are disconnected by the first and second undercuts (U31, U32) formed on the first and second sidewall portions (WP1, WP2) of the groove member (UG_2), so that only the bottom portion (BP) may be formed without being formed on the first and second sidewall portions (WP1, WP2). Accordingly, the path through which impurities in the air, such as moisture and oxygen, which may be introduced through the organic light-emitting layer (EL), penetrate into the display area (DA) can be blocked.

As described above, the groove member (UG_2) can improve the blocking effect of a path through which impurities such as moisture and oxygen penetrate into the display device by forming the first step (H31) of the first side wall portion (WP1) corresponding to the display area (DA) side larger than the second step (H32) of the second side wall portion (WP2) corresponding to the through hole side.

FIGS. 16 and 17 are cross-sectional views for explaining a method of manufacturing the display device illustrated in FIG. 15.

Referring to FIG. 16, a semiconductor member (AC) can be formed on a base substrate (110).

A first insulating layer (130) is formed on the base substrate (110) on which the semiconductor member (AC) is formed.

A first conductive pattern, for example, a first storage electrode (E1), can be formed on the first insulating layer (130).

A second insulating layer (140) is formed on the base substrate (110) on which the first conductive pattern including the first storage electrode (E1) is formed.

A second conductive pattern, for example, a gate electrode (GE) and a second storage electrode (E2), can be formed on the second insulating layer (140).

After forming the second conductive pattern including the gate electrode (GE) and the second storage electrode (E2), the semiconductor member (AC) is doped with impurities. Accordingly, the semiconductor member (AC) can be divided into a source region, a channel region, and a drain region.

A third insulating layer (150) is formed on the base substrate (110) on which the second conductive pattern including the gate electrode (GE) and the second storage electrode (E2) is formed.

The first, second and third insulating layers (130, 140, 150) are etched to form a plurality of contact holes in the display area (DA) and a groove hole (GH) in the groove area (GA). The groove hole (GH) includes a bottom portion (BP), a first sidewall (W1) corresponding to the display area (DA) side and a second sidewall (W2) corresponding to the through hole (TH) side. The first and second sidewalls (W1, W2) may have a step corresponding to the stacking thickness of the first, second and third insulating layers (130, 140, 150) that are sequentially stacked.

A first planarization layer (160) is formed on the base substrate (110) on which the plurality of contact holes and the groove hole (GH) are formed. The first planarization layer (160) may include a plurality of holes corresponding to the plurality of contact holes of the display area (DA). The first planarization layer (160) may include a first planarization member (161) filling the groove hole (GH). The first planarization member (161) may be formed with a first thickness (t1) that is thicker than the laminated thickness of the first, second, and third insulating layers (130, 140, 150), and may be formed to cover the third insulating layer (150) beyond the first and second sidewalls (W1, W2).

A third conductive pattern, for example, the connecting electrode (EE), can be formed on the base substrate (110) on which the first flattening layer (160) and the first flattening member (161) are formed.

A second planarization layer (170) is formed on the base substrate (110) on which the third conductive pattern including the connection electrode (EE) is formed. The second planarization layer (170) may include a plurality of holes corresponding to a plurality of contact holes of the display area (DA) and a hole exposing the connection electrode (EE). The second planarization layer (170) may include a second planarization member (171) formed in the groove area (GA).

The second flattening member (171) has a second thickness (t2) and partially overlaps the first flattening member (161) so as to cover the first end of the first flattening member (161) and expose the second end of the first flattening member (161).

The first end of the second flattening member (171) covers the first end of the first flattening member (161) adjacent to the first side wall (W1) and is disposed on the third insulating layer (150). The second end of the second flattening member (171) may be disposed at the central portion of the first flattening member (161) so that the second end of the first flattening member (161) is exposed.

A fourth conductive pattern including a source electrode (SE) and a drain electrode (DE) is formed on the base substrate (110) on which the second flattening layer (170) and the second flattening member (171) are formed.

A third planarization layer (190) is formed on the base substrate (110) on which the fourth conductive pattern including the source electrode (SE) and the drain electrode (DE) is formed.

The third planarization layer (190) may include a hole exposing the drain electrode (DE) in the display area (DA). The third planarization layer (190) may include a third planarization member (191) formed in the groove area (GA).

The third flattening member (191) has a third thickness (t3), covers the first end of the second flattening member (171), and overlaps the second flattening member (171).

The first end of the third flattening member (191) covers the first end of the second flattening member (171) adjacent to the first side wall (W1) and is disposed on the third insulating layer (150). The second end of the third flattening member (191) overlaps the second end of the second flattening member (171) and can be disposed at the central portion of the first flattening member (161) so that the second end of the first flattening member (161) is exposed.

A protective insulating layer (180) is formed on the base substrate (110) on which the third flattening layer (190) and the third flattening member (191) are formed. The protective insulating layer (180) can be formed using an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, metal, or metal oxide.

Referring to FIG. 17, a pixel electrode (PE) connected to the drain electrode (DE) can be formed on the protective insulating layer (180).

A pixel definition layer (230) is formed on the base substrate (110) on which the pixel electrode (PE) is formed.

The pixel definition layer (230) may include a first opening (OP1) exposing the pixel electrode (PE) of the display area (DA) and a second opening (OP2) exposing the protective insulating layer (180) corresponding to the groove hole (GH) of the groove area (GA).

The protective insulating layer (180) exposed by the second opening (OP2) of the groove area (GA) is etched using a mask. An etching hole (EH) is formed in the etched protective insulating layer (180) of the groove area (GA) that exposes at least one of the first, second, and third planarizing members (161, 171, 191).

Next, the first, second and third planarizing members (161, 171, 191) exposed to the etching hole (EH) can be removed. For example, the first, second and third planarizing members (161, 171, 191) can be removed through a wet etching process.

By removing the first, second and third flattening members (161, 171, 191), a groove member (UG_3) can be formed in the groove area (GA).

The groove member (UG_3) includes a bottom portion (BP), a first side wall portion (WP1) extending from a first end of the bottom portion (BP) and located on the display area (DA) side, and a second side wall portion (WP2) extending from a second end of the bottom portion (BP) and located on the through hole (TH) side.

The above bottom portion (BP) can be defined on the exposed buffer layer (120).

The first sidewall portion (WP1) may include a first sidewall (W1) and a first undercut (U31). The first sidewall (W1) may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The first undercut (U31) may be defined by a space that is concavely formed toward the display area (DA) between the first sidewall (W1) and the protective insulating layer (180) that protrudes toward the through hole (TH) more than the first sidewall (W1). The width of the first undercut (U31) may be the same as the width of the first undercut (U21) according to the previous embodiment illustrated in FIG. 11.

The first side wall portion (WP1) has a first step (H31) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the first undercut (U31). The first step (H31) of the first side wall portion (WP1) is larger than the first step (H11) of the first side wall portion (WP1) according to the previous embodiment illustrated in FIG. 3, and may be the same as the first step (H21) of the first side wall portion (WP1) according to the previous embodiment illustrated in FIG. 11.

The above second side wall portion (WP2) may include a second side wall (W2) and a second undercut (U32).

The second side wall (W2) may face the first side wall (W1) and may be defined by the first, second and third insulating layers (130, 140, 150) sequentially laminated on the buffer layer (120). The second undercut (U32) may be defined by a space that is concavely formed toward the through hole (TH) between the second side wall (W2) and the protective insulating layer (180) that protrudes toward the display area (DA) more than the second side wall (W2).

The width of the second undercut (U32) may be the same as the second undercut (U12) according to the previous embodiment illustrated in FIG. 3.

The second side wall portion (WP2) has a second step (H32) defined from the buffer layer (120) of the bottom portion (BP) to the protective insulation layer (180) of the second undercut (U32). The second step (H32) is smaller than the first step (H31). The second step (H32) of the second side wall portion (WP2) may be the same as the second step (H21) of the second side wall portion (WP2) according to the previous embodiment illustrated in FIG. 3.

According to the embodiments of the present invention, the organic light-emitting layer and the common electrode layer can be disconnected by the first and second undercuts formed on the first and second sidewall portions of the groove member. Accordingly, the path through which impurities such as moisture and oxygen in the air that can be introduced through the organic light-emitting layer (EL) penetrate into the display area (DA) can be blocked.

In addition, the groove member can improve the effect of blocking the path through which impurities such as moisture and acid water penetrate from the outside into the inside of the display device by forming the first step of the first side wall portion corresponding to the display area side larger than the second step of the second side wall portion corresponding to the through hole side.

The display device according to exemplary embodiments of the present invention can be applied to display devices included in computers, laptops, mobile phones, smart phones, smart pads, PMPs, PDAs, MP3 players, etc.

Above, the conductive wire for a display device, the display device, and the manufacturing method of the display device according to exemplary embodiments of the present invention have been described with reference to the drawings, but the described embodiments are exemplary and may be modified and changed by a person skilled in the art without departing from the technical spirit of the present invention as described in the claims below.

Claims (20)

A substrate having a through hole formed within a display area in which pixels are arranged; and
It is arranged in an area between the display area and the through hole, and includes a bottom portion, a first side wall portion on the display area side having a first step from the bottom portion, and a second side wall portion on the through hole side facing the first side wall portion and having a second step smaller than the bottom portion and the first step.
A display device including a groove member, wherein the first side wall portion includes a first undercut having a first width, and the second side wall portion includes a second undercut having a second width smaller than the first width. A display device in accordance with claim 1, wherein each of the first and second sidewall portions includes a sidewall corresponding to an etched surface on which a plurality of insulating layers are etched, and includes an undercut that is concavely formed in a direction perpendicular to the etched surface. In the second paragraph, a buffer layer disposed on the substrate;
A semiconductor member disposed on the above buffer layer;
A first insulating layer disposed on the semiconductor member;
A first conductive pattern disposed on the first insulating layer;
A second insulating layer disposed on the first challenge pattern;
A second conductive pattern disposed on the second insulating layer; and
Including a third insulating layer disposed on the second challenge pattern,
A display device characterized in that the height of the side wall corresponds to the laminated thickness of the first, second and third insulating layers. delete In the third paragraph, a third conductive pattern disposed on the third insulating layer;
A first planarizing layer disposed between the third insulating layer and the third conductive pattern;
A fourth challenge pattern arranged on the third challenge pattern;
A second flattening layer disposed between the third challenge pattern and the fourth challenge pattern;
a pixel electrode arranged on the fourth challenge pattern; and
A display device further comprising a third planarizing layer disposed between the fourth challenge pattern and the pixel electrode. A display device in accordance with claim 5, wherein the first width of the first undercut corresponds to the thickness of the second flattening layer of the display area. A display device in claim 6, further comprising a protective insulating layer disposed between the second flattening layer and the fourth conductive pattern. A display device in claim 5, characterized in that the first width of the first undercut corresponds to the laminated thickness of the second flattening layer and the third flattening layer disposed on the second flattening layer in the display area. A display device according to claim 8, further comprising a protective insulating layer disposed between the third flattening layer and the pixel electrode. A display device, characterized in that in claim 8, the second width of the second undercut corresponds to the thickness of the second flattening layer. A step of forming a through hole within a display area of a substrate on which pixels are arranged; and
A step of forming a groove member including a bottom portion, a first side wall portion on the display area side having a first step from the bottom portion, and a second side wall portion on the through hole side facing the first side wall portion and having a second step smaller than the bottom portion and the first step, in an area between the display area and the through hole,
A method for manufacturing a display device further comprising the step of forming a first undercut having a first width on the first sidewall portion and forming a second undercut having a second width smaller than the first width on the second sidewall portion. delete In claim 11, a step of forming a buffer layer on the substrate;
A step of forming a semiconductor member on the above buffer layer;
A step of forming a first insulating layer on the semiconductor member;
A step of forming a first conductive pattern on the first insulating layer;
A step of forming a second insulating layer on the first challenge pattern;
A step of forming a second conductive pattern on the second insulating layer; and
A method for manufacturing a display device further comprising the step of forming a third insulating layer on the second challenge pattern. A method for manufacturing a display device, further comprising the step of etching the first, second and third insulating layers in the 13th paragraph to form a groove hole including a first sidewall, a second sidewall facing the first sidewall and a bottom portion exposing the buffer layer. In claim 14, a step of forming a third conductive pattern on the third insulating layer;
A step of forming a first planarizing layer disposed between the third insulating layer and the third conductive pattern;
A step of forming a fourth challenge pattern on the third challenge pattern;
A step of forming a second flattening layer between the third challenge pattern and the fourth challenge pattern;
A step of forming a pixel electrode on the fourth challenge pattern; and
A method for manufacturing a display device further comprising the step of forming a third planarization layer between the fourth challenge pattern and the pixel electrode. A method for manufacturing a display device, further comprising the step of forming a protective insulating layer between the second flattening layer and the fourth conductive pattern in claim 15. In the 16th paragraph, a step of forming a first flattening member within the groove hole;
A step of forming a second flattening member partially overlapping the first flattening member so as to cover a first end of the first flattening member and expose a second end of the first flattening member;
A step of forming the protective insulating layer to cover the first and second flattening members;
A step of etching the protective insulating layer to form an etching hole exposing at least one of the first and second planarizing members; and
A method for manufacturing a display device further comprising the step of forming the groove member by removing the first and second planarizing members through the etching hole. A method for manufacturing a display device, further comprising the step of forming a protective insulating layer between the third flattening layer and the pixel electrode in claim 15. In claim 18, a step of forming a first flattening member within the groove hole;
A step of forming a second flattening member overlapping the first flattening member so as to cover the first end and the second end of the first flattening member;
A step of forming a third flattening member partially overlapping the second flattening member so as to cover the first end of the second flattening member and expose the second end of the second flattening member;
A step of forming a protective insulating layer to cover the second and third flattening members;
A step of etching the protective insulating layer to form an etching hole exposing at least one of the second and third planarizing members; and
A method for manufacturing a display device further comprising the step of forming the groove member by removing the first, second and third planarizing members through the etching hole. In claim 18, a step of forming a first flattening member within the groove hole;
A step of forming a second flattening member partially overlapping the first flattening member so as to cover a first end of the first flattening member and expose a second end of the first flattening member;
A step of forming a third flattening member overlapping the second flattening member so as to cover the first end of the second flattening member;
A step of forming a protective insulating layer to cover the first, second and third flattening members;
A step of etching the protective insulating layer to form an etching hole exposing at least one of the first, second and third planarizing members; and
A method for manufacturing a display device further comprising the step of forming the groove member by removing the first, second and third planarizing members through the etching hole.

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