KR102693205B1 - Memory unit performing logic operation with page buffer and logic operation method using the same - Google Patents

Abstract

The present invention relates to a memory unit that performs a logic operation with a page buffer and a logic operation method using the same. The present invention relates to a logic operation method using the same by using the existing page buffer circuit as is or slightly modifying it without having a separate circuit such as an operation circuit in the memory device. It has the effect of being able to perform calculations.

Description

Memory unit that performs logic operations with a page buffer and logic operation method using the same {MEMORY UNIT PERFORMING LOGIC OPERATION WITH PAGE BUFFER AND LOGIC OPERATION METHOD USING THE SAME}

The present invention was proposed to solve problems such as bottlenecks caused by data movement between the central processing unit (CPU) and memory units in von Neumann-based computing systems, and moves data to the CPU for logic operations. It relates to a device and method for performing logic operations with a page buffer within a memory unit without processing the same.

The current computing system based on the von Neumann architecture has a von Neumann bottleneck and a memory wall problem caused by data movement between the processing unit within the CPU and the memory unit.

Figure 1 is a schematic diagram showing a logic operation method in an existing von Neumann-based computing system 10'. According to this, data (a, b) stored in specific memory cells of the memory cell array 112 in the memory device 110 is processed through the bus 240 connected between the memory unit 100 and the processing unit 200. It is moved to the unit 200 and operated on in the arithmetic operation unit 220, and as a result, f(a,b) is sent back to the memory unit 100 through the bus 240 and stored. As the amount of data increases, it increases. As time goes by, bus bottlenecks and resulting memory barrier problems become more inevitable.

To solve the above problem, in-memory computing research has been actively conducted recently. Representative prior technologies include Korean Patent Publication No. 10-2020-0075525 and Registered Patent No. 10-1635902. However, the former uses a separate calculation circuit, and the latter uses a separate detection circuit.

Accordingly, the present invention seeks to provide a memory unit that performs logic operations using a page buffer by using the existing page buffer circuit as is or slightly modifying it, and a logic operation method using the same.

In order to achieve the above object, the memory unit according to the present invention is composed of a memory device and a memory controller, wherein the memory device includes a memory cell array, a page buffer block connected to bit lines of the memory cell array, and It includes an A latch circuit is connected in parallel to perform a logic operation with an internal operand stored in the memory cell array or an external operand input to the input/output device, and the control logic is further provided with LIP control logic for the logic operation. , The memory controller is further equipped with a LIP controller for performing the logic operation through the LIP control logic.

The plurality of latch circuits include circuits including an S-latch, a P-latch, and a Q-latch having the same circuit configuration connected in parallel between an upper node and a lower node, and at the upper node, one or more of the bit lines and The supply voltage terminal is connected in parallel with bit line selection transistors and an initialization transistor, and the lower node has a ground transistor through which the voltage of the upper node is applied to the gate and a PBRST transistor through which the PBRST signal of the LIP control logic is applied to the gate. Each can be connected in parallel to the ground terminal.

The same circuit configuration includes a data transfer transistor and an inverting data transfer transistor connected in parallel to the upper node and opened and closed by the TRAN and TRANn signals of the LIP control logic, respectively; an inverted data driving transistor connected between the data moving transistor and the ground terminal and opened and closed by the voltage of the inverted data storage node; a data drive transistor connected between the inverting data transfer transistor and the ground terminal and opened and closed by the voltage of the data storage node; First and second inverters whose input and output terminals are interconnected and connected between the data storage node and the inverted data storage node; an RST transistor opened and closed by the RST signal of the LIP control logic between the data storage node and the bottom node; And it may include a SET transistor opened and closed by the SET signal of the LIP control logic between the inverted data storage node and the lower node.

In the logic operation method using the memory unit, the S-latch, which is one of a plurality of latch circuits in the page buffer block, is used as an operation result storage latch, and the remaining P-latches and the Q-latches are used to store the operation result inside the memory cell array. A first step of storing data stored in or data received from an external source through the input/output device; and a second step of initializing the upper node to a data “1” state and initializing the data storage node of the S-latch to a data “0” or data “1” state.

The TRAN signal or the TRANn signal is applied simultaneously or sequentially to one or more of the P-latch and the Q-latch to transfer the data stored in the P-latch and the Q-latch to the upper node to perform data movement or logic. A third step of calculation may be further included.

In the second step, the initialization of the upper node is performed by turning on the initialization transistor with a PRECHSO signal to apply a supply voltage (V _DD ) to the upper node to set it to a data "1" state, and the S-latch Initialization of the data storage node is performed in the initialization state of the upper node by turning on the RST transistor with an SRST signal to a data "0" state or by turning on the SET transistor with an SSET signal to a data "1" state, and after the third step. In the third step, if the data of the top node is “0” as a result of the data movement or the logic operation, the data of the data storage node of the S-latch is maintained in an initialized state, and the data of the top node is “0”. If it is 1", the SET transistor is turned on with the SSET signal to store the data in the data storage node of the S-latch as "1", or the RST transistor is turned on with the SRST signal to store the data in the data storage node of the S-latch as "1". A fourth step of storing the inverted data as “0” may be further included.

연산을 수행하고, 상기 제 4 단계에서 상기 RST 트랜지스터에 SRST 신호로 턴온시켜 상기 S-래치의 데이터 저장 노드의 데이터는 상기 연산의 반전 데이터(

)가 저장되는 것으로 OR 연산을 수행할 수 있다.In the first step, data “a” is stored in the P-latch and data “b” is stored in the Q-latch, and in the second step, the data storage node of the S-latch is initialized in the SET transistor. It is turned on by the SSET signal to set the data to "1" state, and in the third step, the TRANn signal is applied simultaneously or sequentially to the P-latch and the Q-latch to change the respective data of the P-latch and the Q-latch. Move the inverted data stored in the storage node to the top node

The operation is performed, and in the fourth step, the RST transistor is turned on with an SRST signal so that the data of the data storage node of the S-latch is the inverted data of the operation (

) is stored, so an OR operation can be performed.

연산을 수행하고, 상기 제 4 단계에서 상기 SET 트랜지스터에 SSET 신호로 턴온시켜 상기 S-래치의 데이터 저장 노드의 데이터는 상기 연산의 결과 데이터가 저장되는 것으로 AND 연산을 수행할 수 있다.In the first step, data “a” is stored in the P-latch and data “b” is stored in the Q-latch, and in the second step, the data storage node of the S-latch is initialized in the RST transistor. It is turned on with the SRST signal to set the data to "0" state, and in the third step, the TRAN signal is applied to the P-latch and the Q-latch simultaneously or sequentially to change the respective data of the P-latch and the Q-latch. Move the data stored in the storage node to the top node

An AND operation can be performed by performing an operation and, in the fourth step, turning on the SET transistor with an SSET signal to store the data in the data storage node of the S-latch as the result of the operation.

의 1차 연산을 하고, 상기 1차 연산의 결과는 상기 SET 트랜지스터에 SSET 신호로 턴온시켜 상기 S-래치의 데이터 저장 노드의 데이터에 저장한 다음, 상기 초기화 트랜지스터에 PRECHSO 신호로 상기 상단 노드를 데이터 "1" 상태로 다시 초기화하고, TRANP 신호를 상기 P-래치에, TRANnQ 신호를 상기 Q-래치에 각각 동시 또는 순차적으로 인가하여 상기 상단 노드에서

의 2차 연산을 하고, 상기 P-래치의 RST 트랜지스터에 PRST 신호 및 상기 PBRST 트랜지스터에 PBRST 신호를 각각 동시 인가하여 상기 P-래치의 데이터 저장 노드를 데이터 "0" 상태로 초기화하고 상기 P-래치의 SET 트랜지스터에 PSET 신호를 인가하여 상기 P-래치의 데이터 저장 노드에 상기 2차 연산의 결과를 저장하고, 상기 초기화 트랜지스터에 PRECHSO 신호로 상기 상단 노드를 데이터 "1" 상태로 다시 초기화하고, TRANnS 신호를 상기 S-래치에, TRANnP 신호를 상기 P-래치에 각각 동시 또는 순차적으로 인가하여 상기 상단 노드에서

의 3차 연산을 하고, 상기 S-래치의 SET 트랜지스터에 SSET 신호 및 상기 PBRST 트랜지스터에 PBRST 신호를 각각 동시 인가하여 상기 S-래치의 데이터 저장 노드를 데이터 "1" 상태로 초기화한 다음, 상기 S-래치의 RST 트랜지스터에 SRST 신호를 인가하여 상기 S-래치의 데이터 저장 노드의 데이터는 상기 3차 연산의 반전 데이터(

)가 저장되는 것으로 XOR 연산을 수행할 수 있다.In the first step, data “a” is stored in the P-latch and data “b” is stored in the Q-latch, and in the second step, the data storage node of the S-latch is initialized in the RST transistor. Turn on with the SRST signal to set the data to "0" state, and in the third step, apply the TRANnP signal to the P-latch and the TRANQ signal to the Q-latch simultaneously or sequentially at the top node.

The first operation is performed, and the result of the first operation is turned on by the SSET signal in the SET transistor and stored in the data of the data storage node of the S-latch, and then the upper node is converted to data by a PRECHSO signal in the initialization transistor. Re-initialize to the "1" state, apply the TRANP signal to the P-latch and the TRANnQ signal to the Q-latch simultaneously or sequentially at the top node.

Perform the secondary operation of and simultaneously apply the PRST signal to the RST transistor of the P-latch and the PBRST signal to the PBRST transistor, respectively, to initialize the data storage node of the P-latch to the data "0" state and the P-latch The PSET signal is applied to the SET transistor to store the result of the secondary operation in the data storage node of the P-latch, and the upper node is reinitialized to the data "1" state with a PRECHSO signal to the initialization transistor, and TRANnS A signal is applied simultaneously or sequentially to the S-latch and a TRANnP signal to the P-latch, respectively, at the top node.

Perform the third operation of and simultaneously apply the SSET signal to the SET transistor of the S-latch and the PBRST signal to the PBRST transistor to initialize the data storage node of the S-latch to the data "1" state, and then initialize the data storage node of the S-latch to the data "1" state. -By applying the SRST signal to the RST transistor of the latch, the data of the data storage node of the S-latch is the inverted data of the third operation (

) is stored, so the XOR operation can be performed.

One of the plurality of latch circuits in the page buffer block serves as an operation result storage latch, and the remaining latch stores data stored inside the memory cell array or data received from the outside through the input/output device. Level 1; A second step of initializing the top node to a data "1" state and initializing the data storage node of the operation result storage latch to a "0" state or a "1" state; A third step of applying the TRAN signal or the TRANn signal to one or more of the remaining latches simultaneously or sequentially to transfer the data stored in each latch to the upper node to perform data movement or logic operation; And in the third step, if the data of the upper node is “0” as a result of the data movement or the logic operation, the data of the data storage node of the storage latch is maintained in an initialized state, and the data of the upper node is “0”. If it is 1", the SET transistor is turned on with the SSET signal to store the data in the data storage node of the storage latch as "1", or the RST transistor is turned on with the SRST signal to invert the data in the data storage node of the S-latch. A fourth step of storing data as “0” may be further included.

The present invention has the effect of allowing logic operations to be performed by using an existing page buffer circuit as is or slightly modifying it, without providing a separate circuit such as an operation circuit in the memory device.

Figure 1 is a schematic diagram showing a logic operation method in an existing von Neumann-based computing system.
Figure 2 is a schematic diagram showing a logic operation method in a computing system having a memory unit according to an embodiment of the present invention.
Figure 3 is a block diagram showing a memory unit equipped to perform logic operations with a page buffer according to an embodiment of the present invention.
FIG. 4 is a block diagram showing the configuration and connection relationship of the memory device of FIG. 3.
FIG. 5 is a block diagram showing the configuration of the control logic of FIG. 3 and the input and output relationship of control signals.
FIG. 6 is a circuit diagram showing an example of a page buffer circuit constituting the page buffer block of FIG. 4.
FIG. 7 is a page buffer operation sequence table showing an example of a Boolean logic operation using the page buffer circuit of FIG. 6.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

Referring to Figures 2 and 3, the memory unit 100 according to an embodiment of the present invention is basically composed of a memory device 110 and a memory controller 120, as usual.

Here, the memory device 110 includes a memory cell array 112, a page buffer block 114 connected to bit lines BLs of the memory cell array, and word lines of the memory cell array, as shown in FIG. 4. (WLs) connected to the May include control logic 118. As shown in FIG. 6, the page buffer block 114 connects a plurality of latch circuits 310, 320, and 330 in parallel to store internal operands stored in the memory cell array 112 or the input/output device 119. ) may be provided to perform logic operations with external operands input. The control logic 118 may further include logic in page buffer (LIP) control logic 117 for the logic operation, as shown in FIG. 4 . As shown in FIG. 3, the memory controller 120 may further include a LIP controller 122 for performing the logic operation through the LIP control logic 117 in addition to the existing memory controller 124.

As shown in FIG. 1, the memory unit 100 of the existing computing system 10' that is currently commercialized also includes a page buffer block 114 that is connected to the bit line of the memory cell array 112 and reads stored data. It is done. However, since the existing computing structure cannot perform calculations within the memory unit 100, input data is transferred to the processing unit 200 to perform calculations, and then transferred back to the memory unit 100 to produce calculation results. Process it.

However, the computing system 10 equipped with the memory unit 100 according to the above-described embodiment of the present invention can perform operations within the page buffer block 114 of the memory unit 100, as shown in FIG. 2. The processing unit 200 transmits only the command for the operation to the memory unit 100, performs the operation in the page buffer of the page buffer block 114, and then reads the operation result or stores it in the memory cell array 112. I do it.

The inventors of the present invention found that in the case of NAND flash, a plurality of data latches can be included in the page buffer to implement multi-level cells. In the present invention, such page buffer is used as is or slightly modified and stored in the memory cell array read through the page buffer. A method was found to store the internal operands or external operands input from the outside through the input/output device 119 in the data latch and then perform a logic operation within the page buffer.

The memory unit 100 that performs logic operations in one embodiment of the present invention may be configured as shown in FIG. 3. Here, the memory device 110 is one of non-volatile memory devices such as NAND flash, 3D vertical NAND flash, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectirc RAM). It can be. However, the memory device 110 of the present invention is equipped to perform basic memory operations by receiving signals from an existing memory controller (124) and LIP operations by receiving signals from the LIP controller (122). For example, the memory controller 120 receives a command CMD_LIP signal for performing LIP operations and basic memory operations, DATA_EX, which is the value of an external operand or external data, and an ADD_IN signal, which is a memory space address to store the value of an internal operand or data. It may be equipped to perform LIP operations and basic memory operations. Additionally, DATA_R, which is the result of performing LIP in the memory device 110 or data stored in the memory cell array 112, may be transmitted to the memory controller 120 and output to the outside.

The memory device 110 shown in FIG. 3 is configured as in FIG. 4 and may include a plurality of latch circuits in the page buffer block 114 to perform basic memory operations and LIP operations. The control logic 118 receives addresses and control commands such as external data (DATA_EX), LIP command (CMD_LIP), and memory space address (ADD_IN) through the input/output device (I/O) 119 and outputs the X decoder (X-Dec, 116) and the page buffer block 114 are controlled to perform memory basic operations and LIP operations. In particular, the control logic 118 includes LIP control logic for logic operation with the LIP operation, as shown in FIGS. 4 and 5. 117 is further provided, through which a page buffer sequence signal (PB_SEQ) for controlling a plurality of latch circuits is generated and sent to the page buffer block 114. At this time, an operation of reading internal data stored in the memory cell array 112 may be additionally performed, if necessary. FIG. 5 is a block diagram showing the configuration of the control logic 118 of FIG. 4 and the input and output relationship of control signals.

Referring to FIGS. 3 to 5 , in the present invention, a separate operation circuit is not required to perform logic operations within the memory unit 100. However, the memory controller 120 of FIG. 3 includes a LIP controller 122 in addition to the existing memory controller 124, and logic operations are performed through the LIP control logic 117. That is, the LIP control logic 117 generates a page buffer sequence signal (PB_SEQ) appropriate for the type of operation for performing the LIP operation through the LIP command (CMD_LIP) received through the input/output device 119 to generate the page buffer block 114. ) will be transmitted.

FIG. 6 is a circuit diagram showing an example of a page buffer circuit constituting the page buffer block 114 of FIG. 4. With reference to this, the page buffer circuit constituting the page buffer block 114 of the present invention may be implemented with the same configuration as the existing circuit, but is preferably implemented with a plurality of latch circuits to be described later. Examples related to this will be described.

In one embodiment of the present invention, the plurality of latch circuits constituting the page buffer block 114 are S-latches 310 having the same circuit configuration between the upper node (sensing node, SO) and the lower node 305. , circuits including the P-latch 320 and the Q-latch 330 may be connected in parallel. The names of the latches are given for convenience of explanation. Also, with reference to FIGS. 6 and 7, a preferred embodiment will be described in which the page buffer circuit is configured with three latches for storing two input data (operands: a, b) and one output data. However, 4 In cases where more than two latches, of course, where input data is stored, can be overwritten with output values, logic operations can be performed with only two latches.

As shown in FIG. 6, at the top node SO, one or more of the bit lines BLs and a supply voltage terminal V _DD are connected to bit line selection transistors 342 and 344 and an initialization transistor 350, respectively. Can be connected in parallel. The lower node 305 includes a ground transistor (M1, 307) through which the voltage of the upper node (SO) is applied to the gate and a PBRST transistor 309 through which the PBRST signal of the LIP control logic 117 is applied to the gate. It can be connected in parallel to the ground terminal.

The same circuit configuration is inverted with the data transfer transistors 318, 328, and 338, which are connected in parallel to the top node (SO) and are opened and closed by the TRAN and TRANn signals of the LIP control logic 117, respectively, as shown in FIG. data movement transistors 316, 326, 336; an inverted data driving transistor (308) connected between the data moving transistors (318, 328, 338) and the ground terminal and opened and closed by the voltage of the inverted data storage nodes (313, 323, 333); A data driving transistor 306 connected between the inverting data transfer transistors 316, 326, and 336 and the ground terminal and opened and closed by the voltage of the data storage nodes 311, 321, and 331; First and second inverters (302, 304) whose input and output terminals are interconnected and connected between the data storage nodes (311, 321, 331) and the inverted data storage nodes (313, 323, 333); RST transistors (312, 322, 332) opened and closed by the RST signal of the LIP control logic 117 between the data storage nodes (311, 321, 331) and the lower node (305); And it may include SET transistors (314, 324, 334) between the inverted data storage nodes (313, 323, 333) and the lower node (305), which are opened and closed by the SET signal of the LIP control logic (117).

Here, the control signals sent from the LIP control logic 117 to the page buffer block 114 are divided into pulse waveforms according to the S-latch 310, P-latch 320, and Q-latch 330, As shown in Figure 6, the TRAN signal is applied to TRANS, TRANP, and TRANQ, the TRANn signal is applied to TRANnS, TRANnP, and TRANnQ, the RST signal is applied to SRST, PRST, and QRST, and the SET signal is applied to SSET, PSET, and QSET. approved.

Next, referring to FIGS. 6 and 7, a logic operation method using the above-described memory unit will be described.

First, in Figure 6, the initialization transistor 350 is turned on with a PRECHSO signal that precharges the bit line (BL) and the upper node (sensing node, SO), and the cell data of the memory cell array is detected and amplified to transmit the upper node. The BLSHF signal transmitted to (SO) and the BLSLT signal to protect the low-voltage transistor of the page buffer from the high voltage applied to the bit line during the erase operation are shown as being applied to the gates of the bit line selection transistors 342 and 344, respectively, and are shown as being applied to the gates of the bit line selection transistors 342 and 344, respectively. Circuits for inputting and outputting data through data lines are omitted. In addition, as described above, three latches named S, P, and Q are included. When a multi-level program is operated, data indicating the program progress is stored in one of these latches (e.g., S-latch). It may be updated as the program/verify loop progresses. State information to be programmed is stored in the remaining latches (e.g., P-latch and Q-latch), and is referred to when verifying each state. Each latch has control signals (xSET, xRST) that set the data storage node (x=S, P, Q; 311, 321, 331) to 'H' (data "1") or 'L' (data "0"). ). The data of the data storage node can be selectively set by referring to the state (V _DD or 0V) of the top node (SO), or it can be initialized all at once with the PBRST signal at 'H'. Additionally, it includes control signals (TRANx, TRANnx) that move the data from each data storage node to the top node (SO). By utilizing means (control signals) for setting and data movement of these data storage nodes, the operands (e.g., a and b) stored in the data storage nodes 321 and 331 of the P-latch and Q-latch are It is possible to perform a logical operation and store the operation result in the data storage node 311 of the S-latch.

Referring to FIG. 7, if pulse signals are applied in order to perform the desired logic, the operation results of the data loaded into the P-latch and Q-latch can be stored in the S-latch.

The input and output terminals of three latches (310, 320, 330) and two inverters (302, 304) are interlocked and connected to maintain the stored value only when power is supplied to the computing system 10. In order to store the operation result in a non-volatile memory device as needed, after performing the LIP operation, when the LIP operation result is stored in the S-latch, the data of the S-latch can be transferred to the bit line and stored in the memory cell array 112. You can.

The logic operation method using the above-described memory unit is specifically, the S-latch 310, one of the plurality of latch circuits in the page buffer block 114, is used as an operation result storage latch, and the remaining P-latch 320 is used as an operation result storage latch. and a first step of storing data stored inside the memory cell array 112 or data received from the outside through the input/output device 119 in the Q-latch 330; And a second step of initializing the top node (SO) to the data "1" state and initializing the data storage node 311 of the S-latch 310 to the data "0" or data "1" state. This can be implemented.

The first step is a data load step, in which data stored inside the memory cell array 112 or data received from the outside through the input/output device 119 is loaded into the P-latch 320 in the page buffer block 114. Or load it into the Q-latch (330). For explanation, in the page buffer operation sequence table of FIG. 7, data “a” is loaded into the P-latch 320, and data “b” is loaded into the Q-latch 330.

The second step is an initialization step, and in order to perform LIP, the top node (SO) is precharged with high data “1” through the PRECHSO pulse signal. Afterwards, the data storage node (311, S node) of the S-latch (310) is initialized to the “0” state or “1” state according to each operation. In the process of storing the LIP operation result in the S-latch 310 with reference to the top node (SO), if the top node (SO) is in a low state and data is “0”, it is transmitted to the gate of the ground transistor (M ₁ , 307). This is to prepare for a case where 0 V is applied and the operation result is not stored in the S-latch 310. This also applies when intermediate results are stored and used in a P-latch or Q-latch for XOR operations, etc., which will be described later.

In the second step, the initialization of the S-latch 310 is performed by turning on the initialization transistor 350 with the PRECHSO signal and applying the supply voltage (V _DD ) to the upper node (SO) to generate data “1” in a high state. ”, and in the initialization state of the upper node (SO), the RST transistor 312 of the S-latch 310 is turned on with an SRST signal to enter the data “0” state or the SET transistor of the S-latch 310 ( 314) can be turned on with the SSET signal to set the data to "1" state.

In the above embodiment, following the second step, the top node (SO) is initialized to the data "1" state and the TRAN signal or TRANn signal is connected to one or more of the P-latch 320 and the Q-latch 330. A third step may be further included in which the data stored in the P-latch 320 and the Q-latch 330 are applied simultaneously or sequentially to the top node (SO) to perform data movement or logic operation.

"가 상단 노드(SO)에 전달된다. The third step is a step of data movement and/or logic operation, where the top node (SO) is initialized and the data of the P-latch 320 or Q-latch 330 is transferred to the top node through the TRAN signal or TRANn signal. Forward it to (SO). For example, when a TRANP pulse signal is applied, the data stored in the data storage node 321 of the P-latch is “ ” is transmitted to the top node (SO), and when the TRANnP pulse signal is applied, the inverted data of the data stored in the data storage node 321 of the P-latch is “ ” is delivered. In addition, when the TRANP and TRANQ pulse signals are applied simultaneously or sequentially, the data stored in the data storage node 321 of the P-latch is ” and data stored in the data storage node 331 of the Q-latch “ ” Only when both are “1”, the top node (SO) maintains the initial state “1”, so the logical product of the two data “

" is delivered to the top node (SO).

After the third step, when the data of the top node (SO) is “0” as a result of the data movement and/or the logic operation in the third step, the data storage node 311 of the S-latch 310 The data is maintained in the initialized state, and when the data of the top node (SO) is "1", the SET transistor 314 of the S-latch 310 is turned on with an SSET signal to store the data storage node of the S-latch ( The data in 311) is stored as “1” or the RST transistor 312 of the S-latch 310 is turned on with an SRST signal, and the data in the data storage node 311 of the S-latch is stored as inverted data “0”. A fourth step may be further included.

Hereinafter, with reference to FIGS. 6 and 7, a method of performing an OR operation, an AND operation, and an XOR operation will be described in a specific embodiment of the present invention.

First, the OR operation stores data “a” in the P-latch 320 and data “b” in the Q-latch 330 in the first step, and stores data “b” in the S-latch in the second step. The data storage node 311 of 310 is initialized by turning on the SET transistor 314 of the S-latch 310 with the SSET signal to set the data to a "1" state.

연산을 수행하고, 상기 제 4 단계에서 S-래치(310)의 RST 트랜지스터(312)에 SRST 신호로 턴온시켜 상기 S-래치(310)의 데이터 저장 노드(311)의 데이터는 상기 연산의 반전 데이터(

)가 저장되는 것으로 수행할 수 있다.Then, in the third step, the TRANn signal, that is, the TRANnP and TRANnQ signals, are applied simultaneously or sequentially to the P-latch 320 and the Q-latch 330, respectively, to Move the inverted data of the data stored in each data storage node (321) (331) of the Q-latch (330) to the upper node (SO)

The operation is performed, and in the fourth step, the RST transistor 312 of the S-latch 310 is turned on with an SRST signal, so that the data of the data storage node 311 of the S-latch 310 is the inverted data of the operation. (

) can be performed by storing it.

The AND operation stores data “a” in the P-latch 320 and data “b” in the Q-latch 330 in the first step, and stores data “b” in the S-latch 310 in the second step. )'s data storage node 311 is initialized by turning on the RST transistor 312 of the S-latch 310 with an SRST signal to set the data to "0" state.

연산을 수행하고, 상기 제 4 단계에서 S-래치(310)의 SET 트랜지스터(314)에 SSET 신호로 턴온시켜 상기 S-래치(310)의 데이터 저장 노드(311)의 데이터는 상기 연산의 결과 데이터(

)가 저장되는 것으로 수행할 수 있다.Then, in the third step, the TRAN signal, that is, the TRANP and TRANQ signals, are applied simultaneously or sequentially to the P-latch 320 and the Q-latch 330, respectively, to The data stored in each data storage node (321) (331) of the Q-latch (330) is moved to the upper node (SO).

The operation is performed, and in the fourth step, the SET transistor 314 of the S-latch 310 is turned on with an SSET signal, so that the data of the data storage node 311 of the S-latch 310 is the result data of the operation. (

) can be performed by storing it.

The XOR operation stores data “a” in the P-latch 320 and data “b” in the Q-latch 330 in the first step, and stores data “b” in the S-latch 310 in the second step. )'s data storage node 311 is initialized by turning on the RST transistor 312 of the S-latch 310 with an SRST signal to set the data to "0" state.

의 1차 연산을 하고, 상기 1차 연산의 결과는 S-래치(310)의 SET 트랜지스터(314)에 SSET 신호로 턴온시켜 상기 S-래치(310)의 데이터 저장 노드(311)의 데이터에 저장한 다음, 상기 초기화 트랜지스터(350)에 PRECHSO 신호로 상기 상단 노드(SO)를 데이터 "1" 상태로 다시 초기화하고, TRANP 신호를 상기 P-래치(320)에, TRANnQ 신호를 상기 Q-래치(330)에 각각 동시 또는 순차적으로 인가하여 상기 상단 노드(SO)에서

의 2차 연산을 하고, 상기 P-래치(320)의 RST 트랜지스터(322)에 PRST 신호 및 상기 PBRST 트랜지스터(309)에 PBRST 신호를 각각 동시 인가하여 상기 P-래치(320)의 데이터 저장 노드(321)를 데이터 "0" 상태로 초기화하고 상기 P-래치(320)의 SET 트랜지스터(324)에 PSET 신호를 인가하여 상기 P-래치(320)의 데이터 저장 노드(321)에 상기 2차 연산의 결과를 저장하고, 상기 초기화 트랜지스터(350)에 PRECHSO 신호로 상기 상단 노드(SO)를 데이터 "1" 상태로 다시 초기화하고, TRANnS 신호를 상기 S-래치(310)에, TRANnP 신호를 상기 P-래치(320)에 각각 동시 또는 순차적으로 인가하여 상기 상단 노드(SO)에서

의 3차 연산을 하고, 상기 S-래치(310)의 SET 트랜지스터(314)에 SSET 신호 및 상기 PBRST 트랜지스터(309)에 PBRST 신호를 각각 동시 인가하여 상기 S-래치(310)의 데이터 저장 노드(311)를 데이터 "1" 상태로 초기화한 다음, 상기 S-래치(310)의 RST 트랜지스터(312)에 SRST 신호를 인가하여 상기 S-래치(310)의 데이터 저장 노드(311)의 데이터는 상기 3차 연산의 반전 데이터(

)가 저장되는 것으로 수행할 수 있다.Then, in the third step, the TRANnP signal is applied to the P-latch 320 and the TRANQ signal is applied to the Q-latch 330 simultaneously or sequentially at the top node.

The first operation is performed, and the result of the first operation is turned on with the SSET signal in the SET transistor 314 of the S-latch 310 and stored in the data of the data storage node 311 of the S-latch 310. Then, the top node (SO) is re-initialized to the data "1" state with the PRECHSO signal to the initialization transistor 350, the TRANP signal is applied to the P-latch 320, and the TRANnQ signal is applied to the Q-latch ( 330) simultaneously or sequentially from the top node (SO).

Perform the secondary operation of and simultaneously apply the PRST signal to the RST transistor 322 of the P-latch 320 and the PBRST signal to the PBRST transistor 309, respectively, to obtain the data storage node of the P-latch 320 ( 321) is initialized to the data "0" state and a PSET signal is applied to the SET transistor 324 of the P-latch 320 to perform the secondary operation in the data storage node 321 of the P-latch 320. The result is stored, and the top node (SO) is re-initialized to the data "1" state with the PRECHSO signal to the initialization transistor 350, the TRANnS signal to the S-latch 310, and the TRANnP signal to the P- Simultaneously or sequentially apply to each latch 320 from the upper node (SO)

Perform the third operation, and simultaneously apply the SSET signal to the SET transistor 314 of the S-latch 310 and the PBRST signal to the PBRST transistor 309, respectively, to generate the data storage node of the S-latch 310 ( 311) is initialized to the data "1" state, and then an SRST signal is applied to the RST transistor 312 of the S-latch 310, so that the data of the data storage node 311 of the S-latch 310 is Inverted data of 3rd order operation (

) can be performed by storing it.

The remaining operations shown in FIG. 7 can also be performed by applying control pulse signals in the order presented with reference to the specific embodiments above.

Referring to the above-described embodiments, in a more general embodiment, one of the plurality of latch circuits in the page buffer block 114 is used as an operation result storage latch, and the remaining latches contain data stored inside the memory cell array or A first step of storing data received from outside through the input/output device; A second step of initializing the top node to a data "1" state and initializing the data storage node of the operation result storage latch to a "0" state or a "1" state; A third step of applying the TRAN signal or the TRANn signal to one or more of the remaining latches simultaneously or sequentially to transfer the data stored in each latch to the upper node to perform data movement or logic operation; And in the third step, if the data of the upper node is “0” as a result of the data movement or the logic operation, the data of the data storage node of the storage latch is maintained in an initialized state, and the data of the upper node is “0”. If it is 1", the SET transistor is turned on with the SSET signal to store the data in the data storage node of the storage latch as "1", or the RST transistor is turned on with the SRST signal to invert the data in the data storage node of the S-latch. It may be performed by further including a fourth step of storing data as “0”.

After the logic operation, the LIP operation result stored in the S-latch 310 as necessary ( Alternatively, DATA_R) can be transmitted to the bit line (BL) and directly stored in the memory element of the memory cell array 112, or transmitted to the memory controller 120 and output externally.

In a more complex expression, combinations of Boolean logic operations can also be calculated by moving the Boolean logic operation calculated in the page buffer to the memory cell array 112 and storing the intermediate operation result. In the case of a full adder, it can be expressed as follows.

If there are more than 4 latches, this formula can obtain a result using only the latches. However, if there are 3 latches, the intermediate calculation result is stored in a memory cell, other terms are calculated, and the final result is obtained by calculating the other terms again. I can pay it. In this way, more combinations of terms can be implemented by moving data between the memory cell array 112 and the page buffer block 114.

In the existing von Neumann architecture, data requiring calculation is moved from the memory unit to the CPU, the calculation is performed in the CMOS-based ALU, and the resulting data is brought back to the memory unit to store the value.

However, if the computing method using logic in page buffer proposed in the present invention is used, only the signal sequence generation circuit of the page buffer circuit is added to the control logic of the memory device, so that data is stored within the memory unit without moving through the bus 240. All logic operations are possible in the page buffer. Additionally, the calculation results can be transferred to the bit line and the results can be stored in the memory array. In other words, by eliminating data movement between the memory unit and the CPU, the performance of the overall system can be improved and energy consumption can be dramatically reduced.

100: memory unit 110: memory device
112: memory cell array 114: page buffer block
116: X decoder 118: Control logic
119: input/output device 120: memory controller
122: LIP controller 124: Conventional memory controller
200: processing unit

Claims (10)

delete delete In a memory unit consisting of a memory device and a memory controller,
The memory device includes a memory cell array, a page buffer block connected to bit lines of the memory cell array, an X decoder connected to word lines of the memory cell array, an input/output device connected to the page buffer block, and an address and Includes control logic to receive control commands and control the X decoder and the page buffer block,
The page buffer block is equipped to connect a plurality of latch circuits in parallel to perform logic operations with internal operands stored in the memory cell array or external operands input to the input/output device,
The control logic is further provided with LIP control logic for the logic operation,
The memory controller is further provided with a LIP controller for performing the logic operation through the LIP control logic,
The plurality of latch circuits include circuits including an S-latch, a P-latch, and a Q-latch having the same circuit configuration between an upper node and a lower node, connected in parallel,
At the upper node, one or more of the bit lines and a supply voltage terminal are connected in parallel with bit line selection transistors and an initialization transistor, respectively,
At the lower node, a ground transistor to which the voltage of the upper node is applied to the gate and a PBRST transistor to which the PBRST signal of the LIP control logic is applied to the gate are each connected in parallel to the ground terminal,
The same circuit configuration includes a data transfer transistor and an inverting data transfer transistor connected in parallel to the upper node and opened and closed by the TRAN and TRANn signals of the LIP control logic, respectively;
an inverted data driving transistor connected between the data moving transistor and the ground terminal and opened and closed by the voltage of the inverted data storage node;
a data driving transistor connected between the inverting data transfer transistor and the ground terminal and opened and closed by the voltage of the data storage node;
First and second inverters whose input and output terminals are interconnected and connected between the data storage node and the inverted data storage node;
an RST transistor opened and closed by the RST signal of the LIP control logic between the data storage node and the lower node; and
A memory unit comprising a SET transistor opened and closed by a SET signal of the LIP control logic between the inverted data storage node and the bottom node.
In the logic operation method using the memory unit of claim 3,
The S-latch, which is one of a plurality of latch circuits in the page buffer block, is used as an operation result storage latch, and the remaining P-latches and the Q-latches contain data stored inside the memory cell array or the input/output device. A first step of storing data received from outside through; and
A logic using a memory unit comprising a second step of initializing the upper node to a data "1" state and initializing the data storage node of the S-latch to a data "0" or data "1" state. How to calculate.
According to claim 4,
The TRAN signal or the TRANn signal is applied simultaneously or sequentially to one or more of the P-latch and the Q-latch to transfer the data stored in the P-latch and the Q-latch to the upper node to perform data movement or logic. A logic calculation method using a memory unit, further comprising a third step of performing calculation.
According to claim 5,
In the second step, the initialization of the upper node is performed by turning on the initialization transistor with a PRECHSO signal to apply a supply voltage (V _DD ) to the upper node to set it to a data "1" state, and the S-latch Initialization of the data storage node is performed by turning on the RST transistor with an SRST signal to a data "0" state or by turning on the SET transistor with an SSET signal to a data "1" state in the initialization state of the upper node,
After the third step, if the data of the upper node is “0” as a result of the data movement or the logic operation in the third step, the data of the data storage node of the S-latch is maintained in an initialized state, and the upper When the data of the node is "1", the SET transistor is turned on with an SSET signal to store the data of the S-latch, and the data of the node is stored as "1", or the RST transistor is turned on by an SRST signal to store the data of the S-latch. A logic operation method using a memory unit, further comprising a fourth step of storing the data of the storage node as inverted data “0”.
According to claim 6,
In the first step, data “a” is stored in the P-latch and data “b” is stored in the Q-latch, respectively,
In the second step, the data storage node of the S-latch is initialized by turning on the SET transistor with an SSET signal to set the data to "1" state,
In the third step, the TRANn signal is applied simultaneously or sequentially to the P-latch and the Q-latch to move the inverted data stored in each data storage node of the P-latch and the Q-latch to the upper node.

perform calculations,
In the fourth step, the RST transistor is turned on with an SRST signal so that the data of the data storage node of the S-latch is the inverted data of the operation (

) A logic operation method using a memory unit, characterized in that OR operation is performed by storing ).
According to claim 6,
In the first step, data “a” is stored in the P-latch and data “b” is stored in the Q-latch, respectively,
In the second step, the data storage node of the S-latch is initialized by turning on the RST transistor with an SRST signal to set the data to “0” state,
In the third step, the TRAN signal is applied simultaneously or sequentially to the P-latch and the Q-latch to move the data stored in each data storage node of the P-latch and the Q-latch to the upper node.

perform calculations,
A logic operation method using a memory unit, characterized in that in the fourth step, the SET transistor is turned on with an SSET signal and an AND operation is performed on the data of the data storage node of the S-latch to store the result data of the operation. .
According to claim 6,
In the first step, data “a” is stored in the P-latch and data “b” is stored in the Q-latch, respectively,
In the second step, the data storage node of the S-latch is initialized by turning on the RST transistor with an SRST signal to set the data to “0” state,
In the third step, the TRANnP signal is applied to the P-latch and the TRANQ signal is applied to the Q-latch simultaneously or sequentially at the top node.

The first operation is performed, and the result of the first operation is turned on by the SSET signal in the SET transistor and stored in the data of the data storage node of the S-latch, and then the upper node is converted to data by a PRECHSO signal in the initialization transistor. Re-initialize to the "1" state, apply the TRANP signal to the P-latch and the TRANnQ signal to the Q-latch simultaneously or sequentially at the top node.

Perform the secondary operation of and simultaneously apply the PRST signal to the RST transistor of the P-latch and the PBRST signal to the PBRST transistor, respectively, to initialize the data storage node of the P-latch to the data "0" state and the P-latch The PSET signal is applied to the SET transistor to store the result of the secondary operation in the data storage node of the P-latch, and the upper node is reinitialized to the data "1" state with a PRECHSO signal to the initialization transistor, and TRANnS A signal is applied simultaneously or sequentially to the S-latch and a TRANnP signal to the P-latch, respectively, at the top node.

Perform the third operation of and simultaneously apply the SSET signal to the SET transistor of the S-latch and the PBRST signal to the PBRST transistor to initialize the data storage node of the S-latch to the data "1" state, and then initialize the data storage node of the S-latch to the data "1" state. -By applying the SRST signal to the RST transistor of the latch, the data of the data storage node of the S-latch is the inverted data of the third operation (

) A logic operation method using a memory unit, characterized in that XOR operation is performed by storing.
In the logic operation method using the memory unit of claim 3,
One of the plurality of latch circuits in the page buffer block serves as an operation result storage latch, and the remaining latch stores data stored inside the memory cell array or data received from the outside through the input/output device. Level 1;
A second step of initializing the top node to a data "1" state and initializing the data storage node of the operation result storage latch to a "0" state or a "1"state;
A third step of applying the TRAN signal or the TRANn signal to one or more of the remaining latches simultaneously or sequentially to transfer the data stored in each latch to the upper node to perform data movement or logic operation; and
In the third step, when the data of the upper node is “0” as a result of the data movement or the logic operation, the data of the data storage node of the storage latch is maintained in an initialized state, and the data of the upper node is “1” In this case, the SET transistor is turned on with the SSET signal to store the data in the data storage node of the storage latch as "1", or the RST transistor is turned on with the SRST signal so that the data in the data storage node of the S-latch is inverted data. A logic operation method using a memory unit, further comprising a fourth step of storing as “0”.