KR102697844B1 - Epitaxial wafer and manufacturing method thereof - Google Patents

Abstract

An epitaxial wafer according to one embodiment of the present invention comprises: a substrate; and a laminated structure disposed on the substrate, the laminated structure including a first region constituting a semiconductor element and a second region disposed at a periphery of the first region; wherein the second region comprises silicon (Si) layers and silicon germanium (SiGe) layers alternately laminated, and the silicon germanium layer may include doped boron (B).

Description

{Epitaxial wafer and manufacturing method thereof}

The present invention relates to an epitaxial wafer and a method for manufacturing an epitaxial wafer, and more specifically, to an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of preventing occurrence of interlayer defects by reducing a difference in lattice constant.

Recently, there has been an increasing demand for increased integration of memory and non-memory devices. Accordingly, scale down for increased integration has been continuously studied, and 3D devices implemented in various ways have been proposed as a method for increasing the integration of devices.

Following this trend, research is also being conducted to produce 3D-DRAM elements in DRAM. 3D-DRAM has a structure in which DRAM elements are produced in a three-dimensional space and stacked in the Z-axis direction. However, in a three-dimensionally stacked structure, since the components of each layer are different, stress occurs due to the difference in lattice parameters between layers. This can cause dislocation between the constituent atoms of the crystal lattice, and there is a problem in that defects such as voids and hillocks can occur.

One of the several objects of the present invention is to provide an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of reducing the difference in lattice constants between a Si layer and a Si-Ge layer.

One of the several objects of the present invention is to provide an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of relieving stress between a Si layer and a Si-Ge layer.

One of the several objects of the present invention is to provide an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of preventing occurrence of defects.

One of the several objects of the present invention is to provide an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of improving the integration density.

In one embodiment of the present invention, an epitaxial wafer according to the present invention comprises: a substrate; and a laminated structure disposed on the substrate, the laminated structure including a first region constituting a semiconductor element and a second region disposed at a periphery of the first region; wherein the second region comprises silicon (Si) layers and silicon germanium (SiGe) layers alternately laminated, and the silicon germanium layer may include doped boron (B).

In one embodiment of the present invention, a method for manufacturing an epitaxial wafer according to the present invention includes a step of forming a laminated structure by alternately growing a silicon layer and a silicon germanium layer on a substrate; wherein the silicon germanium layer may include doped boron (B).

One of the many effects of the present invention is that the difference in lattice constants between the Si layer and the Si-Ge layer can be reduced.

One of the many effects of the present invention is that the stress between the Si layer and the Si-Ge layer can be relieved.

One of the many effects of the present invention is that it can provide an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of preventing the occurrence of defects.

One of the many effects of the present invention is that it can provide an epitaxial wafer and a method for manufacturing an epitaxial wafer capable of improving integration.

FIG. 1 is a perspective view schematically showing an epitaxial wafer according to one embodiment of the present invention.
Figure 2 is a plan view of Figure 1.
Figure 3 is a cross-sectional view showing area II' of Figure 1.
Figure 4 is a cross-sectional view showing area II-II" of Figure 1.
Figure 5 is a graph showing the lattice constants of (a) Si _1-y B _y , (b) Si _1-y Al _y , and (c) Si _1-y Ga _y calculated using LDA and GGA-PBE.
Figure 6 is a graph showing the average bond length according to the doping concentration of Si _1-y B _y , Si _1-y Al _y , and Si _1-y Ga _y .
Figure 7 is a graph showing the lattice constant according to the change in the concentration of Ge and B in Si _1-xy Ge _x B _y .
Figure 8 is a schematic diagram explaining the mechanism by which a defect occurs in the prior art.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention can be modified in various ways and can have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention. In describing each drawing, similar reference numerals are used for similar components. In the attached drawings, the dimensions of structures are illustrated larger than actual dimensions in order to ensure clarity of the present invention.

The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprises" or "has" and the like are intended to specify the presence of a feature, number, step, operation, component or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined in this application.

The present invention relates to an epitaxial wafer. FIG. 1 is a perspective view schematically illustrating an epitaxial wafer according to the present invention, and FIG. 2 is a plan view of FIG. 1. Referring to FIG. 1 and FIG. 2, an epitaxial wafer (1) according to one embodiment of the present invention includes a substrate (10); and a laminated structure including a first region (100) disposed on the substrate (10) and constituting a semiconductor element, and a second region (200) disposed in a periphery of the first region (100), wherein the second region (200) may be arranged such that a silicon (Si) layer and a silicon germanium (SiGe) layer are alternately laminated.

At this time, the silicon germanium layer of the second region may include boron (B). The conventional epitaxial wafer had a structure in which a silicon germanium (SiGe) layer and a silicon layer were sequentially laminated on a silicon substrate. Fig. 8 schematically shows that a defect occurs in a wafer having a conventional silicon layer and a silicon germanium layer. The silicon germanium (SiGe) layer and the silicon layer are formed by epitaxial growth and correspond to layers having different lattice constants. Specifically, the lattice constant of silicon is 5.43Å and the lattice constant of germanium is 5.66Å, and the silicon germanium (SiGe) layer has a lattice constant between the lattice constants depending on the composition ratio of silicon and germanium. However, when a silicon layer is grown on a silicon germanium (SiGe) layer due to the difference between the lattice constant of the silicon and the lattice constant of silicon, the silicon layer may be subject to strain due to the tensile force generated by the difference in the lattice constant, and misfit dislocations may occur. In particular, when the interlayer thickness is formed thinly to improve the integration density, the above-mentioned problem occurs more frequently, and there is a limitation that a stacked structure cannot be formed in an ultra-high layer.

The present invention has been made to solve such a problem, and the inventors of the present invention have found that when a silicon germanium (SiGe) layer is doped with boron (B), the difference in the lattice constants described above can be minimized. The epitaxial wafer according to the present invention can minimize the difference in lattice constants between the silicon layer and the silicon germanium (SiGe) layer by including a silicon germanium (SiGe) layer including boron (B), and can minimize interlayer defects even in an ultra-high-layer stacked structure.

In one example of the present invention, the silicon germanium (SiGe) layer of the second region of the epitaxial wafer according to the present invention may include a compound represented by the general formula Si _1-xy Ge _x B _y (0<x≤0.4, 0<y≤0.4). The compound represented by the general formula may be a compound in which boron (B) exists in a partially dissolved form in silicon germanium (SiGe). When the epitaxial wafer according to the present invention satisfies the above content range, the difference in lattice constants between the silicon layer of the second region and the silicon germanium (SiGe) layer can be reduced, thereby suppressing stress formation.

In one example, the average thickness of the silicon (Si) layer and/or the silicon germanium (SiGe) layer of the second region of the epitaxial wafer according to the present invention may be 100 nm or less. FIG. 4 is a cross-sectional view taken along line II-II' of FIG. 1, schematically illustrating a cross-section of the second region of the epitaxial wafer according to the present example. Referring to FIG. 4, the average thickness (t21) of the silicon layer (210) of the second region (200) of the epitaxial wafer (1) according to the present invention may be 100 nm or less, and the average thickness (t22) of the silicon germanium layer (220) of the second region (200) may be 100 nm or less. Alternatively, the average thickness (t21) of the silicon layer (210) and the average thickness (t22) of the silicon germanium layer (220) of the second region (200) may be 100 nm or less. As described above, the epitaxial wafer (1) according to the present invention can reduce the difference in lattice constant between the silicon layer (210) and the silicon germanium layer (220) by doping the silicon germanium layer (220) of the second region (200) with boron, thereby minimizing the stress between the silicon layer (210) and the silicon germanium layer (220). Accordingly, the silicon layer (210) and/or the silicon germanium layer (220) of the second region (200) can have an average thickness of 100 nm or less. The lower limit of the average thickness of the silicon layer and/or the silicon germanium layer is not particularly limited, but may be, for example, greater than 0 nm.

In one embodiment of the present invention, the number of stacked layers in the second region of the silicon epitaxial wafer according to the present invention may be 3 or more. The number of stacked layers in the second region being 3 or more may mean that the number of stacked silicon layers included in the second region is 3 or more, the number of stacked silicon germanium layers included in the second region is 3 or more, or the number of stacked silicon layers and silicon germanium layers in the second region are both 3 or more. The upper limit of the number of stacked layers in the second region is not particularly limited, but may be, for example, 1000 layers or less. The silicon epitaxial wafer according to the present embodiment may have the above-mentioned number of stacked layers and thus may implement high capacity.

The epitaxial wafer according to the present invention may include a first region constituting a semiconductor element. At this time, the first region may include silicon (Si) layers and insulating layers that are alternately laminated. FIG. 3 is a cross-sectional view schematically illustrating the first region (100) of the epitaxial wafer (1) according to the present invention. Referring to FIG. 3, the first region (100) of the epitaxial wafer (1) according to the present invention may include a structure in which silicon layers (110) and insulating layers (120) are alternately laminated. The insulating layer (120) may be formed after etching and removing a silicon germanium layer disposed between silicon layers, as described below.

In one example, the insulating layer of the first region of the epitaxial wafer according to the present invention may include a void space. The insulating layer may be used in a process of manufacturing a semiconductor device with the epitaxial wafer according to the present invention, and more specifically, the insulating layer may be formed in a process of forming a mask pattern having etching selectivity on the first region and performing the process of etching at least a portion of the first region multiple times, and may be a space remaining after etching and removing the silicon germanium layer of the first region.

In one example, the insulating layer of the first region of the epitaxial wafer according to the present invention may include a different composition from the silicon germanium layer of the second region. The insulating layer may include, for example, one or more selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The insulating layer may be formed in the above-described empty space and may be arranged to fill the empty space.

In one embodiment of the present invention, a first region of an epitaxial wafer according to the present invention may include a plurality of unit elements repeated in a direction perpendicular to a stacking direction of a stacked structure. At this time, the plurality of unit elements may be arranged to be spaced apart by scribe lines. Referring to FIG. 2, a first region (100) of an epitaxial wafer (1) according to the present embodiment may include a plurality of unit elements (111) partitioned by scribe lines (SL). The scribe lines (SL) are regions provided so that each unit element can be separated and cut into individual chips in a dicing process for the wafer.

The above scribe line (SL) may be formed in a grid shape. For example, the scribe line (SL) may include a horizontal line extending along a first direction (D1) and a vertical line extending along a second direction (D2) intersecting the first direction (D1). In Fig. 2, the length of the unit element in the first direction (D1) and the length of the unit element in the second direction (D2) are depicted as being the same, but the length of the unit element in the first direction and the length of the unit element in the second direction may be set differently as needed.

In one example of the present invention, a plurality of unit elements included in a first region of an epitaxial wafer according to the present invention may each include a cell region (CELL) including a memory cell array and a circuit region (PERI) controlling the memory cell array.

In the above example, the unit element included in the first region may include a plurality of word lines, a plurality of memory cell transistors connected to each of the word lines, and a plurality of bit lines connected to the memory cell transistors. The structure may be a structure in which one memory cell transistor is disposed between one word line and one bit line. A gate of the memory cell transistor may be connected to a word line, and a source of the memory cell transistor may be connected to a bit line. Each of the memory cell transistors may include a capacitor. The word line, the memory cell transistor, the bit line, and the capacitor may form one cell, and one unit element may include a plurality of cells.

In one embodiment of the present invention, at least two or more of the plurality of memory cell transistors included inside each of the plurality of unit elements arranged in the first region of the epitaxial wafer according to the present invention may be arranged in the stacking direction of the stacked structure. The structure may be a structure in which the plurality of memory cell transistors within the unit element are stacked and arranged in a third direction. That is, the unit element included in the first region of the epitaxial wafer according to the above example may be a three-dimensional semiconductor memory element. The epitaxial wafer according to the present invention may be formed from a structure in which a silicon layer and a boron-doped silicon germanium layer are cross-stacked, and as described above, the stress between the silicon layer and the silicon germanium layer can be reduced through the boron-doped silicon germanium layer, thereby preventing the occurrence of interlayer dislocation. Through this, a memory element capable of preventing a defect can be implemented even when a high-layer stacked structure is implemented.

In one example, a plurality of word lines included in a unit element of an epitaxial wafer according to the present invention may be arranged vertically with respect to a substrate. Within one unit element, the plurality of word lines may be arranged to be spaced apart from each other in a first direction (D1) or a second direction (D2). When the plurality of word lines are arranged vertically with respect to the substrate, a plurality of bit lines included in the unit element may be arranged horizontally with respect to the substrate, and may be arranged to be spaced apart from each other in a third direction (D3).

In another example, a plurality of bit lines included in a unit element of an epitaxial wafer according to the present invention may be arranged vertically with respect to a substrate. Within one unit element, the plurality of bit lines may be arranged to be spaced apart from each other in a first direction (D1) or a second direction (D2). When the plurality of bit lines are arranged vertically with respect to the substrate, a plurality of word lines included in the unit element may be arranged horizontally with respect to the substrate, and may be arranged to be spaced apart from each other in a third direction (D3).

In another example, a plurality of word lines and a plurality of bit lines included in a unit element of an epitaxial wafer according to the present invention may be arranged vertically with respect to the substrate. Within one unit element, the plurality of word lines and the plurality of bit lines may be arranged spaced apart from each other in a first direction (D1) or a second direction (D2).

The word line and/or bit line may be a conductive pattern and may have a line shape or a bar shape. The word line and/or bit line may include a conductive material, and may be, for example, but is not limited to, one or more selected from the group consisting of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

The present invention also relates to a method for manufacturing an epitaxial wafer. The method for manufacturing an epitaxial wafer according to the present invention includes the steps of alternately growing silicon layers and silicon germanium layers on a substrate; wherein the silicon germanium layers may include doped boron (B). By alternately growing the silicon layers and silicon germanium layers, a stacked structure including the silicon layers and silicon germanium layers may be formed on the substrate.

The above-described laminated structure may include an additional insulating film disposed on the top silicon layer or silicon germanium layer, as needed.

After forming the above-described laminated structure, a patterning process may be performed. The patterning process may include a step of forming a mask pattern having openings, a step of etching the laminated structure using the mask pattern as an etching mask, and a step of removing the mask pattern. A trench may be formed on the substrate by the patterning process, and a portion of an upper surface of the substrate may be exposed by the trenches. Thereafter, a process of forming a new insulating film inside the trench may be performed. The new insulating film may have etching selectivity.

The above patterning process may be performed multiple times depending on the structure of the intended semiconductor. When the patterning process is performed multiple times, a process of forming a new insulating film may be performed after etching at least a portion of the insulating film formed in the previous step. The first region of the epitaxial wafer according to the present invention may mean a unit element after performing the patterning process, and may have a laminated structure of a silicon layer that is not removed in the patterning process and an insulating film that is newly formed after the silicon germanium layer is removed by etching.

In addition, in the above patterning process, a region located outside the mask pattern may be a second region. The second region may include a laminated structure formed by alternately growing a silicon layer and a silicon germanium layer, and the silicon germanium layer may include boron (B) as described above.

After performing the above patterning process, an impurity doping process may be performed on the semiconductor exposed by etching, if necessary. The impurities may be p-type impurities or n-type impurities. The p-type impurities may include B, BF, or a combination thereof, and the n-type impurities may include P, As, or a combination thereof.

In addition, after performing the patterning process, a process of replacing the semiconductor exposed by etching with a conductive material may be performed, if necessary. The process of replacing the semiconductor with the conductive material may include, for example, a silicide process. The exposed semiconductor may react with a metal to form a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). As another example, replacing the semiconductor with the conductive material may include conformally forming a metal nitride film or a metal film on the semiconductor.

After performing the above patterning process, etc., a process of filling the internal empty spaces of the remaining trenches with an insulating film may be performed as needed. The insulating film may include any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

The present invention will be described in more detail through the following examples and comparative examples. However, the spirit of the present invention is not limited to the examples described below.

Changes in bond length and lattice constant of silicon due to impurity doping

The structure and elastic properties of boron-doped silicon were calculated by the following method. First, in order to derive the theoretical value, a simulation was performed on a supercell structure with 64 atoms using DFT (density functional modeling). The Vienna ab initio simulation package (VASP) tool was used as the simulation method, and the changes in the bond length and lattice constant of silicon were confirmed when the dopant was doped into the silicon atoms by 0, 6.25, 12.5, and 18.75%. The simulation was conducted by setting the kinetic cutoff energy to a convergence value of 450 eV and calculating the supercell with a 5 x 5 x 5 Monkhorst-Packgrid.

Material atom% Si-Si (Å) Si-X (X　=　B, Al, Ga) (Å) Si:B 0 2.339 n/a 6.25 2.335 2.048 (n: 16) 12.5 2.336 2.028 (n: 32) 18.75 2.34 2.015 (n: 48) Si:Al 0 2.339 n/a 6.25 2.343 2.426 (n: 16) 12.5 2.341 2.443 (n: 32) 18.75 2.339 2.45 (n: 48) Si:Ga 0 2.339 n/a 6.25 2.341 2.378 (n: 16) 12.5 2.339 2.39 (n: 32) 18.75 2.337 2.397 (n: 48)

Table 1 above shows the bond length according to the concentration when Si is doped with B, Al, and Ga, which belong to group IIIA, respectively. As shown in Table 1, as the content of each doped element increases from 6.25 at% to 18.75 at%, the number of doping elements bonded with Si increases from 0 to 48, and accordingly, the number of Si-Si bonds decreases from 128 to 80.

Also, referring to Table 1, it can be confirmed that when doping with B atoms, the bond length of Si-B decreases as the concentration of B increases. On the other hand, when the concentrations of Al and Ga increase, it can be confirmed that the bond lengths of Si-Al and Si-Ga increase. Through the above results, it can be confirmed that when doping boron into the crystal structure of Si, the bond length can be reduced.

Fig. 5 shows the relaxed lattice constants of (a) Si _1-y B _y , (b) Si _1-y Al _y , and (c) Si _1-y Ga _y calculated using LDA and GGA-PBE. Referring to Fig. 5, it can be confirmed that while the relaxed lattice constant decreases depending on the doping concentration of B even though they belong to the same group IIIA, the relaxed lattice constant increases as the doping concentration increases in the case of Al and Ga doping.

Fig. 6 is a graph showing the average bond length according to the doping concentration of Si _1-y B _y , Si _1-y Al _y , and Si _1-y Ga _y . Referring to Fig. 6, as can be inferred from the change in the lattice constant described above, in the case of B doping, the average bond length decreases as the doping concentration increases, whereas in the case of Al and Ga, the average bond length increases as the doping concentration increases.

Effect of doping on silicon germanium

Si and Ge have lattice constants of 5.43Å and 5.66Å, respectively, and SiGe generally has a lattice constant that is linearly proportional between the above values depending on the ratio of germanium contained in silicon. Therefore, when a silicon layer and a silicon germanium layer are sequentially epitaxially grown, a mismatch occurs between the lattice constant of the silicon layer and the lattice constant of the silicon germanium layer because the lattice constant of the silicon germanium layer is larger than that of the silicon layer.

Fig. 7 is a graph showing the lattice constant calculated according to the change in the concentration of B for Si _1-xy Ge _x B _y . x is the fraction of Ge, and y is the fraction of B. When y is 0, B represents the lattice constant of undoped silicon germanium. Referring to Fig. 7, it can be confirmed that the lattice constant of Si _1-xy Ge _x B _y decreases as y increases, and it can be confirmed that the lattice constant of Si _1-xy Ge _x B _y can be adjusted to have the same value as the lattice constant of silicon, 5.43Å, by changing the value of y. In addition, it can be confirmed that the lattice constant of Si _1-xy Ge _x B _y can be matched with that of silicon by adjusting the fraction of B even when the fraction of Ge increases.

Through the above results, it can be confirmed that when the silicon germanium layer includes boron, the difference in lattice constant with the silicon layer can be reduced. Therefore, the epitaxial wafer according to the present invention can minimize the difference in lattice constant between the silicon layer and the silicon germanium layer, thereby minimizing stress that may occur between the silicon layer and the silicon germanium layer, and can prevent the occurrence of defects by suppressing mismatch or dislocation occurrence between crystal lattice atoms even in a structure in which layers with different components are stacked.

Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

1: Epitaxial wafer
10: Substrate
100: Area 1
111: Unit element
200: Area 2

Claims (15)

substrate; and
A laminated structure including a first region disposed on the substrate and forming a semiconductor element and a second region disposed on the periphery of the first region;
The second region is formed by alternately stacking silicon (Si) layers and silicon germanium (SiGe) layers.
In order to reduce the difference in lattice constant between the silicon layer and the silicon germanium layer, the silicon germanium layer of the second region includes a compound represented by the general formula Si _1-xy Ge _x B _y (0<x≤0.4, 0<y≤0.075),
An epitaxial wafer wherein the lattice constant of the silicon germanium layer of the second region is 5.35 to 5.5 Å.
delete In the first paragraph,
An epitaxial wafer wherein the average thickness of the silicon (Si) layer and/or silicon germanium (SiGe) of the second region is greater than 0 nm and less than or equal to 100 nm.
In the first paragraph,
An epitaxial wafer having a stacking number of three or more layers in the second region.
In the first paragraph,
The above first region is an epitaxial wafer including alternately stacked silicon (Si) layers and insulating layers.
In paragraph 5,
An epitaxial wafer wherein the insulating layer contains a different component from the silicon germanium layer of the second region.
In the first paragraph,
The above first region includes a plurality of unit elements repeated in a direction perpendicular to the stacking direction of the above stacked structure,
An epitaxial wafer in which the above-mentioned plurality of unit elements are arranged spaced apart from each other by scribe lines.
In Article 7,
Each of the above multiple unit elements includes a cell region including a memory cell array,
An epitaxial wafer comprising a circuit region controlling the above memory cell array.
In Article 7,
The above unit element is an epitaxial wafer including a plurality of word lines, a plurality of memory cell transistors connected to each of the word lines, and a plurality of bit lines connected to the memory cell transistors.
In Article 9,
An epitaxial wafer in which at least two of a plurality of memory cell transistors included inside the unit element are arranged in the stacking direction of the stacking structure.
A step of alternately growing a silicon layer and a silicon germanium layer on a substrate;
In order to reduce the difference in lattice constant between the silicon layer and the silicon germanium layer, the silicon germanium layer of the second region includes a compound represented by the general formula Si _1-xy Ge _x B _y (0<x≤0.4, 0<y≤0.075),
A method for manufacturing an epitaxial wafer, wherein the lattice constant of the silicon germanium layer of the second region is 5.35 to 5.5 Å.
delete In Article 11,
A method for manufacturing an epitaxial wafer, wherein the average thickness of the silicon (Si) layer and/or silicon germanium (SiGe) is greater than 0 nm and less than or equal to 100 nm.
In Article 11,
A method for manufacturing an epitaxial wafer, further comprising the step of etching a portion of the silicon germanium layer to form a first region.
In Article 14,
A method for manufacturing an epitaxial wafer, further comprising the step of forming an insulating film in an area where the silicon germanium layer is etched.