KR102682349B1 - Display device and method of driving thereof - Google Patents

Abstract

A display device and a method of driving the display device are provided. A display device includes a substrate having a display area; m*n pixels including a sub-pixels provided in the display area (a is 3 or 4, m and n are positive integers); 2(a*m)+2 data lines on the substrate; n gate lines crossing the data line on the substrate; n rows of subpixels are defined by each of the n gate lines, and n/2 common lines are arranged for each pair of consecutive subpixel rows while intersecting the data lines; and a pixel electrode and a common electrode disposed in each sub-pixel area, wherein each sub-pixel row is disposed on each 2i-th and 2i+1-th data line of a pair of the 2(a*m)+2 data lines. The subpixels of the a*m column are defined (i is a positive integer), and among the subpixels of the a*m column, the subpixels arranged in the jth (j is a positive integer) subpixel column are the 2ith data line and the 2i+ It is characterized by being alternately connected to the first data line (here, i=j).

Description

Display device and method of driving it {DISPLAY DEVICE AND METHOD OF DRIVING THEREOF}

The present invention relates to a display device and a method of driving the same, and more specifically, to a display device and a method of driving the same that improve image quality defects in large display panels or high-resolution display panels.

As the information society develops, the demand for display devices with various forms and functions that visually display electrical information signals is increasing. To meet these needs, display devices such as liquid crystal display devices (LCD) and organic light emitting diode displays (hereinafter referred to as “OLED displays”) are being used.

In addition, in order to improve the performance of display devices, various studies are continuing to make them larger, thinner, lighter, higher resolution, and lower power consumption.

Among these, liquid crystal displays are excellent at displaying moving images and are most actively used in portable terminals, laptops, monitors, TVs, etc. due to their high contrast ratio. The liquid crystal display device includes a switching element, a thin film transistor (hereinafter referred to as "TFT"), in each sub-pixel, and a pixel electrode and a common electrode are disposed to control the light transmittance of the liquid crystal.

In a liquid crystal display device with such a structure, the liquid crystal deteriorates as a voltage difference of the same polarity continues between the pixel electrode and the common electrode, and a flicker phenomenon in which the image flickers frequently occurs. To improve the problem of flickering or sudden screen darkening, an inversion driving method was proposed that inverts the phase of the data signal and supplies it to sub-pixels.

However, as liquid crystal displays become larger and higher resolution, the number of sub-pixels arranged on the display panel increases, and the horizontal period (H) of the gate signal becomes shorter, causing a problem in which the data signal is not sufficiently charged in each sub-pixel. .

In this way, if the data signal is not sufficiently charged in each sub-pixel of the liquid crystal display device, the polarity data voltage offset by the inversion driving method is not smoothly performed, and flicker defects or afterimage defects occur again. In other words, flicker defects and afterimage defects occur even in the inversion driving method proposed to improve flicker defects and afterimage defects in liquid crystal display devices.

The problem to be solved by the present invention is to provide a display device and a driving method that can sufficiently offset the polarity voltage of each sub-pixel by inversion driving even when the display panel becomes larger or higher resolution.

Another problem that the present invention aims to solve is to smoothly maintain the residual polarity voltage of each subpixel by changing the connection structure of each subpixel arranged on the display panel and increasing the horizontal period (pulse width) of the gate signal supplied to the gate lines. The aim is to provide a display device that allows offset and a method of driving the same.

Another problem that the present invention aims to solve is to change the connection structure of each subpixel arranged on the display panel and define a rendering pixel composed of a plurality of subpixels, and then reduce the number of rows of subpixels smaller than the number of rows of subpixels constituting the rendering pixel. A display device and method of driving the same that improve flicker defects and afterimage defects by dividing and driving rendering pixels using gate lines are provided.

Another problem to be solved by the present invention is to provide a display device and a driving method thereof that improve the transmittance of each subpixel by alternately arranging a pair of data lines and a single data line in each row of subpixels of a display panel. It is done.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to solve the problems described above, a display device according to an embodiment of the present invention includes a substrate having a display area; m*n pixels including a sub-pixels provided in the display area (a is 3 or 4, m and n are positive integers); 2(a*m)+2 data lines on the substrate; n gate lines crossing the data line on the substrate; n rows of subpixels are defined by each of the n gate lines, and n/2 common lines are arranged for each pair of consecutive subpixel rows while intersecting the data lines; and a pixel electrode and a common electrode disposed in each sub-pixel area, wherein each sub-pixel row is disposed on each 2i-th and 2i+1-th data line of a pair of the 2(a*m)+2 data lines. The subpixels of the a*m column are defined (i is a positive integer), and among the subpixels of the a*m column, the subpixels arranged in the jth (j is a positive integer) subpixel column are the 2ith data line and the 2i+ It is characterized by being alternately connected to the first data line (here i=j).

A display device according to another embodiment of the present invention includes a substrate having a display area; m*n pixels including 4 sub-pixels provided in the display area (m and n are positive integers); 6m+2 data lines on the substrate; 2k gate lines crossing the data lines on the substrate (where k is a positive integer and n is 3*k, the k value); k common lines crossing the data lines on the substrate; 3 rows of subpixels are disposed between the 2k gate lines and the k common lines to define n rows of subpixels, including a pixel electrode and a common electrode disposed in each subpixel area, and the 6m+2 Among the data lines, subpixel columns are arranged between the adjacent 3i-1th data line and the 3i+1th data line centered on the 3ith data line, defining 4*m columns of subpixels (i is a positive integer). , a rendering pixel consisting of 12 subpixels is defined by the subpixels in the 4*m column and the subpixel in the 3*k row among the subpixels in the n row, and each rendering pixel has at least one adjacent subpixel. Cross sub-pixels are connected to data lines that define pixel columns.

A method of driving a display device according to another embodiment of the present invention includes m*n pixels (m and n are positive integers) including 4 sub-pixels provided in a display area, and the sub-pixels are 6m+. Defined by 2 data lines, 2k gate lines that intersect the data lines (where k is a positive integer and n is 3*k, the k value), and k common lines that intersect the data lines, , a method of driving a display device in which a rendering pixel composed of 12 subpixels in units of 3*k rows among subpixels of 4*m columns and n rows of subpixels defined above is defined, wherein the 2k sequentially supplying a pair of gate signals to a pair of adjacent gate lines among the gate lines; and separately driving sub-pixels arranged within the rendering pixel using the pair of gate signals.

Specific details of other embodiments are included in the detailed description and drawings.

The present invention has the effect of ensuring that the polarity voltage of each sub-pixel can be sufficiently offset even when the display panel is enlarged or has a higher resolution.

The present invention has the effect of improving the transmittance of each subpixel by reducing the number of gate lines and data lines arranged in the display panel.

The present invention has the effect of eliminating flicker defects and afterimage defects by defining the subpixels of the display panel in units of rendering pixels and driving the subpixels within each rendering pixel separately.

The effects according to the present invention are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a block diagram showing a display device according to a first embodiment of the present invention.
2A to 2F are diagrams showing a display device according to a first embodiment of the present invention being driven according to an inversion driving method.
Figure 3 is a diagram showing the sub-pixel arrangement of the display panel according to the first embodiment of the present invention.
FIG. 4 is a diagram showing two subpixels arranged in two consecutive rows among subpixel rows of a display panel according to the first embodiment of the present invention.
Figure 5 is a cross-sectional view taken along line I-I' of Figure 4.
Figure 6 is a cross-sectional view taken along line II-II' of Figure 4.
Figure 7 is a cross-sectional view taken along line III-III' of Figure 4.
Figure 8 is a diagram showing a comparative example of a subpixel arrangement of a conventional display panel for comparison with the present invention.
Figure 9 is a diagram comparing gate signals supplied to display panels of the first embodiment of the present invention and the comparative example, respectively.
Figure 10 is a diagram showing the amount of charge charged to sub-pixels in the first embodiment and comparative example of the present invention.
Figure 11 is a diagram showing a sub-pixel arrangement of a display panel according to a second embodiment of the present invention.
FIG. 12 is a diagram illustrating a structure of three subpixels arranged in the third row of subpixel rows of a display panel according to a second embodiment of the present invention.
13 and 14 are diagrams showing embodiments of a connection structure of cross sub-pixels among sub-pixels of a display panel according to a second embodiment of the present invention.
FIG. 15 is a cross-sectional view taken along line IV-IV' of FIG. 13.
FIG. 16 is a cross-sectional view taken along line V-V' of FIG. 13.
FIG. 17 is a cross-sectional view taken along line Ⅵ-VI' of FIG. 13.
Figure 18 is a diagram comparing gate signals supplied in the second embodiment of the present invention and the comparative example.
Figure 19 is a diagram showing the amount of charge charged to the subpixels of the second embodiment of the present invention and the comparative example.
Figure 20 is a diagram showing the sub-pixel arrangement of the display panel according to the third embodiment of the present invention.
Figure 21 is a diagram showing the sub-pixel arrangement of the display panel according to the fourth embodiment of the present invention.
Figure 22 is a diagram showing the operation of subpixels of the display panel according to the first embodiment of the present invention.
Figure 23 is a flowchart showing a method of driving a display device according to the first embodiment of the present invention.
24 and 25 are diagrams showing the operation of subpixels of a display panel according to second to fourth embodiments of the present invention.
Figure 26 is a flowchart showing a method of driving a display device according to second to fourth embodiments of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. In cases where a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'on the side', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used. Additionally, for example, when the positional relationship between two parts is described as 'on top', it may be explained as positions such as 'on top', 'on bottom', or 'on the side'.

When an element or layer is referred to as being on another element or layer, it includes all cases where another layer or other element is interposed directly on or in the middle of another element.

Additionally, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, the present invention will be described with reference to the drawings.

1 is a block diagram showing a display device according to a first embodiment of the present invention. 2A to 2F are diagrams showing a display device according to a first embodiment of the present invention being driven according to an inversion driving method.

Referring to FIG. 1, the display device 100 of the present invention includes a display panel 110 on which a pixel array is formed, and a display panel driving circuit for writing data of an input image into the display panel 110. The display panel driving circuit writes data of the input image to pixels composed of sub-pixels. The display panel driving circuit includes a data driver 120, a gate driver 130, and a controller 150.

Here, the data driver 120 is also called a data driver or source driver, and the gate driver 120 is also called a gate driver or scan driver. Additionally, the controller 150 may be a timing controller used in typical display technology, or may be a control device that performs other control functions, including a timing controller.

The display panel 110 includes an upper substrate and a lower substrate that face each other with a liquid crystal layer therebetween. A pixel array on which an input image is displayed is formed in the active area of the display panel 110. The pixel array includes subpixels arranged in a matrix form by an intersection structure of a plurality of data lines DL and a plurality of gate lines GL.

Here, the direction parallel to the gate line GL of the display panel 110 is defined as the X direction (or first direction), and the direction parallel to the data line DL is defined as the Y direction (or second direction). Accordingly, the X direction may be referred to as the horizontal direction and the Y direction may be referred to as the vertical direction.

Each pixel is composed of red (R), green (G), blue (B) sub-pixels or red (R), green (G), blue (B), and white (W) sub-pixels to implement color. It can be.

In addition, as in the present invention, 12 subpixels arranged in 4 columns and 3 rows of subpixels can be defined as one unit rendering pixel, and the subpixels in each rendering pixel can be divided and driven to implement a color image. Display The lower substrate of the panel 120 includes a plurality of data lines (DL), a plurality of gate lines (GL), a thin film transistor (TFT) disposed in an area corresponding to each sub-pixel, and a pixel electrode connected to the TFT. , a storage capacitor (Cst) connected to the pixel electrode, and a common electrode that forms an electric field to control the transmittance of the liquid crystal together with the pixel electrode (not shown).

TFTs formed on the lower substrate of the display panel 110 may be implemented as amorphous silicon (a-Si) TFT, low temperature poly silicon (LTPS) TFT, oxide TFT, etc. TFTs are formed at the intersection of the data line DL and the gate line GL (see FIG. 3). TFTs supply data voltage from a data line to the pixel electrode in response to a gate signal.

A color filter array including a black matrix (BM) and a color filter may be formed on the upper substrate of the display panel 110. However, since this is not fixed, a color filter array can be formed on the lower substrate on which the TFTs are formed.

In the present invention, the description is focused on the IPS mode (In-Plane Switching Mode) or FFS mode (Fringe Field Mode), which is a horizontal electric field driving method in which the pixel electrode and the common electrode are placed together in the subpixel (SP), but the common electrode is TN (TN). In the case of a vertical electric field driving method such as Twisted Nematic (Twisted Nematic) mode and VA (Vertical Alignment) mode, it can be formed on the upper substrate.

Additionally, a polarizing plate may be attached to each of the upper and lower substrates of the display panel 110 and an alignment film may be formed to set a pre-tilt angle of the liquid crystal.

Additionally, touch sensors may be placed on the display panel 110 as an on-cell type or an add-on type. To drive such a touch sensor, a touch sensor driver (not shown) may be added to the driving circuit of the display device 100.

The touch sensor driver may receive the output signal of the touch sensor, generate coordinates for each touch input, and transmit them to a host system (not shown).

The display device of the present invention can be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, or a reflective liquid crystal display device. Transmissive and semi-transmissive liquid crystal displays require a backlight unit.

The backlight unit is disposed below the display panel 110 and uniformly irradiates light to the display panel 110. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

Additionally, the driving circuit of the display panel 110 may further include a gamma compensation voltage generator (not shown) that supplies a gamma reference voltage (GMA) to the data driver 120. The gamma reference voltage (GMA) may be divided into a positive gamma compensation voltage and a negative gamma compensation voltage within the data driver 120 and supplied to the display panel 110. More specifically, the voltage divided into the positive gamma compensation voltage and the negative gamma compensation voltage is generated by a multiplexer (MUX) (not shown) disposed within the data driver 120 or between the data driver 120 and the display panel 110. ) can be supplied to a plurality of data lines (DL).

Generally, a positive data voltage is supplied to a plurality of data lines DL through a multiplexer. The positive data voltage supplied to the plurality of data lines DL is a voltage higher than the common voltage Vcom applied to the common electrode, and the negative data voltage is lower than the common voltage Vcom.

The data driver 120 may include one or more source drive ICs (SICs). Each source driver IC may include a plurality of channels, and the number of source driver ICs disposed in the data driver 120 may be determined depending on the resolution of the display panel 110.

For example, in the case of the 8k 120Hz model among high-resolution TV models (the number of subpixels is 7680*3*4320), the number of channels of the source drive IC is 1920, and the data driver 120 has 24 source drive ICs. can be placed.

The gate driver 130 supplies gate signals to the plurality of gate lines GL under the control of the controller 150.

The controller 150 transmits input image data received from a host system (not shown) disposed inside or outside the display device 100 to the data driver 120. The controller 150 receives timing signals that are synchronized with input image data from the host system.

Timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock (DCLK). The controller 150 controls the operation timing of the data driver 120 and the gate driver 130 based on timing signals (Vsync, Hsync, DE, and DCLK).

The gate control signal is generated by the controller 150 to control the operation timing of the gate driver 130. Gate control signals include Gate Start Pulse (GSP), Gate Shift Clock (GSC), and Gate Output Enable (GOE). The gate start pulse (GSP) controls the start operation timing of the gate driver 130. The gate shift clock (GSC) is a clock signal for shifting the gate start pulse (GSP). The gate output enable signal (GOE) controls the output timing of the gate driver 130.

The source control signal is generated by the controller 150 to control the operation timing of the data driver 120. The source control signal includes a source start pulse (SSP), source sampling clock (SSC), polarity control signal (POL), and source output enable signal (SOE).

The source start pulse (SSP) controls the data sampling start timing of the data driver 120. The source sampling clock (SSC) is a clock signal that controls the data sampling timing of the data driver 120. The polarity control signal (POL) controls the polarity of the data voltage output from the data driver 120. The source output enable signal (SOE) controls charge sharing timing and data output timing. The controller 150 transmits the gate control signal and the source control signal through separate wires or codes and inputs information about the on/off (or high/low) level of each of the signals into a control data packet. It can be serially transmitted to source drive ICs along with video data.

The controller 150 increases the frame rate at a frequency of Hz (frame rate or frame frequency) of the input image (N is a positive integer of 2 or more) and sets the driving frequency of the display panel 110 to a frame multiplied by N times. It can be controlled by rate. The frame rate is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method. Recently, there is a trend to adopt a method of increasing the frame rate to 120Hz or higher to implement high-resolution images such as UHD.

Additionally, when the data of the input image changes little or is a still image, the controller 150 drives the display panel driving circuit at a low speed to lower the update frequency of data written to the pixels in order to reduce power consumption. For example, the timing controller 105 can lower the frame rate to 30 Hz or less in a low-speed driving mode. The frame rate in low-speed driving mode may be referred to as LRR (Low Refresh Rate).

The controller 150 is a host system that overall controls television systems, home theater systems, set-top boxes, navigation systems, DVD players, Blu-ray players, personal computers (PCs), phone systems, mobile devices, wearable devices, etc. Timing signals (Vsync, Hsync, DE, CLK) along with digital video data (RGB) of the image are transmitted from (not shown). This host system can execute an application program in conjunction with coordinate information of a touch input input from a touch sensor driver disposed within the display device 100.

In addition, the controller 150 controls the polarity of the data voltage applied to each of the sub-pixels SP using the polarity control signal POL to drive the display device 100 in the manner shown in FIGS. 2A to 2F. The method can be controlled using various inversion methods.

Referring to FIGS. 2A to 2F, a square with polarity (+, -) indicates one sub-pixel.

Figure 2a shows a frame inversion driving method. In the first frame, an electric field of positive polarity is applied to all subpixels, and in the second frame, the polarity is reversed to apply negative polarity to all subpixels. An electric field is applied.

Figure 2b shows a line inversion driving method. In the first frame, a (+) polarity electric field is applied to the subpixels of odd-numbered lines, and a (-) polarity electric field is applied to subpixels of even-numbered lines. is applied, and in the second frame, the polarity is reversed so that a (-) polarity electric field is applied to the sub-pixels of odd-numbered lines and a (+) polarity electric field is applied to sub-pixels of even-numbered lines.

Figure 2c shows the column inversion driving method. In the first frame, an electric field of positive polarity is applied to subpixels in odd-numbered columns and an electric field of negative polarity is applied to subpixels in even-numbered columns. In the second frame, the polarity is reversed, so that a (-) polarity electric field is applied to the subpixels in odd-numbered columns, and a (+) polarity electric field is applied to subpixels in even-numbered columns.

FIG. 2D shows a dot inversion driving method, in which adjacent subpixels have opposite polarities, and for each subpixel, the polarity in the first frame and the polarity in the second frame are inverted.

2E and 2F are a driving method that is a modified version of the dot inversion driving method. In FIG. 2E, the polarities of two sub-pixels in the column direction of the sub-pixels are opposite to each other, and the polarity of each sub-pixel in the first frame is different from the polarity in the first frame. The polarities in the second frame are reversed. This driving method is also called a vertical 2-dot inversion driving method. Figure 2f is called a horizontal 2-dot inversion driving method. Unlike Figure 2e, the polarities of the two subpixels in the row direction of the subpixels are opposite to each other, and for each subpixel, the polarity in the first frame and the polarity in the second frame are different. The polarities are reversed.

In this way, the polarity of the data voltage applied to each subpixel can be inverted into dot inversion, line inversion, column inversion, etc. within one frame period. Accordingly, within one frame period, the polarity of the subpixels may be reversed in the column or row direction on a column-by-column basis, a row-by-row basis, a neighboring sub-pixel basis, or two sub-pixels. Additionally, when viewed on the time axis, the polarity of each subpixel is inverted on a frame period basis by the data voltage whose polarity is inverted, as shown in FIGS. 2A to 2F.

In this specification, the description will focus on the inversion driving method corresponding to FIGS. 2D to 2F, but this does not mean that the driving method for the display device of the present invention is limited. The display device can be driven in the various inversion driving methods described above by modifying the connection structure of the sub-pixels, data lines, and gate lines arranged in the display panel of the present invention or by adjusting the data voltage supplied from the data driver.

In particular, as display panels become larger and higher resolution, the frame rate frequency (Hz) of the input image increases. When the frame rate frequency increases, the horizontal period (H: pulse width) of the gate signal supplied to each gate line increases. ) is shortened, causing a problem in which the polarity data voltage is not sufficiently charged in each subpixel. In this way, if the data voltage is not sufficiently charged in each sub-pixel, the inversion driving method does not completely offset the residual charge of each sub-pixel, which causes flicker defects and afterimage defects to occur again.

However, the present invention allows the polarity data voltage to be sufficiently charged in each sub-pixel even when the frame rate frequency (Hz) of the input image increases, thereby eliminating flicker defects and afterimage defects caused by the inversion driving method.

Additionally, the present invention has the effect of improving the transmittance of each sub-pixel by reducing the number of gate lines and data lines disposed on the display panel (the effect of increasing the area of the transmission area of the sub-pixel).

In addition, the present invention defines the subpixels of the display panel in units of rendering pixels and drives the subpixels within each rendering pixel separately so that the data voltage can be sufficiently charged in each subpixel.

Figure 3 is a diagram showing the sub-pixel arrangement of the display panel according to the first embodiment of the present invention.

Referring to FIG. 3 along with FIG. 1 , the display panel 110 of the present invention displays an image through pixels arranged in a matrix form. As shown in FIG. 3, the pixel is a first pixel (P1) defined by three sub-pixels (SP) consisting of red (R), green (G), and blue (B), or two red (R) and green pixels. It can be defined as a second pixel (P2) defined by four sub-pixels (SP) composed of (G) and blue (B). Here, as shown in the figure, the second pixel P2 is composed of two red (R) subpixels and green (G) and blue (B) subpixels, or two green (G) and red (R) subpixels. , blue (B) sub-pixels or red (R), green (G) and two blue (B) sub-pixels. Additionally, the second pixel P2 may be defined by red (R), green (G), blue (B), and white (W) subpixels.

Therefore, the description here focuses on the second pixel (P2) composed of red (R), green (G), blue (B), and red (R) sub-pixels, but the first pixel (P1) or the second pixel (P2) can be applied in the same way by defining it as a pixel that selectively includes sub-pixels of various colors that are different from the configuration of the sub-pixels described above.

In addition, the subpixel SP shown in FIG. 3 displays the polarity (+, -) of the data voltage applied to each subpixel in one frame according to the dot inversion driving method described in FIG. 2D.

As shown in FIG. 3, the display panel 110 of the present invention is divided into a display area that displays an image and a non-display area around the display area, and a plurality of pixels are arranged in a matrix form on the lower substrate of the display area. It is arranged into n columns and n rows (where m and n are positive integers).

Therefore, as described above, if the number of subpixels constituting a pixel is a, the number of subpixels is a*m. For example, when a pixel is composed of three sub-pixels (SP) like the first pixel (P1), the row of sub-pixels is made up of 3*m, and the row of sub-pixels is composed of 4 sub-pixels (SP) like the second pixel (P2). When configured as (SP), the number of sub-pixels is 4*m.

In addition, in the display panel 110 of the present invention, a subpixel (SP) is defined by two data lines (DL) and one gate line (GL). Referring to the drawing, each row of subpixels is two on one side. It can be defined in the form in which data lines are arranged. Accordingly, one data line is added to one side of the column of the first subpixel or the other side of the column of the last subpixel. However, as explained above, this definition is not fixed.

For example, each row of subpixels has a pair of data lines on the left and right sides centered on the subpixel row, and an additional data line on the left and right of the first subpixel row or the last subpixel row, respectively. It can be defined as arranged. In addition, the even-numbered data line and the odd-numbered data line are placed on the left and right sides of each column of subpixels, respectively, and the odd-numbered data line is placed on the left and right of the column of the first or last subpixel, respectively ( It can be defined as the arrangement of the first data line) and the most significant data line (the last data line). Additionally, it can be added to the definition that a pair of data lines consisting of a continuous odd-numbered data line and an even-numbered data line are disposed between adjacent columns of subpixels.

Therefore, the data lines DL according to the first embodiment of the present invention may be composed of 2(a*m)+2, and when a is 3, 6*m+2 data lines DL are arranged. If a is 4, 8*m+2 data lines (DL) are arranged.

Accordingly, the data line DL disposed on the display panel 110 of the present invention includes 2(a*m)+2 data lines arranged from the left to the right (X-axis direction) of the display area, of which A pair of 2i-th and 2i+1-th data lines are arranged in each column of subpixels (i is a positive integer).

In addition, the display panel 110 of the present invention has a*m rows of subpixels, of which 2i are placed on the left and right sides of the jth (j is a positive integer) subpixel row arranged along the X-axis direction, respectively. The th data line and the 2i+1th data line (where i=j) are arranged. Here, the total number of sub-pixel columns other than the pixel column is 3*m or 4*m depending on the structure of the first pixel (P1) or the second pixel (P2) above, so the maximum number of j columns is 3*m or It is 4*m dog.

A row of subpixels of the present invention may be defined by a gate line (GL). In the first embodiment of the present invention, rows of subpixels are defined to correspond to each of the n gate lines GL, so the number of rows of subpixels and the number of gate lines GL are the same. Therefore, since the pixel is defined above as the number of subpixels in the horizontal direction, the maximum number of rows of subpixels and rows of pixels (first or second pixels) is n.

In addition, a common line (VCOM) is arranged to intersect the data line (DL) and parallel to the gate line (GL), and the common line (VCOM) is arranged for each pair of consecutive subpixel rows (or consecutive gate lines). n/2, which is half the number of gate lines (GL), are arranged. The pixel electrode and common electrode shown in FIG. 4 are disposed in each sub-pixel (SP) area.

Accordingly, each of the common lines (VCOM) can supply a common voltage to the subpixels (SP) corresponding to the two subpixel rows. In the first embodiment of the present invention, two rows of consecutive subpixels are driven by a gate signal supplied to a pair of gate lines.

Among the subpixels arranged in the display panel 110 of the present invention, the subpixels arranged in the jth column are alternately connected to the 2ith data line and the 2i+1th data line arranged on both sides. For example, the red (R) subpixels arranged in the first subpixel column are connected to the second data line (DL2) and the third data line (DL3) along the vertical direction (parallel to the Y direction or the data line direction). Each is connected alternately (connected in a zigzag pattern).

Additionally, in the first embodiment of the present invention, the first data line DL1 and the last data line DL_2(a*m)+2 are not connected to the subpixel SP, so the two data lines DL are It can be removed. However, since two data lines are placed in the left and right areas based on each column of subpixels (SP), data lines (DL1, DL_2(a*m)+2) are additionally placed to maintain balance. It is desirable.

This is because, if the components arranged in adjacent areas of each sub-pixel row are different, differences in electric field or parasitic capacitance that affect each sub-pixel row occur, resulting in luminance non-uniformity.

FIG. 4 is a diagram showing two subpixels arranged in two consecutive rows among subpixel rows of a display panel according to the first embodiment of the present invention. Figure 5 is a cross-sectional view taken along line I-I' of Figure 4. Figure 6 is a cross-sectional view taken along line II-II' of Figure 4. Figure 7 is a cross-sectional view taken along line III-III' of Figure 4.

First, referring to FIG. 4 along with FIG. 1, the subpixels SP disposed on the display panel 110 of the first embodiment of the present invention are disposed in two subpixel rows along the vertical direction (Y-axis). It operates on a sub-pixel basis. For example, the subpixels (SP) arranged in two rows in the vertical direction centered on the first common line (VCOM1) are connected to the gate signal supplied to the first gate line (GL1) and the second gate line (GL2). driven together by

Accordingly, among the rows of subpixels arranged in the display panel 110, the jth subpixel row is driven in units of subpixels corresponding to a pair of consecutive gate lines GL1 and GL2. Accordingly, as shown in the figure, the 2i-1th data line, the 2ith data line, the 2i+1th data line, and the 2i+2th data line are arranged on both sides of the jth subpixel column, respectively.

A thin film transistor (TFT) is disposed in each subpixel (SP), and the thin film transistor disposed in each subpixel (SP) is connected to the 2i-th data line ((2i)th DL) and the 2i+1th data line ((2i) +1)th DL) is connected alternately.

In addition, a pixel electrode and a common electrode are disposed in each sub-pixel (SP) area, and the pixel electrode according to the first embodiment of the present invention is parallel to the first gate line (GL1) or the first common line (VCOM1). It consists of one pixel electrode (400a) and a second pixel electrode (400b) in which a portion of the sub-pixel column is bent in a specific direction.

Correspondingly, a common electrode is disposed in the sub-pixel (SP) area. The common electrode according to the first embodiment of the present invention is a first common electrode parallel to the first common line (VCOM1) or the first gate line (GL1). (410a), a second common electrode 410b alternately disposed with the second pixel electrode 400b in the sub-pixel (SP) area, and a 2i-th data line disposed on both sides of the sub-pixel column (j-th column) A third common electrode 410c is disposed overlapping the 2i-1th data line, the 2i+1th data line, and the 2i+2th data line. Here, the first pixel electrode 400a and the second pixel electrode 400b are formed integrally with each other, and the first to third common electrodes 410a, 410b, and 410c are formed integrally with each other.

Additionally, first and second storage electrodes 420a and 420b, which together with the first and second pixel electrodes 400a constitute a storage capacitor, are disposed in the sub-pixel (SP) area. The first storage electrode 420a is formed in an area adjacent to the first gate line GL1 so as to overlap the first pixel electrode 400a and the second pixel electrode 400b, and the second storage electrode 420b is a sub-pixel. It is formed integrally with the first common line (VCOM1) along both edges of the (SP) area. In the drawing, two second storage electrodes 420b are formed to extend from both edges of the first storage electrode 420a, but in some cases, one may be formed along one edge of the first storage electrode 420a.

Additionally, in the first embodiment of the present invention, auxiliary patterns 430a and 430b can be formed in areas on both sides of each sub-pixel column. As the resolution of the auxiliary patterns 430a and 430b increases, the area of the subpixel (SP) decreases and is used to secure storage capacitance or to shield the data voltage supplied to the adjacent subpixel column or the electric field formed by the adjacent subpixel column. It can be used to do this.

With reference to FIGS. 5 to 7, the cross-sectional views taken along the lines I-I', II-II', and III-III' of FIG. 4 are as follows.

Line Ⅰ-Ⅰ' is a cross-sectional view of a thin film transistor (TFT), some pixel electrodes, and a common electrode in the sub-pixel (SP) area. A thin film transistor (TFT) includes a gate electrode 501 disposed on a substrate 500, a gate insulating layer 502 disposed on the gate electrode 501, and a gate insulating layer 502 corresponding to the gate electrode 501. It includes a semiconductor layer 514, a source electrode 517a, and a drain electrode 517b disposed thereon.

The gate electrode 501 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof, but is not limited thereto. The gate electrode 501 may be made of a single layer of a conductive material or a plurality of layers including a conductive material.

The gate insulating layer 502 is a layer for insulating the gate electrode 501 and the semiconductor layer 514, and may be made of an insulating material. For example, the gate insulating layer 502 may be composed of a single layer or a multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A semiconductor layer 514 is disposed on the gate insulating layer 502. For example, the semiconductor layer 514 may be made of an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

The source electrode 517a and the drain electrode 517b are disposed on the semiconductor layer 514 to be spaced apart from each other. The source electrode 517a and the drain electrode 517b may be electrically connected to the semiconductor layer 514. The source electrode 517a and the drain electrode 517b may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof. It is not limited. The source electrode 517a and the drain electrode 517b may be made of a single layer of a conductive material or a plurality of layers including a conductive material.

A protective layer 520 is disposed on the thin film transistor (TFT). It may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the protective layer 520 may be formed of an organic material including acrylic, or a multi-layer structure of alternating organic and inorganic materials.

As shown in FIG. 5, a fourth contact hole C4 is formed on the protective layer 520 to connect the first pixel electrode 400a disposed on the protective layer 520 and the lower portion of the protective layer 520. The disposed drain electrode 517b is electrically connected.

In the sub-pixel (SP) area, pixel electrodes and common electrodes are alternately arranged. For example, the second pixel electrode 400b constituting the pixel electrode and the second common electrode 410b constituting the common electrode are alternately arranged in the sub-pixel (SP) area.

The Ⅱ-Ⅱ' line is an area where the second auxiliary pattern 430b and the third common electrode 410c are connected in the area where the data lines (2i+1th data line and 2i+2th data line) are arranged, Line Ⅲ-Ⅲ' is an area where the first common electrode 410a and the first common line (VCOM1) are connected in the first common line (VCOM1) area.

As shown in FIG. 6, a second auxiliary pattern 430b is disposed between the 2i+1th data line and the 2i+2th data line. The second auxiliary pattern 430b is electrically connected to the third common electrode 410c through the third contact hole C3 formed in the gate insulating layer 502 and the protective layer 520.

In this way, when the second auxiliary pattern 430b is connected to the third common electrode 410c, it serves to supplement the storage capacitance of the subpixel (SP) area. If the second auxiliary pattern 430b is disposed without being connected to the common line or common electrode, it functions to shield the electric field applied from the adjacent sub-pixel column.

As shown in FIG. 7, in the first common line VCOM1 area, the first common electrode 410a and the first common line VCOM1 are electrically connected through the first contact hole C1.

Figure 8 is a diagram showing a comparative example of a subpixel arrangement of a conventional display panel for comparison with the present invention. Figure 9 is a diagram comparing gate signals supplied to display panels of the first embodiment of the present invention and the comparative example, respectively. Figure 10 is a diagram showing the amount of charge charged to the subpixels of the first embodiment and comparative example of the present invention.

Referring to FIG. 8, as in the comparative example, in the prior art, one subpixel (SP) is defined by one data line (DL1) and one gate line (GL1), and each subpixel (SP) column Subpixels arranged along each subpixel (SP) column receive a polarity data voltage from one data line corresponding to .

Therefore, from the perspective of the rows of subpixels, gate signals are sequentially supplied to each of the gate lines (GL1, GL2, GL3, ....) arranged on the display panel, so that the subpixels are sequentially driven in each row of subpixels. .

At this time, when driving the display device according to the inversion driving method, polarity data voltages (+, -) are alternately supplied to each data line (DL1, DL2, DL3, ...) as shown in FIG. 8. , the polarities of adjacent subpixels along the subpixel row are varied. However, when the display device becomes higher resolution and the frame rate frequency of the input image increases from 60Hz to 120Hz or 180Hz, a problem occurs in which the horizontal period (1H: pulse width) of the gate signal becomes shorter.

For example, assuming that the frame rate frequency of the input image is 60Hz and the horizontal period (1H) of the gate signal is 1㎲, at 120Hz, the horizontal period (1H) of the gate signal is shortened to 0.5㎲ (because 1 second per second) This is because while displaying 60 video frames, you have to display 120 video frames). Additionally, in the case of high-resolution display devices, the number of subpixels per unit area increases, so a shorter gate signal must drive more subpixels.

As such, as display devices become higher resolution and frame rate frequencies increase, when gate signals are consistently supplied to each sub-pixel row sequentially as in the prior art, the polarity data voltages (+, -) supplied through the data lines ) is not sufficiently charged in the sub-pixel area.

If the polarity data voltage (+, -) is not sufficiently charged in each sub-pixel area, the residual polarity voltage in the sub-pixel area cannot be offset even by inversion driving, and flicker defects and afterimage defects re-occur in the display device. In other words, even in the inversion driving method developed to eliminate flicker defects and afterimage defects that occur in display devices, the problem of flicker defects and afterimage defects still exists.

However, in the first embodiment of the present invention, as shown in FIGS. 3 and 9, the frame rate is increased by overlapping and supplying a gate signal with twice the horizontal period (2H) to a pair of consecutive (adjacent) gate lines. This was done to compensate for the shortened horizontal period of the gate signal due to the increase in frequency.

To be more specific, when the pixel of the first embodiment of the present invention has a second pixel (P2) structure composed of four sub-pixels (SP), the first gate line (GL1) and the second gate line (GL2) have the same structure. Gate signals with gate signal widths are overlapped and supplied. At this time, the horizontal period (gate pulse width) of the gate signal supplied to the pair of gate lines (GL1, GL2) is 2H, which is twice the horizontal period (H) of each gate signal. That is, in the first embodiment of the present invention, twice the horizontal period (H) is overlapped and supplied to a pair of adjacent gate lines. Therefore, in the first embodiment of the present invention, the subpixels arranged in a pair of rows of the subpixels are simultaneously driven with twice the horizontal period (H) to increase the turn-on period of the thin film transistor arranged in each subpixel. This ensured that the polarity data voltages (+, -) could be sufficiently charged in the subpixels.

Referring to Figures 9 and 10, in the first embodiment of the present invention, gate signals are simultaneously supplied sequentially to a pair of adjacent gate lines among gate lines arranged on the display panel. At this time, the gate signal width of the gate signals supplied to a pair of gate lines is not 1H but 2H, that is, the gate signal with a period (2H) that is the sum of the horizontal periods (1H) of the two gate signals is supplied.

Accordingly, the subpixels arranged on the display panel are driven in units of 2 rows, and the width of the driving gate signal is doubled. Because the horizontal period of the gate signal is doubled, the polarity data voltages (+, -) supplied to each subpixel through the data lines can be sufficiently charged.

Referring to FIG. 10, in the prior art (comparative example), the gate signal width is 1H, so when the high-resolution display device and the frame rate frequency increase, the turn-on period of the thin film transistor (TFT) disposed in each sub-pixel is short, resulting in a polarity data voltage. (+, -) does not reach the normal charge amount (X1).

However, in the first embodiment of the present invention, since the horizontal period of the gate signal is doubled, the polarity data voltages (+, -) charged in each sub-pixel are charged to more than the normal charge amount (X2).

As such, in the first embodiment of the present invention, even if the display panel becomes larger or higher resolution, each sub-pixel is sufficiently charged with the polarity data voltage, so polarity voltage offset by the inversion driving method can be smoothly achieved. Because of this, the present invention has the effect of eliminating flicker defects and afterimage defects even when the display panel becomes larger or higher resolution.

Figure 11 is a diagram showing a sub-pixel arrangement of a display panel according to a second embodiment of the present invention.

Since the first embodiment of the present invention has been described in FIG. 3 in relation to the second embodiment of the present invention, the following description will focus on the differentiated parts.

Referring to FIG. 11 along with FIG. 1, the display panel 110 according to the second embodiment of the present invention displays an image through pixels arranged in a matrix form. The pixel P is composed of four sub-pixels SP, like the second pixel P2 in FIG. 3. For example, a pixel (P) consists of two red (R) subpixels plus a green (G) and blue (B) subpixel, or two green (G), red (R), and blue (B) subpixels. or red (R), green (G) and two blue (B) subpixels. Additionally, red (R), green (G), blue (B), and white (W) subpixels may be defined.

As shown in FIG. 11, in the second embodiment of the present invention, a plurality of pixels P are arranged in m columns and n rows (where m and n are positive integers). Accordingly, in the second embodiment of the present invention, since the pixel P is composed of four sub-pixels SP, the number of rows of sub-pixels is 4*m. Additionally, in the second embodiment of the present invention, if the data lines arranged to correspond to each sub-pixel column are viewed as the left data line, 6 data lines are arranged in units of 4 sub-pixel columns. Additionally, two data lines are additionally placed on the right side of the last subpixel column, so the number of data lines DL is 6*m+2.

Additionally, since a pair of gate lines GL are arranged in units of 3 rows of subpixels, the number of gate lines GL is 2k. At this time, k is a positive integer and is the k value when n is 3*k. Since one common line (VCOM) that intersects the data line (DL) is arranged in units of three rows of subpixels, when the number of common lines (VCOM) arranged in the display panel 110 is l, (l is a positive integer), when n is 3*l, it is the l value. Accordingly, the number of common lines (VCOM) for n-row subpixels is reduced to l (n/3).

In the second embodiment of the present invention, n rows of subpixels are defined in such a way that three subpixel rows are respectively arranged between 2k gate lines (GL) and l common lines (VCOM). A pixel electrode and a common electrode are disposed in each sub-pixel (SP) area.

In addition, among the 6*m+2 data lines (DL), subpixel columns are arranged between the adjacent 3i-1th data line and the 3i+1th data line centered on the 3ith data line (i is a positive integer). ).

In particular, in the second embodiment of the present invention, 12 subpixels are defined as rendering pixels (RP) by subpixels in 4*m columns and subpixels in 3*k rows among subpixels in n rows. That is, in the second embodiment of the present invention, the driving is controlled in units of 12 subpixels among the rows of subpixels arranged on a pair of gate lines (GL) and one common line (VCOM).

Additionally, in the second embodiment of the present invention, subpixels arranged in each subpixel column are alternately connected to data lines DL arranged on both sides of the subpixel column. That is, in the second embodiment of the present invention, a pair of sub-pixel columns are arranged on both sides of the 3i-th data line, and the 3i-1-th data line and the 3i+1-th data line are arranged on both sides of the pair of sub-pixel columns. do. The 3i-1th, 3i-th, and 3i-1st data lines are connected to subpixels arranged in a pair of subpixel columns. However, the rendering pixel (RP) area includes 12 subpixels composed of subpixels in 4 columns and 3 rows, so it includes at least two pairs of subpixel columns. Therefore, in terms of rendering pixels (RP), a pair of data lines are placed between a pair of sub-pixel columns and an adjacent pair of sub-pixel columns, and these are data lines arranged to connect to a pair of sub-pixel columns and a pair of adjacent sub-pixel columns, respectively. am. In the second embodiment of the present invention, since the subpixels arranged in the rendering pixel (RP) area are divided and driven, a pair of subpixel columns includes a subpixel connected to a data line arranged for connection to another pair of subpixel columns. At least one or more subpixels are arranged, and these subpixels are defined as cross subpixels.

For example, when a pair of sub-pixel columns placed on both sides of the 3i-th data line are called the j-th column and j+1-th column, the j-th sub-pixel column has the 3i-1-th data line and the 3i-th data line on both sides. is arranged, and the 3i-th data line and the 3i+1-th data line are arranged in the j+1th subpixel column (i and j are positive integers). The subpixels SP arranged in the jth subpixel column are alternately connected to the 3i-1th data line ((3i-1)th DL) and the 3ith data line ((3i)th DL), respectively. However, in the case of cross subpixels, at least one of the subpixels of the jth subpixel column is connected to the 3i-2th data line ((3i-2)th DL), and the subpixels of the j+1th subpixel column are connected to the 3i-2th data line ((3i-2)th DL). At least one of them is connected to the 3i+2th data line ((3i+2)th DL).

To express this differently, between a pair of sub-pixel columns (j-th column and j+1-th column) and a pair of adjacent sub-pixel columns (j+2-th column and j+3-th column), there are 3i+1-th and 3i+2-th data. Lines ((3i+1)th DL, (3i+2)th DL) are placed, and the 3i+1th data line ((3i+1)th DL) is a subpixel placed in the j+2th subpixel column. It is connected to at least one of (cross subpixel in the j+2th subpixel column). Additionally, the 3i+2th data line ((3i+2)th DL) is connected to at least one of the subpixels arranged in the j+1th subpixel column (cross subpixel in the j+1th subpixel column). .

In the second embodiment of the present invention, the subpixels constituting the rendering pixel are divided and driven again in units of 6 subpixels. In order to perform this divided driving, at least one cross subpixel can be placed in the rendering pixel (RP). there is.

In the second embodiment of the present invention, gate lines are arranged corresponding to n-row sub-pixels twice the value of k when n is 3*k, so the number of sub-pixels is less than the number of n-rows. In addition, the common line (VCOM) is arranged in n/3 common lines because one common line is arranged in units of 3 rows of subpixels.

FIG. 12 is a diagram illustrating a structure of three subpixels arranged in the third row of subpixel rows of a display panel according to a second embodiment of the present invention. 13 and 14 are diagrams showing embodiments of a connection structure of cross sub-pixels among sub-pixels of a display panel according to a second embodiment of the present invention. FIG. 15 is a cross-sectional view taken along line IV-IV' of FIG. 13. FIG. 16 is a cross-sectional view taken along line V-V' of FIG. 13. FIG. 17 is a cross-sectional view taken along line Ⅵ-VI' of FIG. 13.

The same reference numerals as those in FIG. 4 illustrating the first embodiment of the present invention refer to the same components. Hereinafter, the description will focus on parts that are different from the first embodiment of the present invention.

First, referring to FIG. 12 together with FIG. 1, the subpixels SP disposed on the display panel 110 of the second embodiment of the present invention are disposed in three subpixel rows along the vertical direction (Y-axis). It operates on a sub-pixel basis. For example, three rows of subpixels in the vertical direction centered on the first common line (VCOM1) are defined by two gate lines (GL1, GL2), and centered on each of the two gate lines (GL1, GL2). Rows of subpixels are arranged on the upper and lower sides, respectively.

In the second embodiment of the present invention, subpixel columns are arranged on both sides of the 3i-th data line (i is a positive integer). In the second embodiment of the present invention, unlike the first embodiment, the subpixels are driven by sequentially supplying two non-overlapping gate signals to adjacent gate lines. At this time, since a pair of gate lines drive three rows of subpixels, the horizontal period of the gate signal is 3H/2. In other words, assuming that the horizontal period of the gate signal supplied to each of the 3 rows of subpixels is 1H, a total of 3H of gate signals must be supplied sequentially, but since there are two gate lines (GL) corresponding to the 3 rows of subpixels, each gate The horizontal period of the gate signal supplied to the line (GL) is 3H/2.

Accordingly, in the second embodiment of the present invention, the horizontal period of the gate signal supplied to the gate line GL is increased to 1.5H.

In addition, in the second embodiment of the present invention, a pair of gate lines are connected to subpixels arranged in three rows of subpixels, so the subpixels in the upper area and the subpixels in the lower area are connected with one gate line as the center. An area exists.

Additionally, among the common electrodes shown in the figure, the third common electrode 410c may be formed in a structure in which three rows of vertical sub-pixels are integrally formed or connected.

In particular, in the second embodiment of the present invention, a cross sub-pixel exists, and FIGS. 13 and 14 show embodiments of configuring the cross sub-pixel. Referring to FIG. 13, the second contact portion CP2 is disposed in the thin film transistor area of the second subpixel SP2, and correspondingly, the adjacent data line (3i+2th data line: (3i+2)th) The first contact portion CP1 is disposed on the front end data line (3i+1th data line: (3i+1)th DL) of the DL). The first subpixel SP1 and the second subpixel SP2 are subpixels arranged in the j+1th subpixel column and the j+2th subpixel column, respectively, described in FIG. 11.

The first contact part CP1 and the second contact part CP2 are electrically connected by the first contact connection part 1300. Accordingly, the second subpixel SP2 receives a data voltage from a data line (3i+1th data line: (3i+1)th DL) that supplies polarity data voltages (+, -) to adjacent subpixel columns.

In addition, a fourth contact portion CP4 is disposed in the first subpixel SP1 area, and a 3i+2th data line ((3i+2)th DL that supplies polarity data voltages to adjacent subpixel columns to correspond to the fourth contact portion CP4). ) is disposed in the third contact portion CP3. The third contact part CP3 and the fourth contact part CP4 are electrically connected by the second contact connection part 1330. Accordingly, the first sub-pixel (SP') receives a data voltage from a data line (3i+2th data line: (3i+2)th DL) that supplies polarity data voltages (+, -) to adjacent sub-pixel columns. .

14 , unlike FIG. 13 , the first sub-pixel SP1 implements a cross sub-pixel by extending a portion of the pixel electrode and connecting it to a thin film transistor of the second sub-pixel SP2 disposed in an adjacent sub-pixel column. As shown in the figure, it can be seen that the first connection pattern 1440 extending from the pixel electrode of the first sub-pixel (SP1) is connected to the drain electrode of the thin film transistor of the second sub-pixel (SP2).

In the same way, the second connection pattern 1400 extending the pixel electrode disposed in the second sub-pixel SP2 can be seen to be connected to the drain electrode of the thin film transistor in the adjacent first sub-pixel SP1 region.

With reference to FIGS. 15 to 17, the cut surfaces of the IV-IV' line, V-V' line, and VI-VI' line are as follows.

Here, since the same reference numerals as those in FIGS. 5 to 7 indicate the same components, the description below will focus on distinguishing features.

Referring to FIG. 15, the drain electrode 517b in the second sub-pixel (SP2) area of FIG. 13 is disposed on the first storage electrode 420a with the gate insulating layer 502 interposed therebetween, and the protective layer 520 ) The first pixel electrode 400a and the drain electrode 517b are electrically connected through the fifth contact hole C5 formed in ).

Additionally, referring to FIG. 16, in the sixth contact hole C6 area, the first contact portion CP1 and the 3i+1th data line ((3i+1)th DL) are disposed on the gate insulating layer 502. do. The first contact portion CP2 is formed extending from the 3i+1th data line ((3i+1)th DL) and is connected to the first connection contact through the sixth contact hole C6 formed in the cone protection layer 520. Part 1300 is connected to the first contact part CP1.

Also, referring to FIG. 17, in the intersection area of the second connection contact part 1330 and the 3i+1th data line ((3i+1)th DL), the first connection contact part 1300 and the second connection contact part It can be seen that 1330 is disposed on the protective layer 520 because it is formed simultaneously when the pixel electrode and the common electrode are formed.

Figure 18 is a diagram comparing gate signals supplied in the second embodiment of the present invention and the comparative example. Figure 19 is a diagram showing the amount of charge charged to the subpixels of the second embodiment of the present invention and the comparative example.

Referring to Figures 18 and 19, in the second embodiment of the present invention, gate signals are simultaneously supplied sequentially to a pair of adjacent gate lines among gate lines arranged on the display panel. At this time, since the gate signals supplied to a pair of gate lines drive three rows of subpixels, the width of each gate signal is 1.5H, which is increased from 1H.

Therefore, the subpixels arranged on the display panel are driven in units of three rows, and each of the six subpixels (SP) is operated by two gate signals based on the rendering pixel (RP) defined in the second embodiment of the present invention. do. Similar to the first embodiment of the present invention, since the horizontal period of the gate signal increases, the polarity data voltages (+, -) supplied to each sub-pixel can be sufficiently charged in the sub-pixel area.

As shown in FIG. 19, in the prior art (comparative example), the gate signal width is 1H, so when the high-resolution display device and the frame rate frequency increase, the turn-on period of the thin film transistor (TFT) disposed in each sub-pixel is short, resulting in polarity. The data voltage (+, -) is only charged below the normal charge level and is not charged any further (X1).

However, in the second embodiment of the present invention, the horizontal period of the gate signal increases by 1.5 times, so the polarity data voltage (+, -) charged in each sub-pixel is charged to more than the normal charge amount (X3)

As such, in the second embodiment of the present invention, even if the display panel becomes larger or higher resolution, each sub-pixel is sufficiently charged with the polarity data voltage, so polarity voltage offset by the inversion driving method is smoothly performed. Because of this, the present invention has the effect of eliminating flicker defects and afterimage defects even when the display panel becomes larger or higher resolution.

Additionally, the second embodiment of the present invention has the effect of increasing the aperture ratio of each sub-pixel area by reducing the number of data lines compared to the first embodiment.

Figure 20 is a diagram showing the sub-pixel arrangement of the display panel according to the third embodiment of the present invention. Figure 21 is a diagram showing the sub-pixel arrangement of the display panel according to the fourth embodiment of the present invention.

In order to apply the vertical 2-dot inversion method described in FIG. 2E, FIG. 20 has the same structure as the subpixel arrangement of FIG. 11, but the connection relationship between the data lines and each subpixel and the position of the cross subpixel are changed.

As shown in the figure, the subpixels arranged on the display panel 110 have opposite polarities in units of two subpixels in the column direction of the subpixels, and each subpixel has a polarity in the first frame and a polarity in the second frame. The polarities in the frame are reversed.

In order to apply the horizontal 2-dot inversion method described in FIG. 2F, FIG. 21 has the same structure as the subpixel arrangement of FIG. 11, but the connection relationship between the data lines and each subpixel and the position of the cross subpixel are changed.

As shown in the figure, the subpixels arranged in the display panel 110 have opposite polarities in the two subpixel units in the row direction of the subpixels, and each subpixel has a polarity in the first frame and a polarity in the second frame. The polarities in the frame are reversed.

As such, in the second embodiment of the present invention, since the horizontal period of the gate signal increases to 1.5H, the residual polarity voltage in each subpixel area can be canceled even when applied to various inversion driving methods. Therefore, the second embodiment of the present invention has the effect of reducing flicker defects and afterimage defects.

Additionally, the second embodiment of the present invention has the effect of increasing the transmittance of each sub-pixel area because the number of data lines is reduced compared to the first embodiment of the present invention.

Figure 22 is a diagram showing the operation of subpixels of the display panel according to the first embodiment of the present invention. Figure 23 is a flowchart showing a method of driving a display device according to the first embodiment of the present invention.

The driving method according to the first embodiment of the present invention includes the step of sequentially supplying gate signals to a pair of adjacent gate lines among the gate lines arranged on the display panel (S2300), and the pair of gate signals are each other's gate signals. It includes a step of supplying the same width and overlapping (S2301) and a step of driving the subpixels in units of rows of a pair of subpixels among the subpixels of the display panel (S2302).

In particular, in the first embodiment of the present invention, twice the horizontal period (H) of the gate signals is overlapped and supplied in units of 2 rows among the rows of subpixels, so that the 2nd row of subpixels corresponding to a pair of gate lines is supplied. The polarity data voltages (+, -) of the arranged sub-pixels can be sufficiently charged.

As shown in FIG. 22, in the first embodiment of the present invention, subpixels are driven in units of 2 rows. Even if the pixel placed on the display panel is composed of a first pixel (P1) composed of three subpixels or a second pixel (P2) composed of four subpixels, all subpixels arranged in the second row of subpixels They operate by a pair of gate signals with a horizontal period of 2H.

Figures 24 and 25 are diagrams showing the operation of subpixels of a display panel according to second to fourth embodiments of the present invention. Figure 26 is a flowchart showing a method of driving a display device according to second to fourth embodiments of the present invention.

The driving method according to the second embodiment of the present invention includes sequentially supplying gate signals from subpixels having the structures of FIGS. 11, 20, and 21 to gate lines arranged on the display panel (S2600), and It includes the step of dividing and driving subpixels of a rendering pixel corresponding to a pair of gate lines (S2601).

More specifically, in order to drive three rows of subpixels in units of a pair of adjacent gate lines, the horizontal period of each pair of gate signals is 1.5H. Unlike the first embodiment of the present invention, in the second embodiment of the present invention, a pair of gate signals do not overlap each other. Instead, a pair of gate signals divides and drives six sub-pixels based on the rendering pixel (RP). That is, the gate signals supplied to a pair of gate lines are divided into half and half of the three rows of subpixels and driven.

In particular, in the second embodiment of the present invention, the horizontal period (H) of the gate signals is increased by 1.5 times in units of 3 rows among the rows of subpixels, so that the sub-pixels arranged in the 3rd row of subpixels corresponding to a pair of gate lines The pixels can sufficiently charge the polarity data voltage (+, -).

As shown in Figures 24 and 25, the rendering pixels (RP) arranged in three rows of subpixels include four subpixels arranged in the first subpixel row and two subpixels arranged in the second subpixel row. 1 It is driven by the gate signal supplied to the gate line (GL1). Additionally, two subpixels arranged in the second subpixel row and four subpixels arranged in the third subpixel row are driven by the gate signal supplied to the second gate line GL2.

As such, the second embodiment of the present invention has the effect of ensuring that the polarity voltage of each sub-pixel is sufficiently offset even when the display panel is enlarged or has a higher resolution.

Additionally, in the second embodiment of the present invention, the transmittance of each sub-pixel is improved by reducing the number of gate lines and data lines disposed on the display panel.

Additionally, in the second embodiment of the present invention, the subpixels of the display panel are defined in units of rendering pixels and the subpixels within each rendering pixel are driven separately, thereby eliminating flicker defects and afterimage defects.

Exemplary embodiments of the present invention may be described as follows.

A display device according to an embodiment of the present invention includes a substrate having a display area; m*n pixels including a sub-pixels provided in the display area (a is 3 or 4, m and n are positive integers); 2(a*m)+2 data lines on the substrate; n gate lines crossing the data line on the substrate; n rows of subpixels are defined by each of the n gate lines, and n/2 common lines are arranged for each pair of consecutive subpixel rows while intersecting the data lines; and a pixel electrode and a common electrode disposed in each sub-pixel area.

In a display device according to another embodiment of the present invention, each subpixel column is arranged in each 2i-th and 2i+1-th data line of a pair of 2(a*m)+2 data lines, so that the subpixels in the a*m column are (i is a positive integer), and among the subpixels of the a*m column, the subpixels arranged in the jth (j is a positive integer) subpixel column are the 2ith data line and the 2i+1th data line (where i= It can be connected alternately with j).

In a display device according to another embodiment of the present invention, a common line may be commonly connected to common electrodes arranged in two rows of subpixels.

A display device according to another embodiment of the present invention may include a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel.

A display device according to another embodiment of the present invention consists of four subpixels, each of which has two subpixels: a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. It can be.

In a display device according to another embodiment of the present invention, a pair of data lines may be disposed between each row of subpixels, and an auxiliary pattern may be disposed for each subpixel between the pair of data lines.

In a display device according to another embodiment of the present invention, the auxiliary pattern may be connected to a common line in units of 2 rows among each subpixel row.

A display device according to another embodiment of the present invention includes a substrate having a display area; m*n pixels including 4 sub-pixels provided in the display area (m and n are positive integers); 6m+2 data lines on the substrate; 2k gate lines crossing the data lines on the substrate (where k is a positive integer and the k value is when n is 3*k); k common lines crossing the data lines on the substrate; Three rows of subpixels are arranged between the 2k gate lines and the k common lines to define n rows of subpixels, and may include a pixel electrode and a common electrode disposed in each subpixel area.

A display device according to another embodiment of the present invention has 4 subpixel columns arranged between the adjacent 3i-1th data line and the 3i+1th data line centered on the 3ith data line among the 6m+2 data lines. The subpixel in the *m column is defined (i is a positive integer), and a rendering pixel consisting of 12 subpixels is defined by the subpixel in the 4*m column and the subpixel in the 3*k row among the subpixels in the n row. , each rendering pixel may include a cross sub-pixel in which at least one sub-pixel is connected to a data line defining an adjacent sub-pixel column.

In a display device according to another embodiment of the present invention, a common line may be commonly connected to common electrodes arranged in three rows of subpixels.

The display device according to another embodiment of the present invention may include a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel, and a white (W) subpixel.

A display device according to another embodiment of the present invention consists of four subpixels, each of which has two subpixels: a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. It can be.

In a display device according to another embodiment of the present invention, auxiliary patterns may be disposed on both sides of each subpixel between each subpixel column.

In a display device according to another embodiment of the present invention, the auxiliary pattern may be connected to a common line in units of three rows among each subpixel row.

In a display device according to another embodiment of the present invention, two cross sub-pixels may be arranged for each rendering pixel.

In a display device according to another embodiment of the present invention, the cross sub-pixel may be connected to the drain electrode of the thin film transistor disposed in the sub-pixel adjacent to the connection pattern extending from the pixel electrode.

In the display device according to another embodiment of the present invention, the cross sub-pixel may be formed by arranging contact parts on each data line that supplies data voltage to the source electrode of the thin film transistor and the adjacent sub-pixel, and connecting them by a contact connection part. there is.

A display device driving method according to another embodiment of the present invention includes m*n pixels (m and n are positive integers) including 4 sub-pixels provided in the display area, and 6m+2 pixels on the substrate. A data line, 2k gate lines crossing the data line on the substrate (where k is a positive integer and n is 3*k, the k value), k crossing the data line on the substrate A common line, 3 rows of sub-pixels are arranged between the 2k gate lines and the k common lines to define n rows of sub-pixels, and includes a pixel electrode and a common electrode arranged in each sub-pixel area, Among the 6m+2 data lines, a subpixel column is placed between the adjacent 3i-1th data line and the 3i+1th data line centered on the 3ith data line, defining a 4*m column of subpixels (i is a positive number). ), a rendering pixel composed of 12 subpixels is defined by the subpixels in the 4*m column and the subpixels in the 3*k row among the subpixels in the n row, and each rendering pixel has at least one subpixel. may be a method of driving a display device including a cross sub-pixel connected to a data line defining an adjacent sub-pixel column.

A method of driving a display device according to another embodiment of the present invention includes sequentially supplying a pair of gate signals to a pair of adjacent gate lines among 2k gate lines; and separately driving sub-pixels arranged in the rendering pixel using a pair of gate signals.

In a method of driving a display device according to another embodiment of the present invention, the 12 sub-pixels arranged in the rendering pixel can be divided and driven in units of 6 sub-pixels.

In a method of driving a display device according to another embodiment of the present invention, an image input to the display device may have a frame rate frequency of 120 Hz or more.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: display device
110: display panel
120: Gate driver
130: data driving unit
150: controller
400a: first pixel electrode
400b: second pixel electrode
410a: first common electrode
410b: second common electrode
410c: Third common electrode
420a: first storage electrode
420b: second storage electrode
430a, 430b: Auxiliary pattern

Claims (18)

A substrate having a display area;
m*n pixels including a sub-pixels provided in the display area (a is 3 or 4, m and n are positive integers);
2(a*m)+2 data lines on the substrate;
n gate lines crossing the data line on the substrate;
n rows of subpixels are defined by each of the n gate lines, and n/2 common lines are arranged for each pair of consecutive subpixel rows while intersecting the data lines;
a pixel electrode and a common electrode disposed in each sub-pixel area; and
It includes a plurality of auxiliary patterns extending in a column direction between the sub-pixel columns,
Among the 2(a*m)+2 data lines, each subpixel column is arranged between the 2i-th and 2i+1-th data lines of the pair, thereby defining the subpixels of the a*m column (i is a positive integer). ,
Among the subpixels of the a*m column, the subpixels arranged in the jth (j is a positive integer) subpixel column are alternately connected to the 2ith data line and the 2i+1th data line (where i=j),
A pair of data lines is disposed between the subpixel columns, and each of the plurality of auxiliary patterns is disposed between the pair of data lines,
Some of the plurality of auxiliary patterns extend from the common line and are electrically connected to the common electrode,
The remaining of the plurality of auxiliary patterns are arranged to be spaced apart from the common line. According to claim 1,
A display device in which the common line is commonly connected to common electrodes of subpixels arranged in a corresponding pair of subpixel rows. According to claim 1,
The display device includes a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. According to claim 1,
The display device is comprised of four subpixels, each of which has two subpixels: a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. delete According to claim 1,
A display device wherein some of the plurality of auxiliary patterns are connected to a common line corresponding to the pair of consecutive subpixel rows and to common electrodes of subpixels disposed in the consecutive pair of subpixel rows. A substrate having a display area;
m*n pixels including 4 sub-pixels provided in the display area (m and n are positive integers);
6m+2 data lines on the substrate;
2k gate lines that intersect the data line on the substrate and are disposed 2 in each of the 3 rows of subpixels (where k is a positive integer and the k value is 3*k when n is 3*k);
l common lines that intersect the data lines on the substrate and are disposed in each of three rows of subpixels (where l is a positive integer and the l value when n is 3*l); and
N rows of subpixels are defined so that three rows of consecutive subpixels are arranged between the two gate lines and one common line, and each row includes a pixel electrode and a common electrode disposed in the subpixel area,
Among the 6m+2 data lines, a pair of subpixel columns are arranged between the adjacent 3i-1th data line and the 3i+1th data line centered on the 3ith data line, thereby defining a 4*m column of subpixels (i is a positive integer),
A rendering pixel consisting of 12 subpixels is defined by two consecutive pairs of subpixel columns and three consecutive subpixel rows among the subpixels in the 4*m column and the n row of subpixels, and arranged in each rendering pixel. A display device in which a pair of subpixel columns includes at least one cross subpixel connected to a data line arranged to define an adjacent pair of subpixel columns. According to clause 7,
A display device in which the common line is commonly connected to common electrodes of subpixels arranged in the third row of the corresponding subpixel. According to clause 7,
The display device includes a red (R) subpixel, a green (G) subpixel, a blue (B) subpixel, and a white (W) subpixel. According to clause 7,
The display device is comprised of four subpixels, each of which has two subpixels: a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. According to clause 7,
A display device in which a plurality of auxiliary patterns are disposed between the subpixel columns in each subpixel row unit to connect the common line to a common electrode disposed in each subpixel. According to claim 11,
The auxiliary patterns are connected to a common line corresponding to the three consecutive sub-pixel rows and to common electrodes of sub-pixels arranged in the three consecutive sub-pixel rows. According to clause 7,
A display device in which two cross sub-pixels are arranged for each rendering pixel. According to clause 7,
The cross sub-pixel is connected to a drain electrode of a thin film transistor of a sub-pixel disposed in an adjacent pair of sub-pixel columns by a connection pattern extending from the disposed pixel electrode. According to clause 7,
The cross sub-pixel is a display device formed by arranging contact parts on data lines arranged to define a pair of sub-pixel columns adjacent to the source electrode of the arranged thin film transistor, and connecting them by a contact connection part. m*n pixels including 4 sub-pixels (m and n are positive integers) provided in the display area, the sub-pixels include 6m+2 data lines, intersecting the data lines and 3 rows of sub-pixels 2k gate lines, 2 of which are arranged in each row (where k is a positive integer and n is 3*k, the k value), l common lines that intersect the data lines and are arranged 1 in every 3 rows of subpixels (However, l is a positive integer and the l value when n is 3*l), and n rows of subpixels are arranged so that 3 rows of consecutive subpixels are arranged between two gate lines and one common line. And among the 6m+2 data lines, a pair of subpixel columns are arranged between the adjacent 3i-1th data line and the 3i+1th data line centered on the 3ith data line, so that the subpixels in the 4*m column (i is a positive In a method of driving a display device in which a pixel electrode and a common electrode are disposed in each sub-pixel area, an integer of ) is defined, respectively,
Define a rendering pixel composed of 12 subpixels by 2 consecutive pairs of subpixel columns and 3 consecutive subpixel rows among the subpixels in the 4*m column and the subpixel in the n row,
sequentially supplying a pair of gate signals to a pair of adjacent gate lines among the 2k gate lines; and
A method of driving a display device including the step of separately driving sub-pixels arranged in the rendering pixel using the pair of gate signals. The method of claim 16, wherein the 12 sub-pixels arranged in the rendering pixel are divided and driven in units of 6 sub-pixels. The method of claim 16, wherein the image input to the display device has a frame rate of 120 Hz or more.

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