KR102673103B1 - Scan driver, display device using the same, method for controlling the same thereof - Google Patents

Abstract

The present invention relates to a driving circuit for a display. In the scan driver including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage, each stage has a boot When a dropped voltage is applied through the output unit that is connected to the Q node where bootstrapping is applied and supplies voltage to the display device, and the A node that is connected to the Q node and formed in a boosted-down structure, Q A voltage control unit that prevents multiple outputs of the output unit by inducing a voltage drop in the node, a pull-down unit that discharges the Q node and output unit in all sections except the output section of the Q node, and a series connected to the Q node. It includes a deterioration prevention unit composed of a plurality of transistors that distribute voltage in (series).

Description

Scan driver, display device using the scan driver, and control method of the scan driver {Scan driver, display device using the same, method for controlling the same thereof}

The present invention relates to a driving circuit for a display, a scan driver for driving a display, a display device utilizing the same, and a method for controlling such a scan driver.

The display device includes a data driving circuit that supplies a data signal to the data lines of the pixel array, a scan driving circuit that sequentially supplies scan pulses synchronized with the data signal to the scan lines of the pixel array, It includes a timing controller that controls the data driving circuit and the scan driving circuit. Each of the pixels may include a thin film transistor (TFT) that supplies the voltage of the data line to the pixel electrode in response to the scan pulse. The scan pulse swings between the gate on voltage (gate high voltage, VGH) and the gate off voltage (gate low voltage, VGL). The gate-on voltage (VGH) is set to a voltage higher than the threshold voltage (VTH) of the pixel TFT, and the gate-off voltage (VGH) is set to a voltage lower than the threshold voltage (VTH) of the pixel TFT.

Meanwhile, it has high mobility and low production costs, can be applied to large-area display panels due to high uniformity between elements compared to LTPS TFT, and has low off-current characteristics, enabling low power consumption. Recently, research on oxide TFTs is actively underway.

The following prior art literature introduces scan drivers for oxide TFTs, but the development of new scan drivers taking into account the structure and characteristics of oxide TFTs to ensure the stability of the driving circuit is required.

Korean Patent Publication No. 2012-0078557, “Scan Driver”

The technical problem to be solved by the present invention is to overcome the weakness of the conventional scan driver for display driving in which continuous bias stress is applied by DC type driving of the pull-down unit, and to overcome the weakness of the conventional scan driver for display driving, which is the depletion mode operation of the oxide TFT. It solves the problem of increased power consumption due to leakage current occurring in the TFT with negative threshold voltage, and temporarily high ripple voltage due to the parasitic capacitance of the pull-up transistor and clock signal. This solves the problem of multiple outputs occurring at the output node, and prevents TFT deterioration due to an increase in drain-source voltage when a bootstrapping voltage is applied.

In order to solve the above technical problem, a scan driver includes a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage according to an embodiment of the present invention. Each of the stages includes: an output unit connected to a Q node to which bootstrapping is applied and supplying voltage to the display device; a voltage control unit that prevents multiple outputs of the output unit by inducing a voltage drop in the Q node when a dropped voltage is applied through the A node connected to the Q node and formed in a boosted-down structure; a pull-down unit that discharges the Q node and the output unit in sections other than the output section of the Q node; and a deterioration prevention unit consisting of a plurality of transistors connected to the Q node and distributing voltage in series.

In the scan driver according to one embodiment, the voltage control unit applies a voltage lowered from a high voltage to a low voltage to the A node, and through a coupling effect using a capacitor connected to the A node. By inducing the voltage of the Q node to drop to the low voltage, multiple outputs of the scan output node and the carry output node of the output unit can be prevented.

In the scan driver according to one embodiment, the pull-down unit may discharge each of the Q node, the scan output node of the output unit, and the carry output node for 1/3 of a clock cycle.

In the scan driver according to one embodiment, the degradation prevention unit may reduce drain-source voltage by distributing voltage through a transistor connected to the Q node and a series two transistor (STT) structure.

In order to solve the above technical problem, a display device according to another embodiment of the present invention includes a display panel composed of an oxide thin film transistor (TFT); And a scan driver corresponding to a depletion mode operation according to the normally on state of the oxide TFT, wherein the scan driver receives the output signal of the previous stage. It includes a plurality of stages that sequentially generate output signals by passing them to the next stage, each stage comprising: an output unit connected to a Q node to which bootstrapping is applied and supplying a voltage to the display device; a voltage control unit that prevents multiple outputs of the output unit by inducing a voltage drop in the Q node when a voltage drop is applied through the A node formed in a boosted-down structure; a pull-down unit that discharges the Q node and the output unit in sections other than the output section of the Q node; and a deterioration prevention unit consisting of a plurality of transistors connected to the Q node and distributing voltage in series.

In order to solve the above technical problem, a scan driver includes a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage according to another embodiment of the present invention. The control method includes, through each of the stages, (a) pre-charging the Q node connected to the output unit that drives the first transistor to supply voltage to the display device; (b) outputting a high voltage from the output unit by generating bootstrapping through a first capacitor connected to the output unit, and connecting the Q node to distribute the voltage in series Reducing the drain-source voltage of each transistor through a deterioration prevention unit composed of a plurality of transistors; (c) discharging the scan output node and carry output node of the output unit through a pull-up transistor of the output unit; (d) Through a pull-down unit that discharges the Q node and the output unit in the remaining sections excluding the output section of the Q node, the scan output node of the Q node and the output unit is first low (low). ) voltage, discharging the carry output node of the output unit to a second low voltage; and (e) inducing the voltage of the Q node to the second low voltage when the A node connected to the Q node and formed in a boosted-down structure is discharged to the second low voltage. Includes.

Embodiments of the present invention prevent multiple outputs through a boosted-down structure, prevent device deterioration by discharging by adjusting the duty ratio of the pull-down operation, and prevent device deterioration by securing a low drain-source voltage. It can contribute to improving product yield by responding to depletion mode operation.

Figure 1 is a diagram illustrating a scan driver circuit to which a bootstrapping technique is applied and its timing diagram.
Figure 2 is a diagram illustrating a scan driver circuit according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a timing diagram of the scan driver circuit of FIG. 2 according to an embodiment of the present invention.
Figure 4 is a flowchart showing a control method of a scan driver circuit according to another embodiment of the present invention.
5 to 9 are diagrams showing the sequential operation of the circuit according to each step of the control method of the scan driver circuit with timing diagrams.
10 to 12 are graphs illustrating simulation results of a scan driver circuit according to embodiments of the present invention.

Before describing the embodiments of the present invention in detail, let us briefly introduce the technical characteristics and weaknesses of the scan driver circuit that can be used in the display driving technology field in which the present invention is used.

The scan driver circuit used to drive the display applies a bootstrapping technique to the pull-up transistor to supply a stable voltage to each pixel, increasing the gate voltage of the TFT so that a stable voltage can be transmitted to the output terminal. It has a basic structure. Here, the node to which the bootstrapping technique is applied is named Q node. In general, the Q node in a scan driver circuit does not operate except during the pre-charge and bootstrapping periods for stable pixel driving. When the Q node operates in sections other than the output section, the clock voltage can be applied to the output node through a pull-up transistor, so the scan driver circuit has a pull-up voltage to discharge the Q node and the output node. Additional pull-down units can be designed.

This pull-down unit is always on to discharge the Q node except for the pixel driving time, so it can be considered to be driven as a DC type. However, when driven in the DC type, continuous bias stress is applied to the pull-down unit, causing deterioration of the TFT. Additionally, when a bootstrapping voltage is applied to the Q node, the drain-source voltage of the TFT connected to the Q node becomes significantly higher. This leads to deterioration of the TFT, changes in electrical characteristics (shift in threshold voltage, reduction in on-state current, etc.) and directly affects the stability of the circuit.

Meanwhile, oxide TFT configures the channel layer by controlling the ratio of indium-gallium-zinc-oxygen (In-Ga-Zn-O, IGZO), and the ratio of indium (In) can be increased to increase electron mobility. . However, as the proportion of indium increases, oxygen vacancy increases, causing the threshold voltage of the oxide TFT to have a negative value, so that the transistor channel is formed without applying a bias to the gate voltage. state, and this is called depletion mode operation. Therefore, a scan driver structure that can respond to the depletion mode operation of the TFT is required.

Figure 1 is a diagram illustrating a scan driver circuit to which a bootstrapping technique is applied and its timing diagram. Stable output is achieved by applying a bootstrapping technique using a clock (CLK) to the Q node, and then through a pull-down unit. We attempted to prevent multiple outputs by discharging the output node at 100% duty. However, the pull-down unit is driven in DC type to discharge the Q node and VOUT n and is always turned on, so continuous bias stress is applied to the pull-down unit, resulting in deterioration of the TFT.

In addition, the scan driver circuit of Figure 1 does not consider the depletion mode operation of the oxide TFT, which has the disadvantage of increasing power consumption due to leakage current occurring in the TFT with a negative threshold voltage, and the parasitic capacitance of the pull-up transistor and clock There is a risk that a high ripple voltage will momentarily occur at the Q node due to the (CLK) signal, causing multiple outputs at the output node (VOUT n). In addition, during the bootstrapping period, a fairly high drain-source voltage is applied to transistors T1, T2, and T3 connected to the Q node, which may cause device deterioration.

Therefore, the embodiments of the present invention described below were devised to overcome the above technical limitations, and respond to depletion mode operation to solve the problem of increased power consumption due to leakage current due to normally-on operation of the TFT. I would like to propose a scan driver circuit that makes this possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, detailed descriptions of known functions or configurations that may obscure the gist of the present invention are omitted in the following description and attached drawings. In addition, throughout the specification, 'including' a certain component does not mean excluding other components unless specifically stated to the contrary, but rather means that other components may be further included.

Additionally, terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another component. For example, a first component may be named a second component, and similarly, the second component may also be named a first component without departing from the scope of the present invention.

The terms used in the present invention are only used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “comprise” are intended to designate the presence of the described features, numbers, steps, operations, components, parts, or combinations thereof, but are not intended to indicate the presence of one or more other features or It should be understood that this does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless specifically defined differently, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless clearly defined in the present application, should not be interpreted as having an ideal or excessively formal meaning. .

Figure 2 is a diagram illustrating a scan driver circuit according to an embodiment of the present invention. The scan driver includes a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage. Here, the structure of a single stage that can be applied to each stage is shown. The scan driver circuit consists of 14 transistors and 2 capacitors (14T2C). The scan output to each pixel is the G[n] node, and CR[n] is used as an input signal to each scan driver stage. The meaning of the nodes constituting the circuit of FIG. 2 is shown in Table 1 below.

FIG. 3 is a diagram illustrating a timing diagram of the scan driver circuit of FIG. 2 according to an embodiment of the present invention. A total of 6 phases of clock signals are used, and is illustrated as an input signal of the scan driver circuit of FIG. 2. The meaning of each node is shown in Table 2 below.

2 and 3, the scan driver structure proposed in this embodiment has multiple outputs due to parasitic capacitors, electrical deterioration of the pull-down unit, and electrical deterioration of the transistor due to high drain-source voltage, as pointed out earlier. It was designed to solve the problem of circuit malfunctions, including boosted-down structure, duty ratio adjustment of the pull-down unit, and series-two-transistor (STT). structure was introduced.

The output unit 10 is connected to a Q node to which bootstrapping is applied and supplies voltage to the display device.

The voltage control unit 20 induces a voltage drop in the Q node when a dropped voltage is applied through the A node connected to the Q node and formed in a boosted-down structure, thereby generating the output unit 10. This is a configuration that prevents multiple output. More specifically, the voltage control unit 20 applies a voltage lowered from a high voltage to a low voltage to the A node, and connects the Q node through a coupling effect using a capacitor connected to the A node. By inducing the voltage of to drop to the low voltage, multiple outputs of the scan output node and the carry output node of the output unit 10 can be prevented. Here, the voltage control unit 20 controls the parasitic capacitor of the pull-up transistor included in the output unit 10 and the ripple voltage of the Q node through the voltage drop of the Q node. It is prevented.

Referring to FIG. 2, when the CLK2L signal is applied from the high voltage VGH to the second low voltage VGL2 to the A node A[n] through the boosted-down structure of the voltage control unit 20, the capacitor of the voltage control unit 20 Through the coupling effect of (C2), the voltage of the Q node Q[n] goes down to the second low voltage VGL2. At this time, the high parasitic capacitor of the pull-up transistors (T3, T4) of the output unit 10 and the ripple voltage of the Q node Q[n] due to CLK3 and CLK3L are prevented, thereby preventing the scan output node G[n] and the carry output node CR. Since multiple outputs of [n] do not occur, reliability of the circuit can be secured.

The pull-down unit 30 is configured to discharge the Q node and the output unit 10 in sections other than the output section of the Q node. More specifically, the pull-down unit 30 may discharge each of the Q node, the scan output node and the carry output node of the output unit 10 for 1/3 of the clock cycle. At this time, it may further include a D node connected to the A node through a pull-down transistor to form an inverter structure 50. The pull-down unit 30 may be connected to the D node through the D node. The A node can be discharged for 2/3 of the clock cycle, and the Q node can be discharged through the A node.

Referring to FIG. 2, the pull-down unit 30 includes transistors 32 (T6, T7) included inside the output unit 10 and transistors 31 (T6, T7) formed outside the output unit 10. T5a, T5b). To prevent deterioration of the pull-down unit 30, the Q node Q[n], scan output node G[n], and carry output node CR[n] are discharged for a clock (CLK) cycle (duty ratio) of 33.3%, respectively. do. In particular, the Q node Q[n] is discharged through the A node A[n], and the A node A[n] is discharged through the D node D[n] and the pull-down transistor T9 for 66.6% of the clock cycle. do. Therefore, the reliability of the Q node Q[n], scan output node G[n], and carry output node CR[n] can be secured at once by preventing deterioration of each pull-down unit.

The deterioration prevention unit 40 is composed of a plurality of transistors that are connected to the Q node and distribute voltage in series. More specifically, the deterioration prevention unit 40 reduces the drain-source voltage by distributing the voltage through the transistor 41 and the series two transistor (STT) structure 42 connected to the Q node. You can do it. At this time, the transistor 41 connected to the Q node is connected between the Q node and a pre-charging transistor to reduce the drain-source voltage of the pre-charging transistor.

It was previously pointed out that in the scan driver circuit illustrated in FIG. 1, a fairly high drain-source voltage was applied to transistors T1, T2, and T3 during the bootstrapping period, and that this could cause device deterioration during long-term operation, resulting in circuit malfunction. . Therefore, in Figure 2 proposed by this embodiment, the drain-source voltage of the device is connected to the Q node Q[n] through the transistor 41 (T2) and the series-to-transistor (T5a, T5b, T5c) structure 42. Device stability can be secured by applying a structure that lowers .

Meanwhile, the scan driver circuit according to the present embodiment described above can be applied to various types of TFTs (a-Si:H, Poly-Si TFT, Organic TFT, etc.), and can also be used as an oxide TFT-based scan driver circuit. You can. Therefore, a display device according to another embodiment of the present invention corresponds to a display panel composed of an oxide TFT (thin film transistor) and a depletion mode operation according to the normally on state of the oxide TFT. It may include a scan driver.

Here, the scan driver includes a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage, and each of the stages is an angle of the scan driver described above with reference to FIG. 2. Since it can be implemented using configuration, only the outline will be outlined here.

The output unit is connected to the Q node to which bootstrapping is applied and supplies voltage to the display device.

The voltage control unit is configured to prevent multiple outputs of the output unit by inducing a voltage drop in the Q node when a voltage drop is applied through the A node formed in a boosted-down structure. This voltage control unit applies a voltage dropped from a high voltage to a low voltage to the A node, and changes the voltage of the Q node to the low voltage through a coupling effect using a capacitor connected to the A node. and scan the output unit by preventing the parasitic capacitor of the pull-up transistor included in the output unit and the ripple voltage of the Q node through the voltage drop of the Q node. Multiple outputs of output nodes and carry output nodes can be prevented.

The pull-down unit is configured to discharge the Q node and the output unit in the remaining sections excluding the output section of the Q node. Here, each stage of the scan driver further includes a D node connected to the A node through a pull-down transistor to form an inverter structure, wherein the pull-down unit is the Q node and the scan output node of the output unit. and each of the carry output nodes can be discharged for 1/3 of the clock cycle, while the A node can be discharged for 2/3 of the clock cycle through the D node, and the Q node can be discharged through the A node.

The deterioration prevention unit is composed of a plurality of transistors that are connected to the Q node and distribute voltage in series. This deterioration prevention unit reduces the drain-source voltage by distributing voltage through a transistor connected to the Q node and a series-to-transistor (series two transistor, STT) structure, and the transistor connected to the Q node is connected to the Q node and It can be connected between pre-charging transistors to reduce the drain-source voltage of the pre-charging transistor.

Figure 4 is a flowchart showing a control method of a scan driver circuit according to another embodiment of the present invention, which includes a plurality of stages that sequentially generate output signals by transferring the output signal of the previous stage to the next stage. In the scan driver control method, a time-series process of controlling the scan driver circuit of FIG. 2 through each stage is shown. For this purpose, SmartSpice simulation based on oxide TFT was performed in parallel in the proposed scan driver circuit. The threshold voltage (VTH) of the model used is 2 V and the channel length is 5 μm. Additionally, CLK1(L) to CLK3(L), CR[n-1], and G[n-1] swing from -5 V to 28 V, and VGH, VGL1, and VGL2 swing from 28 V, -5V, and -13 V, respectively. has a voltage of In addition, FIGS. 5 to 9 are diagrams showing the sequential operation of the circuit according to each step of the control method of the scan driver circuit along with timing diagrams.

In step S410, the first transistor is driven to pre-charge the Q node connected to the output unit that supplies voltage to the display device. More specifically, first, upon application of a high voltage [VGH], the Q node connected to the output unit that drives the first transistor to supply voltage to the display device is pre-charged to [VGH-VTH] (VTH is the threshold voltage). do. Then, the first low voltage [VGL1] and the second low voltage [VGL2] (VGL1>VGL2) can be applied to the scan output node and the carry output node of the output unit, respectively, through the pull-up transistor of the output unit.

Referring to FIG. 5 showing the pre-charging section along with step S410, the carry output node CR[n-1] and the scan output node G[n-1] are connected to the pre-charging transistor (T1) through the high voltage [VGH]. Operate and charge the Q node Q[n] to [VGH-VTH]. At this time, the first low voltage [VGL1] and the second low voltage [VGL2] are applied to the scan output node G[n] and carry output node CR[n] through the pull-up transistors T3, T4, CLK3, and CLK3L signals of the output unit, respectively. This is approved. Meanwhile, the voltage of the A node A[n] is discharged to the first low voltage [VGL1] through the transistor T8 connected to the A node A[n].

In step S420, the output unit outputs a high voltage by generating bootstrapping through a first capacitor connected to the output unit, and is connected to the Q node to distribute the voltage in series. The drain-source voltage of each transistor is reduced through a deterioration prevention unit composed of a plurality of transistors. More specifically, the first transistor is turned off and the Q node is brought into a floating state to generate bootstrapping through the first capacitor connected to the output unit. At this time, by increasing the voltage of the Q node to [VGH-VTH]+[VGH-VGL1], the high voltage can be output from each of the scan output node and carry output node of the output unit through the pull-up transistor of the output unit. there is. Meanwhile, the transistor connected between the first transistor and the Q node may be turned off to reduce the drain-source voltage of the first transistor to [VGH-VTH-VGL1], and the series connected to the Q node may be reduced to [VGH-VTH-VGL1]. By distributing voltage through a two-transistor (series two transistor, STT) structure, the drain-source voltage of each transistor can be reduced.

Referring to FIG. 6, which shows the output section of the bootstrapping and scan output node G[n] along with step S420, the drains of T1, T2, T5a, and T5b are connected through a plurality of transistors T2 and STT structures (T5a, T5b, and T5c). -An attempt was made to improve device deterioration by reducing the source voltage. More specifically, the pre-charging transistor T1 is turned off, the Q node Q[n] is floating, and bootstrapping occurs through the high voltage [VGH] of CLK3 and capacitor C1. Then, the voltage at Q node Q[n] increases to the value [VGH-VTH]+[VGH-VGL1], thereby increasing scan output node G[n] and carry output node CR[n] through pull-up transistors T3 and T4. The output of high voltage [VGH] is achieved. At this time, transistor T2 is turned off because its gate-source voltage is less than the threshold voltage, so that the drain-source voltage (V _DS ) applied to pre-charging transistor T1 is significantly lowered to [VGH-VTH-VGL1]. do. In addition, the transistors T5a, T5b, and T5c of the deterioration prevention section are designed in a series-to-transistor structure, so when the voltage of transistor T5c is turned on, a high voltage [VGH] is applied to the node between transistors T5a and T5b. This lowers the drain-source voltage of each transistor T5a and T5b. Therefore, the stability of the device can be ensured by preventing electrical deterioration of the pre-charging transistor T1 and transistors T5a and T5b.

In step S430, the scan output node and carry output node of the output unit are discharged through the pull-up transistor of the output unit. More specifically, the floating state of the Q node is maintained and the voltage of the Q node is reduced to [VGH-VTH] by the coupling effect of the first capacitor. Additionally, the scan output node and the carry output node of the output unit may be discharged through the pull-up transistor of the output unit to which the first low voltage [VGL1] and the second low voltage [VGL2] are applied.

Referring to Figure 7, which shows the holding of the Q node Q[n] and the discharge section of the scan output node G[n] along with step S430, the Q node Q[n] is still floating, and CLK3 and the capacitor Due to the coupling effect of C1, the value drops back to [VGH-VTH]. At the same time, the CLK3 and CLK3L signals become the first low voltage [VGL1] and the second low voltage [VGL2], respectively, to the scan output node G[n] and carry output node CR[n] through the pull-up transistors T3 and T4 of the output section. is discharged.

In step S440, through a pull-down unit that discharges the Q node and the output unit in the remaining sections excluding the output section of the Q node, the scan output node of the Q node and the output unit is first low (low). ) voltage, discharging the carry output node of the output unit to a second low voltage. More specifically, a high voltage [VGH] is applied to the A node to operate the transistor included in the pull-down section, and the Q node is operated for 1/3 of the clock cycle through the transistor included in the pull-down section. 1 Can be discharged to low voltage [VGL1]. In addition, the A node is connected to the transistor included in the pull-down unit, and the second capacitor included in the boosted-down structure is connected between the A node and the Q node to provide [VGH to the second capacitor. -VGL1] voltage can be charged. Furthermore, the scan output node of the output unit is discharged to the first low voltage [VGL1] for 1/3 of the clock cycle, and the carry output node of the output unit is discharged to the second low voltage [VGL2] for 1/3 of the clock cycle, respectively. You can do it.

Referring to FIG. 8 showing the first section of discharge holding along with step S440, the CLK2L signal with high voltage [VGH] is applied to the A node A[n] through transistor T11, and transistor T5a of the pull-down part, T5b operates, and the voltage of Q node Q[n] is discharged to the first low voltage [VGL1] (33.3% duty ratio). Therefore, the A node A[n] becomes the high voltage [VGH], and the voltage stored in capacitor C2 becomes [VGH-VGL1]. At this time, the scan output node G[n] and the carry output node CR[n] are discharged to the first low voltage [VGL1] and the second low voltage [VGL2] through transistors T6 and T7, respectively (33.3% duty ratio). Through this, it is possible to prevent deterioration of the transistor elements T5a, T5b, T6, and T7 included in the pull-down part.

In step S450, when the A node connected to the Q node and formed in a boosted-down structure is discharged to the second low voltage, the voltage of the Q node is induced to the second low voltage. More specifically, a high voltage [VGH] is applied to the D node, which is connected to the A node through a pull-down transistor to form an inverter structure, to turn on the pull-down transistor, thereby reducing the voltage of the A node to a high voltage [ [VGH] can be discharged to the second low voltage [VGL2]. Then, according to the discharge of the A node, the voltage of the Q node, which is floating due to the coupling effect of the second capacitor included in the boosted-down structure, is lowered to a second low voltage lower than the first low voltage [VGL1]. It can be induced to descend to [VGL2]. Therefore, by reducing the parasitic capacitor of the pull-up transistor of the output unit and the ripple voltage of the Q node through the voltage drop of the Q node, multiple outputs of the scan output node and the carry output node of the output unit can be prevented. there is.

Referring to FIG. 9 showing the second section of discharge holding along with step S450, boosted-down completely lowers the Q node Q[n] to the second low voltage [VGL2] using the coupling effect of capacitor C2. By applying the structure, we attempted to prevent multiple outputs of the scan output node G[n] due to the parasitic capacitor of the pull-up transistor T3 of the output unit. First, a high voltage [VGH] is applied to the D node D[n] through CLK3L and CLK3 to turn on the pull-down transistor T9, and the voltage of the A node A[n] is reduced from the previous high voltage [VGH]. 2 Low voltage [VGL2] is applied. Accordingly, boosted-down occurs in the Q node Q[n], which is in a floating state, and is charged to a voltage lower than the first low voltage [VGL1]. At this time, the ripple voltage of the Q node Q[n] due to the parasitic capacitor (C _GDO ) of CLK3 and the pull-up transistor T3 is reduced, thereby preventing multiple outputs of the scan output node G[n].

10 to 12 are graphs illustrating simulation results of a scan driver circuit according to embodiments of the present invention.

Figure 10 is a simulation result of the Q node Q[n] and scan output node G[n] when the threshold voltage of all TFTs is 2.0V. It can be seen that the pre-charging and bootstrapping voltages at the nth Q[n] are 26 V and 56 V, respectively, and the G[n] output is maintained at a voltage of +28 V without voltage loss.

Figure 11 shows simulation results for A node A[n], scan output node G[n], and Q node Q[n] when the threshold voltage of all TFTs is 10.5V. It can be confirmed that despite the threshold voltage shift of +8.5 V, the G[n] output maintains a voltage of +28 V without voltage loss.

Figure 12 is a simulation waveform of the Q node Q[n] and scan output node G[n] of the scan driver circuit proposed by embodiments of the present invention when all TFTs operate in depletion mode and the threshold voltage is -3.5 V. . It can be confirmed that a voltage of +28V is output at G[n] without voltage loss despite a shift in the threshold voltage of -5.5V.

In scan driver circuits to which embodiments of the present invention are applied, multiple output phenomena, device deterioration, and high power consumption may cause a decrease in yield. According to the above-described embodiments of the present invention, multiple outputs are prevented through a boosted-down structure, deterioration of the device is prevented by discharging by adjusting the duty ratio of the pull-down operation, and low drain-source voltage is secured. This prevents device deterioration and can contribute to improving product yield by responding to depletion mode operation.

Furthermore, embodiments of the present invention design and embed a gate scan driver inside the AMOLED and AMLCD panel TFT substrate, thereby reducing costs by eliminating the driver IC, and improving yield by eliminating the driver IC attachment process during the module process. can contribute to

In the above, the present invention was examined focusing on its various embodiments. Those skilled in the art will understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative rather than a restrictive perspective. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the equivalent scope should be construed as being included in the present invention.

10: output unit 20: voltage control unit
30, 31, 32: Pull-down section 40, 41, 42: Deterioration prevention section
50: Inverter circuit

Claims (19)

In a scan driver including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage,
Each of the above stages is:
An output unit connected to a Q node to which bootstrapping is applied and supplies voltage to the display device;
a voltage control unit that prevents multiple outputs of the output unit by inducing a voltage drop in the Q node when a dropped voltage is applied through the A node connected to the Q node and formed in a boosted-down structure;
a pull-down unit that discharges the Q node and the output unit in sections other than the output section of the Q node; and
A scan driver comprising: a deterioration prevention unit composed of a plurality of transistors connected to the Q node and distributing voltage in series. According to claim 1,
The voltage control unit,
A voltage dropped from a high voltage to a low voltage is applied to the A node, and the voltage of the Q node is induced to drop to the low voltage through a coupling effect using a capacitor connected to the A node. A scan driver that prevents multiple outputs from the scan output node and carry output node of the output unit. According to claim 2,
The voltage control unit,
A scan driver that prevents a parasitic capacitor of a pull-up transistor included in the output unit and a ripple voltage of the Q node through a voltage drop of the Q node. According to claim 1,
The pull-down part,
A scan driver that discharges each of the Q node, the scan output node and the carry output node of the output unit for 1/3 of a clock cycle. According to claim 4,
It further includes a D node connected to the A node through a pull-down transistor to form an inverter structure,
The pull-down part,
A scan driver that discharges the A node through the D node for 2/3 of a clock cycle and discharges the Q node through the A node. According to claim 1,
The deterioration prevention unit,
A scan driver that reduces drain-source voltage by distributing voltage through a transistor connected to the Q node and a series-to-transistor (STT) structure. According to claim 6,
A transistor connected to the Q node is connected between the Q node and a pre-charging transistor to reduce the drain-source voltage of the pre-charging transistor. A display panel composed of an oxide TFT (thin film transistor); and
Includes a scan driver corresponding to depletion mode operation according to the normally on state of the oxide TFT,
The scan driver is,
It includes a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage, each of the stages comprising:
An output unit connected to a Q node to which bootstrapping is applied and supplies voltage to the display device;
a voltage control unit that prevents multiple outputs of the output unit by inducing a voltage drop in the Q node when a voltage drop is applied through the A node formed in a boosted-down structure;
a pull-down unit that discharges the Q node and the output unit in sections other than the output section of the Q node; and
A display device comprising: a deterioration prevention unit composed of a plurality of transistors connected to the Q node and distributing voltage in series. According to claim 8,
The voltage control unit,
A voltage dropped from a high voltage to a low voltage is applied to the A node, and the voltage of the Q node is induced to drop to the low voltage through a coupling effect using a capacitor connected to the A node. By preventing the parasitic capacitor of the pull-up transistor included in the output unit and the ripple voltage of the Q node through the voltage drop of the Q node, the scan output node and carry output of the output unit A display device that prevents multiple outputs from nodes. According to claim 8,
Each stage of the scan driver is:
It further includes a D node connected to the A node through a pull-down transistor to form an inverter structure,
The pull-down part,
The Q node, the scan output node of the output unit, and the carry output node are each discharged for 1/3 of the clock cycle, the A node is discharged through the D node for 2/3 of the clock cycle, and the A node is discharged through the A node. A display device that discharges the Q node. According to claim 8,
The deterioration prevention unit,
The drain-source voltage is reduced by distributing voltage through a transistor connected to the Q node and a series-to-transistor (series two transistor, STT) structure, and the transistor connected to the Q node is connected to the Q node and pre-charging (pre-charging). -charging) A display device connected between transistors to reduce the drain-source voltage of the pre-charging transistor. In the control method of a scan driver including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage,
Through each of the above stages,
(a) pre-charging the Q node connected to the output unit that supplies voltage to the display device by driving the first transistor;
(b) outputting a high voltage from the output unit by generating bootstrapping through a first capacitor connected to the output unit, and connecting the Q node to distribute the voltage in series Reducing the drain-source voltage of each transistor through a deterioration prevention unit composed of a plurality of transistors;
(c) discharging the scan output node and carry output node of the output unit through a pull-up transistor of the output unit;
(d) Through a pull-down unit that discharges the Q node and the output unit in the remaining sections excluding the output section of the Q node, the scan output node of the Q node and the output unit is first low (low). ) voltage, discharging the carry output node of the output unit to a second low voltage; and
(e) when the A node connected to the Q node and formed in a boosted-down structure is discharged to the second low voltage, inducing the voltage of the Q node to the second low voltage; The control method of the scan driver. According to claim 12,
In step (a),
(a1) Pre-charging the Q node connected to the output unit that supplies voltage to the display device by driving the first transistor according to the application of high voltage [VGH] to [VGH-VTH] (VTH is the threshold voltage) ; and
(a2) applying a first low voltage [VGL1] and a second low voltage [VGL2] (VGL1>VGL2) to the scan output node and the carry output node of the output unit, respectively, through the pull-up transistor of the output unit; Including, control method of scan driver. According to claim 12,
In step (b),
(b1) turning off the first transistor and inducing the Q node into a floating state to generate bootstrapping through a first capacitor connected to the output unit; and
(b2) increasing the voltage of the Q node to [VGH-VTH]+[VGH-VGL1] to output the high voltage at each of the scan output node and carry output node of the output unit through the pull-up transistor of the output unit. A control method of a scan driver, including steps. According to claim 14,
In step (b),
(b3) turning off the transistor connected between the first transistor and the Q node to reduce the drain-source voltage of the first transistor to [VGH-VTH-VGL1]; and
(b4) reducing the drain-source voltage of each transistor by distributing the voltage through a series two transistor (STT) structure connected to the Q node. According to claim 12,
In step (c),
(c1) maintaining the floating state of the Q node and reducing the voltage of the Q node to [VGH-VTH] by the coupling effect of the first capacitor; and
(c2) discharging the scan output node and the carry output node of the output unit through the pull-up transistor of the output unit to which the first low voltage [VGL1] and the second low voltage [VGL2] are applied, respectively. Scan driver control method. According to claim 12,
In step (d),
(d1) Applying a high voltage [VGH] to the A node to operate the transistor included in the pull-down part, and operating the Q node for 1/3 of the clock cycle through the transistor included in the pull-down part. 1 Discharging to low voltage [VGL1];
(d2) The A node is connected to the transistor included in the pull-down unit, and the second capacitor included in the boosted-down structure is connected between the A node and the Q node, so that the second capacitor [ charging the voltage of [VGH-VGL1]; and
(d3) setting the scan output node of the output unit to a first low voltage [VGL1] for 1/3 of the clock cycle, and the carry output node of the output unit to the second low voltage [VGL2] for 1/3 of the clock period, respectively. A method of controlling a scan driver, including the step of discharging. According to claim 12,
In step (e),
(e1) Applying a high voltage [VGH] to the D node connected to the A node through a pull-down transistor to form an inverter structure to turn on the pull-down transistor, thereby reducing the voltage of the A node to the high voltage [ discharging from [VGH] to a second low voltage [VGL2]; and
(e2) As the A node discharges, the voltage of the Q node, which is floating due to the coupling effect of the second capacitor included in the boosted-down structure, is lowered to a second low voltage lower than the first low voltage [VGL1]. A control method of a scan driver, including a step of inducing a descent to [VGL2]. According to claim 18,
In step (e),
(e3) preventing multiple outputs of the scan output node and carry output node of the output unit by reducing the parasitic capacitor of the pull-up transistor of the output unit and the ripple voltage of the Q node through the voltage drop of the Q node. , Control method of scan driver.