KR102671265B1 - Staircase structure and method of forming 3D memory device - Google Patents

Abstract

Embodiments related to a 3D memory device having a staircase structure and a manufacturing method thereof are disclosed. In one example, the 3D memory device includes a memory array structure and a staircase structure that laterally divides the memory array structure into a first memory array structure and a second memory array structure intermediate the memory array structure. The stairwell structure includes a first stairwell section and a bridge structure connecting the first memory array structure and the second memory array structure. The first stairwell zone comprises a first pair of stairwells opposite each other in a first side direction and at different depths. Each staircase includes a plurality of stairs. At least one staircase of the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through a bridge structure.

Description

Staircase structure and method of forming 3D memory device

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of manufacturing the same.

Planar memory cells are being scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms and manufacturing processes. However, as the feature size of memory cells reaches its lower limit, planar processes and manufacturing techniques become more challenging and more expensive. As a result, the memory density of planar memory cells reaches its upper limit.

3D memory architecture can solve the density limitations of planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals exchanged with the memory array.

Embodiments of three-dimensional memory devices with staircase structures and methods of forming the same are disclosed herein.

In one example, the 3D memory device includes a memory array structure and a staircase structure that laterally divides the memory array structure into a first memory array structure and a second memory array structure intermediate the memory array structure. The stairwell structure includes a first stairwell section and a bridge structure connecting the first memory array structure and the second memory array structure. The first stairwell zone comprises a first pair of stairwells facing each other in a first side direction and at different depths. Each staircase includes a plurality of stairs. At least one staircase of the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through a bridge structure.

In another example, a 3D memory device includes a memory array structure and a staircase structure that laterally divides the memory array structure into a first memory array structure and a second memory array structure midway therebetween. The stairwell structure includes a first stairwell section and a bridge structure connecting the first memory array structure and the second memory array structure. The first stairwell zone comprises a first stairwell comprising a plurality of divisions in a second lateral direction. Each section includes a plurality of steps in a first lateral direction perpendicular to the second lateral direction. A staircase in one of the compartments is vertically between two stairs in another of the compartments. At least one staircase of the first staircase is electrically connected to at least one of the first memory array structure and the second memory array structure through a bridge structure.

In another example, a method of forming a staircase structure of a three-dimensional memory device is disclosed. A stairwell zone mask is patterned including openings for the first stairwell zone and the second stairwell zone in the middle of a stacked structure comprising vertically interleaved first and second material layers. In each of the first and second stairwell zones, at least one pair of stairwells is formed opposite each other at the same depth in the first lateral direction, wherein a second lateral direction is perpendicular to the first lateral direction between the first and second stairwell zones. A bridge structure is formed. In each of the first and second stairwell zones, each stairwell of the at least one pair of stairwells is chopped to a different depth.

The accompanying drawings, which are incorporated into and form a part of this specification, illustrate embodiments of the present disclosure and, together with the detailed description, serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the disclosure. .
1 shows a schematic diagram of a 3D memory device with a staircase structure.
2 shows a schematic diagram of an example 3D memory device with a staircase structure according to some embodiments of the present disclosure.
3 is a top view of an example 3D memory device with a staircase structure according to some embodiments of the present disclosure.
4 shows a top front perspective view of an example stairwell structure of a 3D memory device according to some embodiments of the present disclosure.
5A-5F illustrate various example masks for forming example stairwell structures of a 3D memory device according to some embodiments of the present disclosure.
6A and 6B illustrate a manufacturing process for forming an example stairwell structure of a 3D memory device according to various embodiments of the present disclosure.
7A-7D illustrate various example ways to chop a stairwell to different depths in a stairwell structure according to some embodiments of the present disclosure.
8 is a flow diagram of a method for forming an example stairwell structure of a 3D memory device according to some embodiments.
9 is a flow diagram of another method for forming an example stairwell structure of a 3D memory device according to some embodiments.
Embodiments of the present disclosure will be described with reference to the attached drawings.

Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be used in a variety of other applications.

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc. indicate that the described embodiment may include a particular feature, structure or characteristic; It should be noted that not all embodiments necessarily include those specific features, structures or characteristics. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, achieving such feature, structure, or characteristic in connection with another embodiment will be understood by those skilled in the art, whether or not explicitly stated. It will be within knowledge.

In general, terms can be understood at least in part depending on their use in context. For example, as used herein, the term “one or more” may be used to describe any feature, structure, or characteristic in a singular sense or may be used in a plural sense to describe any feature, structure, or characteristic, depending at least in part on the context. Alternatively, it may be used to describe a combination of combinations. Similarly, terms such as “a” and “the” may be understood to convey singular or plural usage, depending at least in part on the context. Additionally, it can be understood that the term “based on” is not necessarily intended to convey an exclusive set of factors, but instead, depending at least in part on the context, indicates the presence of additional factors that are non-essential and not explicitly accounted for. It can be interpreted in a permissive sense.

In the present disclosure, the meaning of “on”, “above”, and “over” is that “on” not only means “directly above” something, but also means an intermediate feature ( It should be broadly interpreted to include the meaning of “above” something that has a feature or layer, and “above” (“over”) not only means “above” something, but also means “above” something. It should be easily understood that it also includes the meaning of “on” something without an intermediate feature or layer in between (i.e., directly on top of something).

Furthermore, for convenience of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used. It can be used herein to explain the relationship between an element or feature of and other element(s) or feature(s) shown in the drawings. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in another direction) and the spatially relative descriptors used herein may be interpreted similarly accordingly.

As used herein, the term “substrate” refers to the material to which subsequent layers of material are added. The substrate itself can be patterned. Material added over the substrate may be patterned or may remain unpatterned. Moreover, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made of an electrically non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term “layer” refers to a portion of material comprising an area having a thickness. A layer may extend across the entirety of the underlying or overlying structure, or may have a smaller extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, either uniform or non-uniform, having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom faces of a continuous structure, or between any pair of horizontal planes on those faces. The layer may extend horizontally, vertically, and/or along a tapered surface. The substrate may be one layer, may include one or more layers therein, and/or may include one or more layers above and/or below. A layer may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (through which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “nominal/nominally” includes a range of values above and/or below a desired value, established during the design phase of a product or process. It refers to the desired value, i.e. target value, of a characteristic or parameter for component or process operation. Such ranges of values may result from slight variations in the manufacturing process or tolerances. As used herein, the term “about” refers to the value of a given quantity that can vary based on the particular technology node associated with the semiconductor device. Based on the particular technology node, the term “about” may refer to the value of a given quantity varying, for example, within 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value). .

As used herein, the term "3D memory device" refers to a vertically oriented string of memory cell transistors extending perpendicular to the substrate on a lateral substrate (herein referred to as a "memory string", such as a NAND memory string). refers to a semiconductor device with As used herein, the term “vertical/perpendicularly” means nominally perpendicular to the lateral surface of the substrate.

In some 3D memory devices, memory cells for storing data are stacked vertically in a stacked storage structure (e.g., a memory stack). 3D memory devices typically include a staircase structure formed on one or more sides (edges) of a stacked storage structure for purposes such as word line fanout. Staircase structures are usually formed at the edges of each memory plane, so the memory cells are unilaterally driven by word lines and row decoders (also called "x-decoders") that are also arranged at the edges of each memory plane through the corresponding staircase structures. .

For example, Figure 1 illustrates a schematic diagram of a 3D memory device 100 with a staircase structure 104. A 3D memory device 100, such as a 3D NAND memory device, includes two memory planes 102, each having an array of memory cells in a memory array structure 106. Note that x and y axes are included in Figure 1 to account for the two orthogonal (perpendicular) directions in the wafer plane. The x direction is the word line direction of the 3D memory device 100 and the y direction is the bit line direction of the 3D memory device 100. The 3D memory device 100 also includes two stairwell structures 104 on opposite sides of each memory array structure 106 in the x direction. Each word line of memory plane 102 extends laterally in the x direction across the entire memory plane 102 to each staircase (level) of staircase structure 104 . Row decoders (not shown) are formed directly above, below, or near each staircase structure 104 to reduce interconnection length. That is, each row decoder drives half of the memory cells unilaterally (either in the positive or negative x direction, but not both) through half of the word lines, each of which spans the entire memory plane 102.

Accordingly, the load of a unilateral row word line drive scheme includes the resistance of the entire word line across memory plane 102. Moreover, as the demand for higher storage capacity continues to increase, the number of vertical levels in the stacked storage structure increases and the thickness of the stack layer comprising each word line film decreases. Therefore, a much higher resistance is introduced into the load, which can result in large resistive-capacitive (RC) delay. Accordingly, performance of the 3D memory device 100, such as read and write speeds, may be affected by the unilateral word line driving scheme using the side staircase structure 104.

Various embodiments according to the present invention provide a staircase structure in the middle of a memory plane that enables a bidirectional word line driving method to reduce RC delay and a method of manufacturing the same. By replacing the existing lateral staircase structure with, for example, a central staircase structure, each row decoder can drive word lines bidirectionally in opposite directions from the middle of the memory plane, so that the length of the word line to be driven by the row decoder is, e.g. For example, as it is reduced by half, the load resistance can be reduced. In some embodiments, a bridge structure is introduced as part of the stairwell structure to connect word lines separated by a central stairwell structure. In some embodiments, a multi-compartment stairwell structure is used where each step of the stairwell structure includes multiple compartments for fan-out multiple word lines, thereby increasing utilization of the stairwell structure and reducing manufacturing complexity. In some embodiments, multiple chopping processes are used to form multiple stairwells at different depths to reduce the number of trim etch processes, thereby further reducing manufacturing complexity and increasing yield.

2 shows a schematic diagram of an example 3D memory device 200 with a staircase structure 204 in accordance with some embodiments of the present disclosure. In some embodiments, 3D memory device 200 includes multiple memory planes 202. Each memory plane 102 has a memory array structure 206-1/206-2 and a memory array structure 206-1/206-2 in the middle of the memory array structure 206-1/206-2. It may include a staircase structure 204 that is laterally divided into a first memory array structure 206-1 and a second memory array structure 206-2 in the x-direction (word line direction). Unlike the 3D memory device 100 of FIG. 1 where the staircase structure 104 is on opposite sides of each memory array structure 106, according to some embodiments, the staircase structure 204 of the 3D memory device 200 is It is intermediate between the first and second memory array structures 206-1 and 206-2. In some embodiments, for each memory plane 202, staircase structure 204 is in the middle of memory array structure 206-1/206-2. That is, the staircase structure 204 evenly divides the memory array structure 206-1/206-2 into first and second memory array structures 206-1 and 206-2 having the same number of memory cells. It may be a central staircase structure. For example, the first and second memory array structures 206-1 and 206-2 may be symmetrical in the x-direction with respect to the central staircase structure 204. In some examples, stairwell structure 204 may be in the middle, but not centrally, of memory array structures 206-1/206-2, and thus first and second memory array structures 206-1/206-2. 1, 206-2) may have different sizes and/or numbers of memory cells. In some embodiments, 3D memory device 200 is a NAND flash memory where memory cells are provided in the form of an array of NAND memory strings (not shown) in first and second memory array structures 206-1 and 206-2. It's a device. The first and second memory array structures 206-1, 206-2 may include any other suitable components including, but not limited to, gate line slits (GLS), through array contacts (TAC), array common source (ACS), etc. Can contain components.

Each word line (not shown) of the memory plane 202 extending laterally in the x direction is divided into two parts by a staircase structure 204: a first word line crossing the first memory array structure 206-1; It may be separated into a portion and a second word line portion crossing the second memory array structure 206-2. As described in detail below, the two portions of each word line may be electrically connected by a bridge structure (not shown) of the staircase structure 204 at each staircase of the stairwell structure 204. Row decoders (not shown) may be formed directly above, below, or adjacent to each staircase structure 204 to reduce interconnection length. As a result, unlike the row decoder of the 3D memory device 100 of FIG. 1, each row decoder of the 3D memory device 200 uses memory cells in the first and second memory array structures 206-1 and 206-2. can be driven in both directions (in both positive and negative x directions). That is, by replacing the conventional side staircase structure (e.g., 104 in FIG. 1) with, for example, the staircase structure 204 in the middle of the memory array structure 206-1/206-2, each row decoder Since word lines can be driven bidirectionally in opposite directions from the middle of the memory plane, the length of the portion of each word line to be driven by the row decoder is such that the staircase structure 204 has a memory array structure 206-1/206- When in the center of 2), the resistance of the load can be reduced by, for example, being reduced by half. That is, according to some embodiments, the row decoder of the 3D memory device 200 only needs to drive the first word line portion or the second word line portion of each word line.

In Figure 2, each of the stairwell structures 204 in the middle of each memory plane 202 is a functional staircase structure used for landing interconnects (e.g., word line contacts), but during manufacturing. Additional staircase structures (e.g., dummy staircase structures (not shown)) may be formed on one or more sides for load balancing and to separate adjacent memory planes 202 in an etching or chemical mechanical polishing (CMP) process. I understand that it exists. Because the staircase structures 204 each in the middle of each memory plane 202 increase the overall area of the memory planes 202, steeper dummy staircase structures with smaller areas can be formed to reduce die size. there is.

3 shows a top view of an example 3D memory device 300 with a staircase structure 301 in accordance with some embodiments of the present disclosure. 3D memory device 300 may be an example of a portion of memory plane 202 of FIG. 2 that includes stairwell structure 204, and staircase structure 301 of 3D memory device 300 in memory plane 202. This may be an example of the staircase structure 204. As shown in FIG. 3 , 3D memory device 300 may include multiple blocks 302 in the y direction (bit line direction) separated by parallel GLSs 308 . In some embodiments where 3D memory device 300 is a NAND flash memory device, each block 302 is the smallest erasable unit of the NAND flash memory device. Each block 302 may further include a number of fingers 304 in the y direction separated by some of the GLS 308 along with an “H” cut 310 .

In some embodiments, staircase structure 301 is in the middle (e.g., center) of 3D memory device 300 in the x-direction (word line direction). In some embodiments, Figure 3 also shows a pair of peripheral regions 303 of the memory array structure adjacent to the staircase structure 301. The peripheral region 303 separated by the stairwell structure 301 may be used to form a top select gate (TSG) that may be individually driven or electrically connected by interconnects across the staircase structure 301. . As will be described in detail below, the stairwell structure 301 may include multiple stairwell sections, each corresponding to each finger 304, and also a multiple bridge structure, each between two adjacent stairwell sections in the y direction. 306) may be included. Each stairwell section may be within one or two blocks 302. The 3D memory device 300 may include a plurality of dummy channel structures 314 in the stairwell area and bridge structure 306 to provide mechanical support and/or load balancing. The 3D memory device 300 has a word line contact portion 312 in the staircase area of the staircase structure 301, each landing on each word line (not shown) at each staircase of the staircase structure 301 for word line driving. ) may further be included.

To achieve a bidirectional word line driving scheme, according to some embodiments, each bridge structure 306 connects (physically and electrically) a first memory array structure and a second memory array structure (not shown). . That is, according to some embodiments, the staircase structure 301 does not completely chop the memory array structure in the middle but instead leaves the first and second memory array structures connected by the bridge structure 306. Accordingly, each word line is connected in both directions (positive and negative direction) can be driven. For example, Figure 3 further illustrates an example current path for a bidirectional word line drive scheme with bridge structure 306. The first current path indicated by the solid arrow and the second current path indicated by the hollow arrow represent the current passing through the two individual word lines at different levels.

4 shows a top front perspective view of an example stairwell structure 400 of a 3D memory device in accordance with some embodiments of the present disclosure. The staircase structure 400 may be an example of the staircase structure 204 of the 3D memory device 200 of FIG. 2 or the staircase structure 301 of the 3D memory device 300 of FIG. 3. Staircase structure 400 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. It may include a stack structure 401 on a substrate (not shown).

4 includes x, y, and z axes to further illustrate the spatial relationships of the components of staircase structure 400. The substrate of the 3D memory device includes two sides extending laterally in the xy plane, namely a top surface on the front side of the wafer on which the staircase structure 400 can be formed, and a bottom surface on the back side opposite the front side of the wafer. Includes. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, one component (e.g., a layer or device) of a 3D memory device is “on,” “over,” or “on” another component (e.g., a layer or device) of a 3D memory device. Whether or not it is "below" is determined relative to the substrate of the 3D memory device in the z direction (vertical direction orthogonal to the xy plane) when the substrate is located in the lowest plane of the 3D memory device in the z direction. The same concepts for describing spatial relationships apply throughout this disclosure.

Stack structure 401 may include a vertically interleaved first material layer and a second material layer different from the first material layer. The first material layer and the second material layer may alternate in the vertical direction. In some embodiments, stack structure 401 may include a plurality of pairs of material layers stacked vertically in the z-direction, each of which includes a first material layer and a second material layer. The number of material layer pairs (e.g., 32, 64, 96, 128, 160, 192, 224, or 256) of stacked structure 401 may determine the number of memory cells of the 3D memory device.

In some embodiments, the 3D memory device is a NAND flash memory device, and stack structure 401 is a stacked storage structure in which NAND memory strings are formed. Each of the first material layers includes a conductive layer and each second material layer includes a dielectric layer. That is, the stack structure 401 may include interleaved conductor layers and dielectric layers (not shown). In some embodiments, each conductor layer may function as a gate line of a NAND memory string and a word line extending laterally from the gate line and terminating in a stairwell structure 400 for word line fanout. The conductor layer includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. It may contain conductive materials. The dielectric layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer includes a metal such as tungsten and the dielectric layer includes silicon oxide.

Each staircase (shown as a “level”) of staircase structure 400 may include one or more pairs of material layers. In some embodiments, the top material layer of each step is a conductive layer for interconnection in the vertical direction. In some embodiments, every two adjacent stairs of staircase structure 400 are offset by a nominally equal distance in the z-direction and a nominally equal distance in the x-direction. Accordingly, each offset may form a “landing area” for interconnection with a word line contact of a 3D memory device (e.g., 312 in FIG. 3, not shown in FIG. 4) in the z direction.

As shown in FIG. 4, the stairwell structure 400 includes a first stairwell section 402, a second stairwell section 412, and a first stairwell section 402 and a second stairwell in the y direction (beat line direction). A bridge structure 404 between zones 412 may be included. In some embodiments, the first stairwell section 402 includes a first pair of stairwells 406-1 and 406-2 and a second pair of stairwells 410-1 and 410-2 in the x-direction (word line direction). , and a plurality of pairs of stairwells including a third pair of stairwells 416-1 and 416-2. According to some embodiments, each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 includes a plurality of stairs in the x-direction. In some embodiments, each stairwell 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2, as opposed to a dummy stairwell, has a landing interconnection (e.g., It is a functional staircase used for word line via contacts). In other words, according to some embodiments, none of the staircases 406-1, 406-2, 410-1, 410-2, 416-1, 416-2 within the first stairwell section 402 are dummy stairs. .

In some embodiments, each pair of staircases 406-1/406-2, 410-1/410-2 or 416-1/416-2 face each other in the x direction and are at different depths. In one example, the first pair of stairwells 406-1/406-2 may face each other in the x-direction, for example, staircase 406-1 tilted in the negative x-direction and staircase 406-1 2) is inclined in the positive x direction. Similarly, in another example, the second pair of staircases 410-1/410-2 may face each other in the x-direction, for example, with stairwell 410-1 tilted in the negative x-direction and the second pair of staircases 410-1/410-2 (410-2) is inclined in the positive x direction. Since one staircase may include multiple staircases, the depth of a staircase disclosed herein may be referred to as the depth of the same staircase in the z-direction (at the same relative level), for example, a top staircase, a middle staircase, or a bottom staircase. You can. In one example, the first pair of stairwells 406-1/406-2 may be at different depths, for example, the top of stairwell 406-1 is at the top of staircase 406-2 in the z direction. Higher than stairs. Similarly, in another example, the second pair of stairwells 410-1/410-2 may be at different depths, for example, the upper staircase of stairwell 410-1 is in the z-direction and the second pair of stairwells 410-1/410-2 are at different depths. ) is higher than the upper stairs of In some embodiments, each pair of staircases 406-1/406-2, 410-1/410-2, or 416-1/416-2 do not overlap in the z-direction. That is, according to some embodiments, the bottom step of an upper staircase is not lower than the top step of the same pair of lower stairwells.

Although the number of staircase pairs in each stairwell zone (e.g., first stairwell zone 402) is not limited to three as shown in FIG. 4, the same staircase pattern described above (i.e., opposite each other in the x-direction and different staircase pairs) Each pair of stairs in depth) can be applied to any number of pairs of staircases. As a result, in some embodiments, each stairwell 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 of the first stairwell section 402 is at a different depth. That is, according to some embodiments, none of the stairs 406-1, 406-2, 410-1, 410-2, 416-1, 416-2 of the first staircase section 402 overlap in the z-direction. No. Moreover, because each stair in the stairwell may be at a different depth, each stair in the first stairwell section 402 may be at a different depth. That is, according to some embodiments, none of the stairs in the first stairwell section 402 overlap in the z-direction (i.e., are not at the same level). As a result, each staircase in the staircase section (e.g., first stairwell section 402) can be used for a landing interconnect (e.g., a word line contact) that contacts each word line at a different level. .

As shown in FIG. 4 , the stairwell structure 400 is a multi-compartment structure including a plurality of compartments in the y direction in each stairwell zone (e.g., first stairwell zone 402 or second stairwell zone 412). It may be a staircase structure. In some embodiments, each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 of the first stairwell section 402 includes a plurality of sections in the y direction. And, each section includes a plurality of stairs in the x direction. By introducing multiple sections in the y-direction, the dimensions (e.g., length) of the staircase structure 400 in the x-direction can be reduced without reducing the total number of stairs. In some embodiments, in each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2, a staircase in one of the compartments is between two stairs in another one of the compartments. is perpendicular to That is, within each stairwell, the depth of the stairs first changes along the y direction (e.g., increases in the negative y direction in Figure 4) and then along the x direction (e.g., increases in the negative y direction in Figure 4 increases in the negative x direction). As a result, for any section within the staircase, the depth of at least one staircase may be within the depth range of the adjacent section(s). The step depth pattern between the above-described sections can be set according to the sequence of applying the trim etch process and the splitting process. Specifically, the step depth pattern between sections disclosed herein may be achieved by applying a segmentation process prior to the trim etch process, as described below in connection with the manufacturing process. For example, as shown in FIG. 4, the stairwell structure 400 includes each stairwell within a stairwell zone (e.g., each stairwell 406-1, 406-2, 410-1 within the first stairwell zone 402). , 410-2, 416-1, or 416-2) may be a four-compartment staircase structure that may include four compartments (408-1, 408-2, 408-3, 408-4) in the y direction. there is. In one example, in staircase 406-1, there may be a middle staircase of compartment 408-2 vertically between the top and bottom stairs of other compartments 408-1, 408-3, and 408-4. . It should be understood that the number of partitions is not limited by the example of Figure 4 and can be any positive integer (i.e., 1, 2, 3, 4, 5, ...).

Although the first stairwell section 402 has been described in detail above, the manner of arranging stairwells in the first stairwell section 402 disclosed herein does not apply to the second stairwell section 412 or any other stairwell within the stairwell structure 400. It is understood that it can be applied similarly to zones. For example, the second stairwell section 412, like the first stairwell section 402, has a pair of stairwells 414-1 and 414-2 facing each other in the x direction and at different depths (e.g., multiple may include a split staircase).

As shown in Figure 4, according to some embodiments, the first stairwell section 402 and the second stairwell section 412 are asymmetric in the y direction. For example, the stairwell patterns in the first and second stairwell sections 402, 412 may not be symmetrical with respect to the bridge structure 404. By asymmetrically arranging stairwells in adjacent stairwell sections, the mechanical stresses introduced by the stairwell structure 400 can be distributed more evenly. In another example, it is understood that the first stairwell section 402 and the second stairwell section 412 may also be symmetrical in the y direction.

As part of the stack structure 401, the bridge structure 404 may include a vertically interleaved conductor layer and a dielectric layer (not shown), and a conductor layer (e.g., a metal layer or a polysilicon layer). may function as part of a word line. At least a portion within the first and second staircase structures 402, 412 wherein the internal word lines are cut off from the memory array structure in the x-direction (e.g., the positive x-direction, the negative x-direction, or both). Unlike the stairwell, the word lines in the bridge structure 404 may be preserved to connect the memory array structure with word line contacts landed on the stairwell to achieve a bi-directional word line drive scheme. In some embodiments, at least one staircase in a stairwell of the first or second stairwell section 402 or 412 is electrically connected to at least one of the first memory array structure and the second memory array structure via the bridge structure 404. connected. At least one word line is connected to the memory array structure and the bridge structure ( 404) may extend laterally. In one example, a staircase within staircase 406-1 may be electrically connected to the first memory array structure (in the negative x direction) by a portion of each word line extending in the negative x direction through bridge structure 404. You can. However, the bridge structure 404 may not need to electrically connect the same step to a second memory array structure (in the positive x direction) because the portion of each word line extending in the positive x direction is not cut. there is. In another example, a staircase within staircase 416-2 may be electrically connected (in the positive x direction) to a second memory array structure by a portion of each word line extending in the positive x direction through bridge structure 404. You can. However, the bridge structure 404 may not need to electrically connect the same steps to the first memory array structure (in the negative x direction) because the portion of each word line extending in the negative x direction is not cut. there is.

In some embodiments, at least one staircase within a stairwell of the first or second stairwell section 402 or 412 is electrically connected to each of the first memory array structure and the second memory array structure via bridge structure 404. For example, as shown in Figure 4, the stairs within stairwell 416-1 are formed by respective word line portions extending in the negative and positive x directions, respectively, as indicated by current paths (indicated by arrows). It may be electrically connected to both the first and second memory array structures through the bridge structure 404.

5A-5F illustrate various example masks for forming example stairwell structures of a 3D memory device according to some embodiments of the present disclosure. 6A and 6B illustrate a manufacturing process for forming an example stairwell structure of a 3D memory device according to various embodiments of the present disclosure. 8 is a flow diagram of a method 800 for forming an example stairwell structure of a 3D memory device according to some embodiments. 9 is a flow diagram of another method 900 for forming an example stairwell structure of a 3D memory device according to some embodiments. Examples of stairwell structures shown in FIGS. 6A, 6B, 8, and 9 include the stairwell structure 400 shown in FIG. 4. Figures 5a-5f, 6a, 6b, 8 and 9 will be described together. It is understood that the operations depicted in methods 800 and 900 are not exhaustive, and that other operations may be performed before, after, or in between any of the illustrated operations. Additionally, some operations may be performed simultaneously or in an order different from that shown in FIGS. 8 and 9.

Referring to Figure 8, method 800 begins at operation 802 where a stairwell zone mask is patterned including openings for a first stairwell zone and a second stairwell zone in the middle of the stack structure. In some embodiments, the stairwell area mask includes a hard mask. The stack structure may include vertically interleaved first and second material layers. In some embodiments, the stack structure is a dielectric stack, wherein each of the first material layers includes a first dielectric layer (also known as a “sacrificial layer”), and each of the second material layers includes a second dielectric layer different from the first dielectric layer. Contains a dielectric layer. The interleaved first and second dielectric layers may be deposited alternately over the substrate.

6A, a plurality of pairs of first dielectric layers (also known as “sacrificial layers”, not shown) and second dielectric layers (together referred to herein as “dielectric layer pairs”, not shown) are formed. A stack structure 602 comprising a silicon substrate (not shown) is formed on the silicon substrate. That is, stack structure 602 includes interleaved sacrificial layers and dielectric layers, according to some embodiments. Dielectric layers and sacrificial layers may be deposited alternately on the silicon substrate to form stack structure 602. In some embodiments, each dielectric layer includes a layer of silicon oxide and each sacrificial layer includes a layer of silicon nitride. Stack structure 602 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. there is.

In some embodiments, the stack structure is a memory stack, wherein each of the first material layers includes a conductive layer and each of the second material layers includes a dielectric layer. Interleaved conductive layers (eg, polysilicon layers) and dielectric layers (eg, silicon oxide layers) may be deposited alternately over the substrate. Interleaved conductor layers (eg, metal layers) and dielectric layers (eg, silicon oxide layers) can also be formed by a gate replacement process that replaces sacrificial layers of the dielectric stack with conductive layers. That is, the staircase structure may be formed before or after the gate replacement process on the dielectric stack or memory stack.

Referring to Figure 6A, stack structure 602 may include multiple pairs of conductor layers and dielectric layers (together referred to herein as “conductor/dielectric layer pairs”). That is, stack structure 602 includes interleaved conductor layers and dielectric layers, according to some embodiments. In some embodiments, each dielectric layer includes a layer of silicon oxide, and each conductor layer includes a layer of a metal, such as tungsten, or a layer of a semiconductor, such as polysilicon. In some embodiments, to form stack structure 602, slit openings (not shown) may be formed through the dielectric stack, and a sacrificial layer of the dielectric stack may be formed through the slit openings to form a plurality of lateral recesses. It may be etched by applying an etchant, and a conductive layer may be deposited in the side recesses using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

Referring to Figure 5A, a staircase area mask 502 is patterned on stack structure 602 (shown in Figure 6A). The stairwell zone mask 502 includes a plurality of stairwell zones and a second stairwell zone in the x-direction (word line direction) in the middle (e.g., center) of the stack structure 602 (shown in FIG. 6A). Includes openings 508-1 and 508-2 for the stairwell area. The stack structure 602 may include a plurality of blocks 504 separated by parallel GLS 506 in the y direction (bit line direction). According to some embodiments, as shown in Figure 5A, each opening 508-1 or 508-2 crosses each GLS 506 between two blocks 504 and ) is within. In another example, it is understood that each block 508-1 or 508-2 may be in one block 504 without crossing GLS 506. Staircase zone mask 502 may be used to define stairwell zones of a stairwell structure through openings 508-1 and 508-2 such that each stairwell zone may correspond to one or two blocks in the final product of the 3D memory device. You can. As shown in Figure 5A, staircase area mask 502 covers bridge structure 510 between adjacent openings 508-01 and 508-2 in the y direction, according to some embodiments. The bridge structure 510 in the staircase area mask 502 may define a region in which the bridge structure of the staircase structure may be formed in the final product of the 3D memory device, and the openings 508 - 1 and 508-2) may define an area in which a staircase with a staircase structure can be formed in the final product of the 3D memory device. 6A , according to some embodiments, stairwell zones 604 and 616 are defined by respective openings 508-1 and 508-2 of stairwell zone mask 502, and stairwell zones in the y direction ( Bridge structure 614 between 604 and 616 is covered by bridge structure 510 in staircase area mask 502.

In some embodiments, the stairwell area mask 502 is made of a material that can survive various processes until the stairwell structure is formed, for example, at least until the chopping process in operation 808 described below. It is a hard mask, as opposed to a soft mask (eg, a photoresist mask), which can be manufactured. Accordingly, the staircase area mask 502 protects the covered portion of the stack structure 602 (e.g., the bridge structure 614) during subsequent processing until the stairwell area mask 502 is removed, thereby protecting the stack structure 602. ) (and the interleaved first and second material layers therein) may be left intact. Staircase area mask 502 may be made of, for example, polysilicon, a high-k dielectric, titanium nitride (TiN), or any other suitable hard mask material. Staircase area mask 502 is a hard mask on stacked structure 602 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. It can be formed by first depositing a layer of material. The hard mask material layer may then be patterned to form openings 508-1 and 508-2 using lithography and dry etching and/or wet etching processes, such as reactive ion etching (RIE). In some embodiments, prior to formation of staircase zone mask 502, in each pair of peripheral regions (e.g., peripheral region 303 in FIG. 3), a TSG cut staircase is formed in the x direction with openings 508-1 and 508- It is formed adjacent to 2).

Optionally, the method 800 proceeds to operation 804, as illustrated in FIG. 8, wherein each of the first and second stairwell sections includes a plurality of partitions in the second lateral direction. They are formed at different depths. Referring to FIG. 9 , a partition mask including openings in first and second staircase regions is patterned in operation 902 to form partitions, and a plurality of partitions of different depths are patterned in the partition mask in operation 904. Depending on the trim, it is formed by one or more etching cycles. It is understood that task 804 may be skipped in some instances where a multi-compartment staircase structure is not used.

As shown in FIG. 5B , section mask 512 is patterned on stairwell section mask 502 . According to some embodiments, sectioning mask 512 is configured to include openings 514-1 and 514-2 respectively in the openings for first and second stairwell sections 508-1 and 508-2 to form sections in the y direction. ) includes. In some embodiments, partition mask 512 is a soft mask (eg, a photoresist mask) that can be trimmed in a trim etch process to form partitions in the y direction. Each opening 514-1 or 514-2 may have a nominally rectangular shape. The solid lines of openings 514-1 and 514-2 in FIG. 5B illustrate the boundaries of the photoresist layer that underlies stacked structure 602 (shown in FIG. 6A). According to some embodiments, bridge structure 510 remains on partition mask 512 to cover underneath bridge structure 614 (shown in FIG. 6A). In some embodiments, section mask 512 is formed by coating a photoresist layer on stairwell section mask 502 using spin coating and patterning the coated photoresist layer using lithography and development processes. Partitioning mask 512 may be used as an etch mask to etch exposed portions of stack structure 602.

As shown in Figure 6A, a plurality of partitions (e.g., four partitions 612-1, 612-2, 612-3, 612-4) of different depths are formed on the partition mask 512 (Figure 5B). is formed by one or more trim etch cycles (e.g., two trim etch cycles) in the y-direction (as shown). A partition mask 512 with openings 514-1 and 514-2 (indicated by solid lines) may be used as the first etch mask. Portions of stack structure 602 not covered by the first etch mask may be etched to the depth of section using wet etch and/or dry etch processes. Any suitable etchant (e.g., wet etching and/or dry etching) may be used to remove a certain thickness (e.g., section depth) of the stacked structure 602 from the exposed portions. Etched thickness (eg, section depth) can be controlled by etch rate and/or etch time. In some embodiments, the section depth is nominally equal to the thickness of the material layer pair (eg, a dielectric layer pair or a conductor/dielectric layer pair). In some embodiments, section depth is understood to be a multiple of the thickness of a material layer pair.

As shown in Figure 5B, section mask 512 may be trimmed (eg, gradually and inwardly etched). The dashed lines of openings 514-1 and 514-2 illustrate the boundaries of the trimmed photoresist layer covering underneath stacked structure 602. Each of openings 514-1 and 514-2 can be trimmed in both the x and y directions due to their rectangular shape. A partition mask 512 with trimmed openings 514-1 and 514-2 (indicated by dashed lines) may be used as the second etch mask.

As shown in Figure 6A, the amount of photoresist layer trimmed from the first etch mask can be controlled by trimming speed and/or trimming time and can be directly related to the dimensions of the resulting section (e.g. may be a determining factor). Trimming of the first etch mask may be performed using any suitable etching process, such as isotropic dry etching or wet etching. Trimming the first etch mask may cause portions of the stack structure 602 not covered by the first etch mask to be enlarged. The enlarged uncovered portion of the stacked structure 602 can be etched again using the trimmed first etch mask as a second etch mask to form more sections at different depths in each staircase region 604 or 616. . Any suitable etchant (e.g., wet etching and/or dry etching) may be used to remove a certain thickness (e.g., section depth) of the stack structure 602 in the enlarged exposed portion. Etched thickness (eg, section depth) can be controlled by etch rate and/or etch time. In some embodiments, the etched thickness is nominally the same as the etched thickness in the previous etch step. As a result, the depth offset between adjacent segments is nominally the same. It is understood that in some embodiments, the etched thickness is different in different etching steps so that the depth offset is different between adjacent sections. The trim process of the photoresist mask followed by the etching process of the stack structure is referred to herein as a trim etch cycle. The number of trim etch cycles may determine the number of sections formed according to section mask 512. In some embodiments, bridge structure 614 has sections 612-1, 612-2, 612-3, and 612-4 formed by multiple trim etch cycles (e.g., two trim etch cycles). It remains intact afterward, thanks to the protection from the bridge structure 510 of the untrimmed section mask 512 (shown in FIG. 5B).

Figure 6A shows an example of forming a four-compartment staircase structure comprising four compartments (612-1, 612-2, 612-3, 612-4) at different depths in each stairwell section (604, 616). However, it is understood that the multi-compartment stairwell structure and method of manufacturing it is not limited to four compartments and can be any integer greater than 1 by varying the design of the compartment mask 512 as well as the number of trim etch cycles accordingly.

The method 800 proceeds to operation 806, as shown in FIG. 8, wherein each of the first and second stairwell sections includes at least one pair of stairwells opposite each other in the first lateral direction. A bridge structure is formed between the first stairwell section and the second stairwell section with the same depth but in a second lateral direction perpendicular to the first lateral direction. In some embodiments, each stairwell of the at least one pair of stairwells includes a plurality of stairs in a first lateral direction. In some embodiments where the partition is formed in the second lateral direction at operation 804, operation 806 is performed after operation 804. That is, the second lateral partition is formed in front of the first lateral staircase. 9 , to form a stairwell, a staircase mask including openings in a first lateral direction is patterned in operation 906 and at least one staircase mask is patterned in operation 908 by a plurality of trim etch cycles according to the staircase mask. Pairs of stairwells are formed with the same depth.

As shown in Figure 5C, section mask 512 (shown in Figure 5B) is removed once sections 612-1, 612-2, 612-3, and 612-4 are formed, and stairwell mask 516 is patterned on the staircase area mask 502. The stairwell mask 516 includes x-direction openings 518-1, 518-2, and 518-3 to form a pair of stairwells facing each other at the same depth, according to some embodiments. The number of openings 518-1, 518-2, and 518-3 may determine the number of opposing stair pairs to be formed, and may therefore be any suitable number depending on the arrangement of the staircase structure in the final product of the 3D memory device. You must understand that this can happen. In some embodiments, stairwell mask 516 is a soft mask (e.g., a photoresist mask) that can be trimmed in a trim etch process to form stairwells in the x-direction. Each opening 518-1, 518-2, or 518-3 may have a nominally rectangular shape and may extend across openings 508-1 and 508-2 of the staircase area. The solid lines of openings 518-1, 518-2, and 518-3 in Figure 5C illustrate the boundaries of the photoresist layer that underlies stack structure 602 (shown in Figure 6A). In some embodiments, staircase mask 516 is formed by coating a photoresist layer on stairwell area mask 502 using spin coating and patterning the coated photoresist layer using lithography and development processes. Stairwell mask 516 may be used as an etch mask to etch exposed portions of stack structure 602.

As shown in FIG. 6A , a plurality of pairs of stairwells (e.g., Three pairs of staircases (606-1/606-2, 608-1/608-2, 610-1/610-2) are formed. According to some embodiments, bridge structure 614 is formed between stairwell sections 604 and 616 in the y direction. According to some embodiments, each pair of staircases 606-1/606-2, 608-1/608-2, 610-1/610-2 face each other in the x-direction and are at the same depth. Taking a pair of stairwells 606-1/606-2 as an example, the stairwell 606-1 may be inclined in the negative x direction and the stairwell 606-2 may be inclined in the positive x direction. there is. Each staircase 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2 may include the same number of stairs in the x direction. In some embodiments, a pair of stairwells (e.g., three pairs of stairwells 606-1/606-2, 608-1/608-2, and 610-1/610-) in each stairwell section 604 or 616. 2) The number of staircases is determined based on the number of openings (e.g., three openings 518-1, 518-2, 518-3) in the staircase mask 516, and the number of stairs in each stairwell is determined. The number is determined based on the number of trim etch cycles. In some embodiments, as shown in Figure 6A, multiple compartments 612-1, 612-1, and 612-2, 612-3, 612-4) are formed so that each staircase (606-1, 606-2, 608-1, 608-2, 610-1 or 610-2) is divided into multiple compartments (612-1) , 612-2, 612-3 and 612-4).

The trim etching process for forming the staircases 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 has been described in detail above and is not repeated for convenience of explanation. The dimensions of each step in stairwells 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 are determined by the amount of trimmed photoresist layer of staircase mask 516 in each cycle ( e.g., determining the dimension in the x-direction) and by the thickness etched in each cycle (e.g., determining the depth in the z-direction). In some embodiments, the amount of photoresist layer trimmed in each cycle is nominally the same, and thus the steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2 in the x direction. The dimensions of each step in are nominally the same. In some embodiments, the etched thickness in each cycle is nominally the same, such that the depth of each step in stairwells 606-1, 606-2, 608-1, 608-2, 610-1, 610-2 is Nominally the same. As the same trim etch process (e.g., the same number of trim etch cycles) is applied simultaneously through openings 518-1, 518-2, and 518-3 of stairwell mask 516, each stairwell 606-1 , 606-2, 608-1, 608-2, 610-1 or 610-2) may have the same depth. For example, the first pair of stairwells 606-1/606-2 may be formed through the opening 518-1, and the second pair of stairwells 608-1/608-2 may be formed through the opening 518. -2), and the third pair of staircases 610-1/610-2 can be formed through the opening 518-3. According to some embodiments, bridge structure 614 remains intact during the trim etch process.

The method 800 proceeds to operation 808, as shown in FIG. 8, wherein in each of the first and second stairwell sections, each stairwell of the at least one pair of stairwells is chopped to a different depth. do. In some embodiments, after chopping each stairwell, at least one staircase of each staircase is covered by a stairwell zone mask through a bridge structure by at least one of the sacrificial layers or by at least one of the conductive layers with the remainder of the stack structure covered by the stairwell zone mask. connected to the part. 9 , to chop a stairwell, a first chop mask including first openings in first and second stairwell regions is patterned at operation 910 and a first chop mask is patterned at operation 912. A first set of staircases exposed by the openings are chopped to a first depth according to a first chopping mask by a plurality of etches. In some embodiments, to chop a stairwell, a second chopping mask is patterned in operation 914 including second openings in the first and second stairwell regions, and a second set of stairwells exposed by the second openings. is chopped to a second depth by a plurality of etch cycles according to a second chopping mask in operation 916.

As shown in FIG. 5D, when the stairwells 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 are formed, the staircase mask 516 (shown in FIG. 5c) is is removed, and a first chopping mask 520 is patterned on the stairwell zone mask 502. According to some embodiments, the first chopping mask 520 is formed on the first and second stairwell zones 508-1,508-, respectively. The first set of staircases exposed by the openings 522-1 and 522-2, including the openings 522-1 and 522-2 in the opening of 2), are chopped to the same first depth. Since the openings 522-1 and 522-2 of the first chopping mask 520 correspond to the stairwells 610-2, 610-1, and 608-2 (shown in FIGS. 6A and 6B), the stairwells 610- 2, 610-1, and 608-2) can be chopped to the first depth according to the first chopping mask 520. Because the first chopping mask 520 does not need to be trimmed, the first chopping mask 520 may be a hard mask or a soft mask. Each opening 522-1 or 522-2 has a nominally rectangular shape and is in a respective opening of the staircase area 508-1 or 508-2. In some embodiments where the first chopping mask 520 is a soft mask, the first chopping mask 520 can be coated with a photoresist layer on the stairwell area mask 502 using spin coating and a lithography and development process. It is formed by patterning a coated photoresist layer. In some embodiments where the first chopping mask 520 is a hard mask, the first chopping mask 520 may be one or more layers including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or combinations thereof. It is formed by first depositing a layer of hard mask material on the staircase area mask 502 using a thin film deposition process. The hard mask material layer may then be patterned to form openings 522-1 and 522-2 using lithography and dry etching and/or wet etching processes, such as RIE. The first chopping mask 520 may be used as an etch mask to chop the exposed first set of staircases 610-2, 610-1, and 608-2 to the same first depth.

As used herein, a “chopping” process is a process of reducing the depth of one or more stairwells by multiple etch cycles. Each etch cycle may include one or more dry etching and/or wet etching processes that etch one step, i.e., reduce the depth by one step depth. As detailed above, the purpose of the chopping process is to make each stairwell (and each step in the staircase) a different depth in the final product of the 3D memory device, according to some embodiments. Therefore, depending on the number of staircases, a certain number of chopping processes may be required.

As shown in FIG. 5E, once the first set of stairwells 610-1, 610-2, and 608-2 are chopped, the first chopping mask 520 (shown in FIG. 5D) is removed, and the stairwell zone mask A second chopping mask 524 is patterned on 502. According to some embodiments, the second chopping mask 524 includes openings 526-1 and 526-2 in the openings of the first and second stairwell sections 508-1 and 508-2, respectively, to The second set of stairwells exposed by 526-1 and 526-2) are chopped to the same second depth. The openings 526-1 and 526-2 of the second chopping mask 524 correspond to the stairwells 610-1, 608-2, 608-1 and 606-2 (shown in FIGS. 6A and 6B), Accordingly, only the stairwells 610-1, 608-2, 608-1, and 606-2 can be chopped to the second depth according to the second chopping mask 524. Similar to the first chopping mask 520, the second chopping mask 524 may be a hard mask or a soft mask. The second chopping mask 524 may be used as an etch mask to chop the exposed second set of staircases 610-1, 608-2, 608-1, and 606-2 to the same second depth. After the second chopping process according to the second chopping mask 524, some stairwells (e.g., 610-1 and 608-2) are chopped twice by the sum of the first and second depths, and some stairwells (e.g., 610-2) is chopped once to the first depth, some stairwells (eg, 608-1 and 606-2) are chopped once to the second depth, and some stairwells (eg, 606-1) are not chopped.

One or more chopping masks and chopping processes may be required to configure each staircase 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2 at a different depth. For example, as shown in Figure 5F, when the second set of stairwells 610-1, 608-2, 608-1, and 606-2 are chopped, a second chopping mask 524 (shown in Figure 5E) is used. ) can be removed, and a third chopping mask 528 is patterned on the staircase area mask 502. According to some embodiments, the third chopping mask 528 includes openings 530-1 and 530-2 in the openings of the first and second stairwell sections 508-1 and 508-2, respectively, The third set of staircases exposed by 530-1 and 530-2) are chopped to the same third depth. The openings 530-1 and 530-2 of the third chopping mask 528 correspond to the stairwells 608-2 and 608-1 (shown in FIGS. 6A and 6B), and thus the stairwells 608-2 and 608-1 Only 608-1) can be chopped by the third chopping depth according to the third chopping mask 528. Similar to the first and second chopping masks 520 and 524, the third chopping mask 528 may be a hard mask or a soft mask. The third chopping mask 528 may be used as an etch mask to chop the exposed third set of stairwells 608-2 and 608-1 by the same third depth. As a result, after the third chopping process according to the third chopping mask 528, each staircase 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 has different depths. You can have it.

In some embodiments, staircase area mask 502 is removed in a third chopping process, i.e., after finishing the chopping process, for example using a wet etch and/or dry etch process. That is, according to some embodiments, the staircase area mask 502 is configured such that the first and second material layers interleaved in the memory array structure as well as the bridge structure 614 of the stairwell structure are etched by various trim etching processes and chopping processes. To prevent this, it remains on the stack structure 602 at least until the chopping process at task 808.

The above-described first, second, and third chopping masks 520, 524, and 528 and the first, second, and third chopping processes are chopping staircases 606-1, 606-2, 608-1, and 608-2. 610-1 and 610-2) are examples, and it should be understood that the same results can be achieved using other suitable chopping methods (including various chopping masks and chopping processes). Additionally, it should be understood that in the final product of the 3D memory device, the same effect as each staircase in the staircase structure having a different depth can be achieved through various chopping methods. For example, FIGS. 7A-7D illustrate various example ways to chop stairwells to different depths in a stairwell structure according to some embodiments of the present disclosure. Each of FIGS. 7A-7D illustrates one exemplary chopping scheme that can chop six stairwells (indicated by dashed lines in FIGS. 7A-7D) to different depths. As described above, the number of chopping masks, the sequence of chopping masks, the design of each chopping mask (e.g., number and pattern of openings), and/or the depth reduced by each chopping process (e.g., number of etch cycles) determines the staircase. Even if they are at different depths, the specific depth of each staircase can be affected after the chopping process.

According to one aspect of the present invention, a three-dimensional memory device includes a memory array structure and a staircase structure that laterally divides the memory array structure into a first memory array structure and a second memory array structure in the middle of the memory array structure. . The stairwell structure includes a first stairwell section and a bridge structure connecting the first memory array structure and the second memory array structure. The first stairwell zone comprises a first pair of stairwells facing each other at different depths in a first lateral direction. Each staircase includes a plurality of stairs. At least one staircase of the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through a bridge structure.

In some embodiments, each staircase of the first pair of stairs includes a plurality of sections in a second lateral direction perpendicular to the first lateral direction. In some embodiments, a staircase in one of the compartments is perpendicular between two stairs in another one of the compartments.

In some embodiments, the memory array structure includes a plurality of blocks in a second lateral direction. In some embodiments, the first stairwell section is within one or two of the blocks.

In some embodiments, the stairwell structure further includes a second stairwell section. In some embodiments, the bridge structure is between the first stairwell section and the second stairwell section in the second lateral direction.

In some embodiments, the second stairwell zone includes a second pair of stairwells facing each other in a first lateral direction and at a different depth. In some embodiments, the first stairwell zone and the second stairwell zone are asymmetric in the second laterally direction.

In some embodiments, the first stairwell zone includes a second pair of stairwells facing each other in a first lateral direction and at a different depth. In some embodiments, the first and second pairs of stairwells are at different depths. In some embodiments, each staircase of the first and second pair of stairwells is at a different depth.

In some embodiments, the 3D memory device further includes at least one word line extending laterally from the memory array structure and the bridge structure, such that at least one staircase is formed by the at least one word line through the bridge structure to the first and second steps. It is electrically connected to at least one of the second memory array structures.

In some embodiments, at least one staircase of the first pair of stairwells is electrically connected to each of the first memory array structure and the second memory array structure through a bridge structure.

In some embodiments, the bridge structure includes vertically interleaved conductor layers and dielectric layers.

According to another aspect of the present disclosure, a 3D memory device includes a memory array structure and a staircase structure that laterally divides the memory array structure into a first memory array structure and a second memory array structure in the middle of the memory array structure. The stairwell structure includes a first stairwell section and a bridge structure connecting the first memory array structure and the second memory array structure. The first stairwell zone comprises a first stairwell comprising a plurality of compartments in a second lateral direction. Each section includes a plurality of steps in a first lateral direction perpendicular to the second lateral direction. A staircase in one of the compartments is vertically between two stairs in the other one of the compartments. At least one staircase in the first staircase is electrically connected to at least one of the first memory array structure and the second memory array structure through a bridge structure.

In some embodiments, the first stairwell zone further includes a second stairwell. In some embodiments, the first stairwell and the second stairwell face each other in the first side direction and have different depths.

In some embodiments, each staircase in the first and second stairwells is at a different depth. In some embodiments, each staircase in the first and second stairwells is electrically connected to at least one of the first and second memory array structures through a bridge structure.

In some embodiments, the memory array structure includes a plurality of blocks in a second lateral direction. In some embodiments, the first stairwell section is within one or two of the blocks.

In some embodiments, the stairwell structure further includes a second stairwell section. In some embodiments, the bridge structure is between the first stairwell section and the second stairwell section in the second lateral direction.

In some embodiments, the 3D memory device further includes at least one word line laterally extending from the memory array structure and the bridge structure, such that at least one staircase extends through the bridge structure by the at least one word line to the first and second steps. It is electrically connected to at least one of the second memory array structures.

In some embodiments, at least one staircase in the first pair of stairwells is electrically connected to each of the first memory array structure and the second memory array structure through a bridge structure.

In some embodiments, the bridge structure includes vertically interleaved conductor layers and dielectric layers.

In some embodiments, the stairwell structure is in the middle of the memory array structure.

According to another aspect of the present invention, a method of forming a staircase structure of a 3D memory device is disclosed. A stairwell zone mask is patterned including openings for the first stairwell zone and the second stairwell zone in the middle of a stacked structure comprising vertically interleaved first and second material layers. In each of the first and second stairwell zones, at least one pair of stairwells is formed opposite each other at the same depth in the first lateral direction, between the first and second stairwell zones in the first lateral direction perpendicular to the second lateral direction. A bridge structure is formed in the. In each of the first and second stairwell zones, each stairwell of the at least one pair of stairwells is chopped to a different depth.

In some embodiments, prior to forming the at least one pair of stairwells, a plurality of sections are formed in the second lateral direction at different depths, such that each step of the at least one pair of stairwells includes a plurality of sections.

In some embodiments, a partition mask including openings in the first and second staircase regions is patterned to form a plurality of partitions, the plurality of partitions being formed at different depths by one or more trim etch cycles according to the partition mask. do.

In some embodiments, the bridge structure is covered by a staircase area mask or section mask.

In some embodiments, a stairwell mask including openings in a first lateral direction is patterned to form at least one pair of stairwells, wherein the at least one pair of stairwells is patterned at the same depth by a plurality of trim etch cycles according to the stairwell mask. is formed

In some embodiments, to chop each stairwell, a first chopping mask is formed including first openings in the first and second stairwell sections, and the first set of stairwells exposed by the first openings are formed into a first chopping mask. It is chopped to a first depth by a plurality of etching cycles according to the mask.

In some embodiments, to chop each stairwell, a second chopping mask is formed in the first and second stairwell sections and includes second openings, and the second set of stairwells exposed by the second openings are formed into a second chopping mask. It is chopped to a second depth by a plurality of etching cycles according to the mask.

In some embodiments, each of the first material layers includes a sacrificial layer and each of the second material layers includes a dielectric layer.

In some embodiments, each of the first material layers includes a conductive layer and each of the second material layers includes a dielectric layer.

In some embodiments, each staircase of the at least one pair of stairwells includes a plurality of stairs in a first lateral direction. In some embodiments, after chopping each staircase, at least one staircase of each staircase is removed from a stacked structure covered by a stairwell zone mask, through a bridge structure by at least one of the sacrificial layers or by at least one of the conductive layers. connected to the rest.

In some embodiments, the stairwell zone mask remains at least until each stair has been chopped. In some embodiments, the stairwell area mask includes a hard mask.

The foregoing description of specific embodiments is intended to enable others, applying the knowledge of those skilled in the art, to readily modify and/or adapt such specific embodiments for various applications, without undue experimentation and without departing from the general concept of the disclosure. It will reveal general features of the present disclosure that enable it. Accordingly, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the phraseology or phraseology in this specification is for explanatory purposes and not for limitation, and that the terminology or phraseology in this specification should be interpreted by those skilled in the art in the light of teaching and guidance.

Embodiments of the present disclosure have been described using functional structural blocks that illustrate the implementation of specific functions and their relationships. The boundaries of these functional structural blocks are arbitrarily defined herein for convenience of description. Alternative boundaries can be defined as long as specific functions and their relationships are performed appropriately.

The Summary section and the Abstract section may present one or more, but not all, exemplary embodiments of the disclosure as contemplated by the inventor(s), and are therefore not intended to limit the disclosure and appended claims in any way. That's not the intention.

The breadth and scope of the present disclosure should not be limited by any of the foregoing exemplary embodiments, but should be defined only by the following claims and their equivalents.

Claims (41)

As a three-dimensional memory device,
a memory array structure,
a staircase structure in the middle of the memory array structure laterally dividing the memory array structure into a first memory array structure and a second memory array structure, the staircase structure comprising a first staircase section, and a bridge structure connecting the first memory array structure and the second memory array structure, the stairwell structure further comprising a second stairwell section, the bridge structure extending between the first stairwell section and the second stairwell section in a second lateral direction; Between the second stairwell areas,
The first stairwell section includes a plurality of stairs, the second stairwell section includes a plurality of stairs, and the first stairwell section and the second stairwell section are asymmetric in the second lateral direction.
3D memory device. According to paragraph 1,
The first stairwell zone comprises a first pair of stairwells facing each other in a first side direction and at different depths.
3D memory device. According to paragraph 2,
The second stairwell zone comprises a second pair of stairwells facing the first laterally and at different depths.
3D memory device. According to paragraph 2,
At least one staircase of the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.
3D memory device. According to paragraph 1,
further comprising a row decoder directly above, below, or proximate to the staircase structure.
3D memory device. According to paragraph 2,
Each staircase of the first pair of stairwells includes a plurality of divisions in the second lateral direction perpendicular to the first lateral direction,
A staircase in one of the compartments is located vertically between two stairs in the other of the compartments.
3D memory device. According to any one of claims 1 to 6,
the memory array structure includes a plurality of blocks in the second lateral direction,
The first stairwell zone is located within one or two of the blocks.
3D memory device. According to paragraph 2,
the first stairwell zone comprises a second pair of stairwells facing each other in the first lateral direction at different depths,
Each stairwell of the first and second pair of stairwells is at a different depth.
3D memory device. According to clause 8,
Each staircase of the first and second pairs of stairwells is at a different depth.
3D memory device. According to paragraph 1,
It further includes at least one word line extending laterally from the memory array structure and the bridge structure, wherein at least one step is formed by the at least one word line through the bridge structure to the first and second memory arrays. electrically connected to at least one of the structures
3D memory device. According to paragraph 2,
At least one staircase of the first pair of staircases is electrically connected to each of the first memory array structure and the second memory array structure through the bridge structure.
3D memory device. According to paragraph 1,
The bridge structure includes vertically interleaved conductor layers and dielectric layers.
3D memory device. As a three-dimensional memory device,
a memory array structure,
and a stairwell structure in the middle of the memory array structure laterally dividing the memory array structure into a first memory array structure and a second memory array structure, wherein the stairwell structure includes a first stairwell section and the first memory array. a bridge structure connecting the structure and the second memory array structure, the stairwell structure further comprising a second stairwell section, the bridge structure comprising the first stairwell section and the second stairwell section in a second lateral direction. in between,
The first stairwell section comprises a first pair of stairwells having a plurality of sections, and the second stairwell section includes a second pair of stairwells having a plurality of sections, each section being located in the second lateral direction. comprising a plurality of steps in a first vertical direction,
a staircase in one of the compartments is perpendicular between two stairs in another of the compartments, and the first stairwell section and the second stairwell section are asymmetric in the second lateral direction,
3D memory device. According to clause 13,
The first stairwell zone comprises a first pair of stairwells comprising a plurality of sections in the second lateral direction.
3D memory device. According to clause 14,
The second stairwell zone comprises a second pair of stairwells comprising a plurality of sections in the second lateral direction.
3D memory device. According to clause 13,
At least one staircase of the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.
3D memory device. According to clause 13,
further comprising a row decoder directly above, below, or proximate to the staircase structure.
3D memory device. According to clause 13,
The first pair of stairwells and the second pair of stairwells face each other in the first lateral direction and have different depths.
3D memory device. According to clause 13,
Each staircase of the first and second stairwells is at a different depth.
3D memory device. According to clause 13,
Each staircase of the first and second staircases is electrically connected to at least one of the first and second memory array structures through the bridge structure.
3D memory device. According to any one of claims 13 to 20,
the memory array structure includes a plurality of blocks in the second lateral direction,
The first stairwell zone is located within one or two of the blocks.
3D memory device. According to clause 13,
It further includes at least one word line extending laterally from the memory array structure and the bridge structure, wherein at least one step is formed by the at least one word line through the bridge structure to the first and second memory arrays. electrically connected to at least one of the structures
3D memory device. According to clause 13,
At least one staircase of the first staircase is electrically connected to each of the first memory array structure and the second memory array structure through the bridge structure.
3D memory device. According to clause 13,
The bridge structure includes vertically interleaved conductor layers and dielectric layers.
3D memory device. According to clause 13,
The staircase structure is located in the middle of the memory array structure.
3D memory device. A method of forming a staircase structure of a three-dimensional (3D) memory device, comprising:
patterning a stairwell zone mask including openings for a first stairwell zone and a second stairwell zone in the middle of a stacked structure comprising vertically interleaved first and second material layers;
forming at least one pair of stairwells facing each other in each of the first and second stairwell zones, such that a bridge structure is formed in a second lateral direction between the first stairwell zone and the second stairwell zone - the first stairwell zone wherein the stairwell section and the second stairwell section are asymmetric in the second lateral direction.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
The step of forming at least one pair of staircases facing each other includes forming at least one pair of staircases facing each other in a first lateral direction perpendicular to the second lateral direction with the same depth.
Method for forming a staircase structure of a 3D memory device. According to clause 27,
further comprising chopping each stairwell of the at least one pair of stairwells to a different depth in each of the first and second stairwell sections.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
further comprising a row decoder directly above, below, or proximate to the staircase structure.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
Before forming the at least one pair of stairwells, forming the plurality of sections at different depths in the second lateral direction such that each stairwell of the at least one pair of stairwells includes a plurality of sections.
Method for forming a staircase structure of a 3D memory device. According to clause 30,
The step of forming the plurality of compartments is
patterning a partition mask including openings in the first and second stairwell zones;
forming the plurality of sections at different depths by one or more trim etch cycles according to the section mask.
Method for forming a staircase structure of a 3D memory device. According to clause 31,
wherein the bridge structure is covered by the staircase area mask or the section mask,
Method for forming a staircase structure of a 3D memory device. According to any one of claims 26 to 32,
The step of forming the at least one pair of staircases is
patterning a staircase mask including openings in a first lateral direction perpendicular to the second lateral direction;
forming the at least one pair of stairwells at the same depth by a plurality of trim etch cycles according to the staircase mask,
Method for forming a staircase structure of a 3D memory device. According to clause 28,
The steps for chopping each staircase are:
patterning a first chopping mask including first openings in the first and second staircase regions;
chopping the first set of staircases exposed by the first openings to a first depth by a plurality of etching cycles according to the first chopping mask.
Method for forming a staircase structure of a 3D memory device. According to clause 34,
The steps for chopping each staircase are:
patterning a second chopping mask including second openings in the first and second staircase regions;
chopping the second set of staircases exposed by the second openings to a second depth by a plurality of etching cycles according to the second chopping mask.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
Each of the first material layers includes a sacrificial layer, and each of the second material layers includes a dielectric layer.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
Each of the first material layers includes a conductive layer, and each of the second material layers includes a dielectric layer.
Method for forming a staircase structure of a 3D memory device. According to clause 36,
Each staircase of the at least one pair of stairwells includes a plurality of stairs in a first lateral direction perpendicular to the second lateral direction,
After chopping each staircase, at least one staircase of each staircase is connected by at least one of the sacrificial layers to the remainder of the stack structure covered by the stairwell area mask through the bridge structure.
Method for forming a staircase structure of a 3D memory device. According to clause 37,
Each staircase of the at least one pair of stairwells includes a plurality of stairs in a first lateral direction perpendicular to the second lateral direction,
After chopping each staircase, at least one staircase of each staircase is connected by at least one of the conductor layers through the bridge structure to the remainder of the stack structure covered by the staircase area mask.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
The staircase area mask is maintained at least until each staircase is chopped.
Method for forming a staircase structure of a 3D memory device. According to clause 26,
The stairwell area mask includes a hard mask.
Method for forming a staircase structure of a 3D memory device.

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