KR102665796B1 - Resistance variable memory device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a variable resistance memory device and a method of manufacturing the same, including first conductive lines, second conductive lines intersecting the first conductive lines, and a connection between the first conductive lines and the second conductive lines. It includes memory cells provided at each intersection, and each of the memory cells includes a selection element and a variable resistance structure, wherein the variable resistance structure includes a lower electrode, a magnetic tunnel junction, a capping pattern, a stress application pattern, and an upper electrode sequentially stacked. Contains electrodes. The magnetic tunnel junction includes a fixed layer pattern, a free layer pattern, and a tunnel barrier layer pattern interposed between them, the stress applying pattern includes a conductive material having tensile stress, and the fixed layer pattern and the free layer pattern include A variable resistance memory device is provided in which the width of the layer pattern and the tunnel barrier layer pattern is smaller than the width of the capping pattern and the stress application pattern.

Description

Variable resistance memory device and method for manufacturing the same {Resistance variable memory device and method for fabricating the same}

The present invention relates to a variable resistance memory device and a method of manufacturing the same, and more specifically, to a variable resistance memory device using a magnetic tunnel junction as a variable resistance and a method of manufacturing the same.

Recently, with the spread of portable digital devices and the increasing need for digital data storage, interest in non-volatile memory devices that do not lose stored data even when the power is turned off is increasing.

As a semiconductor device, flash memory devices that can be manufactured at low cost based on a silicon process, such as DRAM memory devices, are widely used. However, compared to DRAM memory devices, which are volatile memory devices, flash memory devices have the disadvantage of having relatively low integration, slow operating speed, and requiring a relatively high voltage to store data.

To overcome these shortcomings of flash memory devices, various next-generation semiconductor devices such as phase changeable RAM (PRAM), magnetic RAM (MRAM), and resistance changeable RAM (RRAM) are being developed. It is being proposed. These next-generation non-volatile memory devices can operate at relatively low voltages and have fast access times, thereby offsetting many of the disadvantages of flash memory devices. In particular, magnetic memory devices are attracting attention as next-generation memories because they can operate at high speeds and/or have non-volatile characteristics.

As the electronics industry develops, the demand for high integration and/or low power consumption for magnetic memory devices is intensifying. Therefore, many studies are being conducted to meet these demands.

The technology behind this application is disclosed in Patent Publication No. 10-2018-0065071.

The technical problem to be solved by the present invention is to provide a variable resistance memory device with improved electrical characteristics and reliability and a method of manufacturing the same.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A variable resistance memory device according to embodiments of the present invention for achieving the above object includes first conductive lines; second conductive lines intersecting the first conductive lines; and memory cells provided at intersections between the first conductive lines and the second conductive lines, each of the memory cells including a selection element and a variable resistance structure, wherein the variable resistance structures are sequentially stacked. It includes a lower electrode, a magnetic tunnel junction, a capping pattern, a stress application pattern, and an upper electrode, wherein the magnetic tunnel junction includes a fixed layer pattern, a free layer pattern, and a tunnel barrier layer pattern interposed between them, and the stress application pattern is It includes a conductive material having tensile stress, and the width of the fixed layer pattern, the free layer pattern, and the tunnel barrier layer pattern is smaller than the width of the capping pattern and the stress application pattern.

According to one embodiment, one side of the capping pattern and the stress application pattern is coplanar, and one side of the magnetic tunnel junction adjacent to the one side of the capping pattern and the stress application pattern is adjacent to the one side. It may be unaligned and indented inward.

According to one embodiment, the display device further includes a protection pattern that covers side walls of the variable resistance structure and exposes an upper surface of the upper electrode, and the upper electrode may be connected to a corresponding second conductive line.

According to embodiments of the present invention, as a stress application pattern having tensile stress is disposed on the magnetic tunnel junction, the coercive force of the magnetic tunnel junction can be increased and the switching current can be improved. In particular, as the stress application pattern has a larger width than the layers of the magnetic tunnel junction, the stress application efficiency is improved, further strengthening the magnetic and electrical characteristics of the magnetic tunnel junction, and reducing retention fail bits. It can be.

As a result, it may be possible to provide a variable resistance element with improved electrical characteristics and reliability.

1 is a perspective view schematically showing a variable resistance memory device according to embodiments of the present invention.
Figure 2 is a diagram for explaining memory cells according to embodiments of the present invention.
3A and 3B are conceptual diagrams for explaining magnetic tunnel junction according to embodiments of the present invention.
Figure 4 is a cross-sectional view illustrating a variable resistance memory device according to an embodiment of the present invention.
5 to 16 are cross-sectional views for explaining a method of manufacturing a variable resistance memory device according to an embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The present embodiments are merely provided to ensure that the disclosure of the present invention is complete and to provide common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

In the present specification, when a member is said to be located “on” another member, this includes not only the case where a member is in contact with another member, but also the case where another member exists between the two members. In addition, in the specification of the present application, when a part "includes" a certain component, this means that it may further include other components, rather than excluding other components, unless specifically stated to the contrary.

As used throughout the specification, the terms “about,” “substantially,” and the like are used to mean at or close to that value when manufacturing and material tolerances inherent in the stated meaning are given, and are understood herein. Precise or absolute figures are used to assist in preventing unscrupulous infringers from taking unfair advantage of the stated disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a perspective view schematically showing a variable resistance memory device according to embodiments of the present invention.

Referring to FIG. 1 , first conductive lines CL1 extending in a first direction D1, and second conductive lines CL2 extending in a second direction D2 intersecting the first direction D1. ) can be provided. The second conductive lines CL2 may be spaced apart from the first conductive lines CL1 along the first direction D1 and the third direction D3 perpendicular to the second direction D2. The memory cell stack MCA may be provided between the first conductive lines CL1 and the second conductive lines CL2. The memory cell stack MCA may include memory cells MC provided at intersections of the first conductive lines CL1 and the second conductive lines CL2. Memory cells MC may be two-dimensionally arranged in rows and columns. Although one memory cell stack (MCA) is shown in this embodiment, embodiments of the present invention are not limited thereto. A plurality of memory cell stacks (MCAs) may be provided and vertically stacked.

Each of the memory cells MC may include a selection element SW and a variable resistance structure VR. The selection element SW and the variable resistance structure VR may be electrically connected to each other between a pair of conductive lines CL1 and CL2 connected thereto.

As an example, the selection element SW and the variable resistance structure VR included in each of the memory cells MC are electrically connected to each other between the corresponding first conductive line CL1 and the corresponding second conductive line CL2. can be connected Here, the first conductive line CL1 may be a word line, and the second conductive line CL2 may be a bit line. In addition, although FIG. 1 shows that a variable resistance structure (VR) is provided on the selection element (SW), embodiments of the present invention are not limited thereto.

A voltage is applied to the variable resistance structure (VR) of the memory cell (MC) through the first conductive line (CL1) and the second conductive line (CL2), so that a current can flow in the variable resistance structure (VR), and the applied voltage Accordingly, the resistance of the variable resistance structure (VR) of the selected memory cell (MC) may change.

According to the change in resistance of the variable resistance structure (VR), the memory cell (MC) can store digital information such as “0” or “1”, and the digital information can be erased from the memory cell (MC). For example, data can be written in the high-resistance state “0” and the low-resistance state “1” in the memory cell (MC). Here, writing from the high-resistance state “0” to the low-resistance state “1” may be referred to as a “set operation,” and writing from the low-resistance state “1” to the high-resistance state “0” may be referred to as a “reset operation.” You can. However, the memory cell MC according to embodiments of the present invention is not limited to the digital information of the illustrated high-resistance state “0” and low-resistance state “1” and can store various resistance states.

The variable resistance structure (VR) may include a material that enables information storage. In the present invention, the variable resistance structure (VR) may include a material whose resistance changes by a magnetic field or spin transfer torque (STT). For example, the variable resistance structure (VR) may have a thin film structure configured to exhibit magnetoresistance properties, and a magnetic tunnel junction (Magnetic Tunnel Junction) including at least one ferromagnetic material and/or at least one antiferromagnetic material. Magnetic Tunnel Junction: MTJ) structure may be included. In this case, the memory cell (MC) may be provided as a memory cell of a magnetoresistive memory device (Magnetic RAM: MRAM).

The selection element (SW) may be configured to selectively control the flow of charge passing through the variable resistance structure (VR). For example, the selection device (SW) may be one of a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field effect transistor, and a PMOS field effect transistor. When the selection element SW is composed of a three-terminal bipolar transistor or MOS field effect transistor, an additional wiring (eg, source line, not shown) may be connected to the selection element SW.

Any memory cell (MC) can be addressed by selecting the first conductive line (CL1) and the second conductive line (CL2), and a predetermined distance between the first conductive line (CL1) and the second conductive line (CL2) By applying a signal to program the memory cell (MC) and measuring the current value through the first conductive line (CL1), information according to the resistance value of the variable resistor constituting the corresponding memory cell (MC) can be read. there is.

Figure 2 is a diagram for explaining memory cells according to embodiments of the present invention.

Referring to FIG. 2, the memory cell MC may include a magnetic tunnel junction (MTJ) as a memory element and a selection transistor SE as a selection element SW. A magnetic tunnel junction (MJT) can be formed to have a thin film structure whose electrical resistance can be changed using a spin transfer process caused by a current passing through it.

According to one embodiment, the magnetic tunnel junction (MTJ) may include a pinned layer (PL), a free layer (FL), and a tunnel barrier layer (TBL) interposed between them. The pinned layer (PL) has a magnetization direction fixed in one direction, and the free layer (FL) has a magnetization direction that can be changed to be parallel or anti-parallel to the magnetization direction of the pinned layer (PL). The electrical resistance of the magnetic tunnel junction (MTJ) may vary depending on the magnetization directions of the pinned layer (PL) and the free layer (FL). When the magnetization directions of the pinned layer (PL) and the free layer (FL) in the magnetic tunnel junction (MTJ) are parallel, the magnetic tunnel junction (MTJ) has a low resistance state, and '0' corresponding to the first data is written. You can. On the other hand, when the magnetization directions of the pinned layer (PL) and the free layer (FL) in the magnetic tunnel junction (MTJ) are antiparallel, the magnetic tunnel junction (MTJ) has a high resistance state and '1' corresponding to the second data. ' can be entered.

The gate electrode of the selection transistor SE may be connected to the corresponding word line WL, the first terminal of the selection transistor SE may be electrically connected to the first conductive line CL1, and the first terminal of the selection transistor SE may be electrically connected to the first conductive line CL1. The second terminal may be electrically connected to the second conductive line CL2 through a magnetic tunnel junction (MTJ). For example, the first conductive line CL1 corresponds to a source line electrically connected to the source of the selection transistor SE, and the second conductive line CL2 corresponds to the drain of the selection transistor SE. It may correspond to a bit line that is entirely connected to . Alternatively, the first conductive line CL1 may correspond to a bit line, and the second conductive line CL2 may correspond to a source line. Data can be written to the magnetic tunnel junction (MJT) by a write voltage applied through the bit line, and data stored in the magnetic tunnel junction (MJT) can be read by a read voltage applied through the bit line.

In this example, the free layer FL is shown as connected to the second conductive line CL2 and the fixed layer PL is shown as connected to the selection transistor SE, but the present invention is not limited thereto. According to another embodiment, unlike shown, the fixed layer PL may be connected to the second conductive line CL2 and the free layer FL may be connected to the selection transistor SE. Hereinafter, the magnetic tunnel junction (MTJ) will be described in detail with reference to FIGS. 3A and 3B.

3A and 3B are conceptual diagrams for explaining magnetic tunnel junction according to embodiments of the present invention.

The electrical resistance of the magnetic tunnel junction (MTJ) may depend on the magnetization directions of the pinned layer (PL) and the free layer (FL). For example, the electrical resistance of the magnetic tunnel junction (MTJ) may be much greater when the magnetization directions of the pinned layer (PL) and the free layer (FL) are antiparallel compared to when the magnetization directions of the pinned layer (PL) and the free layer (FL) are parallel. As a result, the electrical resistance of the magnetic tunnel junction (MTJ) can be adjusted by changing the magnetization direction of the free layer (FL), which can be used as a data storage principle in the magnetic memory device according to the present invention.

Referring to FIG. 3A , the pinned layer PL and the free layer FL may be magnetic layers for forming a horizontal magnetization structure in which the magnetization direction is substantially parallel to the top surface of the tunnel barrier layer TBL. In this case, the pinned layer PL may include a layer containing an anti-ferromagnetic material and a layer containing a ferromagnetic material. According to one embodiment, the layer containing an antiferromagnetic material may include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr. According to another embodiment, the layer including an antiferromagnetic material may include at least one selected from rare metals. Rare metals may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). Meanwhile, the layer containing a ferromagnetic material contains at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O12. It can be included.

The free layer (FL) may include a material having a changeable magnetization direction. The free layer (FL) may include a ferromagnetic material. As an example, the free layer (FL) is at least one selected from FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O12 may include.

The free layer (FL) may be composed of multiple layers. As an example, it may include a plurality of layers containing a ferromagnetic material and a layer containing a non-magnetic material interposed between the layers. In this case, the layers containing a ferromagnetic material and the layer containing a non-magnetic material may constitute a synthetic antiferromagnetic layer. Synthetic antiferromagnetic layers can reduce the critical current density of magnetic memory devices and improve thermal stability.

The tunnel barrier layer (TBL) is made of magnesium (Mg) oxide, titanium (Ti) oxide, aluminum (Al), magnesium-zinc (MgZn) oxide, magnesium-boron (MgB) oxide, and titanium (Ti) nitride. and at least one of vanadium (V) nitride. As an example, the tunnel barrier layer (TBL) may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier layer (TBL) may include multiple layers. The tunnel barrier layer (TBL) may be formed using a chemical vapor deposition (CVD) process.

Referring to FIG. 3B, the pinned layer PL and the free layer FL may have a perpendicular magnetization structure in which the magnetization direction is substantially perpendicular to the top surface of the tunnel barrier layer TBL. In this case, each of the fixed layer (PL) and the free layer (FL) may include at least one of a material having an L10 crystal structure, a material having a close-packed hexagonal lattice, and an amorphous Rare-Earth Transition Metal (RE-TM) alloy. there is. As an example, each of the fixed layer (PL) and the free layer (FL) may be at least one of materials having an L10 crystal structure including Fe50Pt50, Fe50Pd50, Co50Pt50, Co50Pd50, and Fe50Ni50. In contrast, each of the fixed layer (PL) and the free layer (FL) has a dense hexagonal lattice of 10 to 45 at. It may include a cobalt-platinum (CoPt) disordered alloy or a Co3Pt ordered alloy having a platinum (Pt) content of %. In contrast, each of the fixed layer (PL) and the free layer (FL) contains at least one selected from iron (Fe), cobalt (Co), and nickel (Ni) and rare earth metals terbium (Tb), dysprosium (Dy), and gadolinium ( It may include at least one selected from amorphous RE-TM alloys containing at least one of Gd).

The pinned layer (PL) and the free layer (FL) may include a material having interface perpendicular magnetic anisotropy. Interfacial perpendicular magnetic anisotropy refers to a phenomenon in which a magnetic layer with intrinsic horizontal magnetization characteristics has a perpendicular magnetization direction due to the influence from the interface with another adjacent layer. Here, the intrinsic horizontal magnetization characteristic means that in the absence of external factors, the magnetic layer has a magnetization direction parallel to its widest surface. For example, when a magnetic layer having intrinsic horizontal magnetization characteristics is formed on a substrate and there are no external factors, the magnetization direction of the magnetic layer may be substantially parallel to the top surface of the tunnel barrier layer (TBL).

As an example, each of the fixed layer (PL) and the free layer (FL) may include at least one of cobalt (Co), iron (Fe), and nickel (Ni). In addition, each of the fixed layer (PL) and free layer (FL) is made of boron (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), silicon (Si), It may further include at least one of non-magnetic materials including silver (Ag), gold (Au), copper (Cu), carbon (C), and nitrogen (N). As an example, each of the fixed layer (PL) and the free layer (FL) includes CoFe or NiFe, and may further include boron (B). In addition, in order to lower the saturation magnetization amount of the fixed layer (PL) and free layer (FL), each of the fixed layer (PL) and free layer (FL) is made of titanium (Ti), aluminum (Al), silicon (Si), and magnesium. It may further include at least one of (Mg), tantalum (Ta), and silicon (Si).

Figure 4 is a cross-sectional view illustrating a variable resistance memory device according to an embodiment of the present invention.

Referring to FIG. 4, a substrate 100 may be provided. The substrate 100 may be, for example, a semiconductor substrate such as a silicon substrate, germanium substrate, or silicon-germanium substrate. The substrate 100 may be provided with selection transistors SE corresponding to selection elements SW (see FIG. 1) of the memory cells MC.

A lower interlayer insulating film 110 covering the selection transistors SE may be disposed on the substrate 100 . Contact plugs 112 electrically connected to the selection transistors SE may be provided within the lower interlayer insulating layer 110. Contact plugs 112 may include metal (eg, tungsten, or copper) or conductive metal nitride (eg, titanium nitride, tantalum nitride, or tungsten nitride). The lower interlayer insulating film 110 may include silicon oxide or silicon nitride.

Lower conductive lines (not shown) may be disposed within the lower interlayer insulating film 110. Lower conductive lines (not shown) may include the same material as the contact plugs 112 . The lower conductive lines (not shown) may correspond to the first conductive line CL1 described with reference to FIG. 2 . In this embodiment, one interlayer insulating film is shown, but this is for convenience of explanation and the present invention is not limited thereto. A plurality of interlayer insulating films (not shown) including contact plugs and connection conductive patterns may be stacked on the substrate 100 . Additionally, a peripheral circuit (not shown) including transistors, contacts, wiring, etc. may be formed on the substrate 100.

Variable resistance structures VR electrically connected to the contact plugs 112 may be disposed on the lower interlayer insulating film 110 . According to embodiments of the present invention, each of the variable resistance structures VR includes a lower electrode 114, a magnetic tunnel junction (MTJ), a capping pattern 116, a stress application pattern 118, and an upper electrode sequentially stacked. It may include (120).

The lower electrode 114 may be connected to the contact plug 112. The lower electrode 114 may have a larger width than the contact plug 112 . For example, the lower electrode 114 may include Ti, TiN, Ta, TaN, W, WN, or a combination thereof. In one embodiment, the lower electrode 114 may include a TiN layer.

A magnetic tunnel junction (MTJ) may be disposed on the lower electrode 114. The magnetic tunnel junction (MTJ) may include a fixed layer pattern (PLc), a free layer pattern (FLc), and a tunnel barrier layer pattern (TBLc) sandwiched between them. In this example, the fixed layer pattern PLc is shown as being in contact with the lower electrode 114, but the present invention is not limited thereto. According to another embodiment, unlike shown, the free layer pattern (FLc) may contact the lower electrode 114, and the fixed layer pattern (PLc) may contact the capping layer 116. The fixed layer pattern (PLc), tunnel barrier layer pattern (TBLc), and free layer pattern (FLc) of the magnetic tunnel junction (MTJ) are the fixed layer (PL) and free layer (FL) described with reference to FIGS. 2, 3A, and 3B, respectively. ) and the tunnel barrier layer (TBL), so detailed description thereof will be omitted.

A capping pattern 116 may be disposed on the magnetic tunnel junction (MTJ). The capping pattern 116 may include a metal oxide such as RuO, MgO, VO, WO, VdO, TaO, HfO, MoO, or a combination thereof. As an example, the capping pattern 116 may include a dielectric layer such as a RuO layer.

A stress application pattern 118 may be disposed on the capping pattern 116. That is, the stress application pattern 118 may be interposed between the capping pattern 116 and the upper electrode 120. The lower surface of the stress applying pattern 118 may be in direct contact with the upper surface of the capping pattern 116, and the upper surface of the stress applying pattern 118 may be in direct contact with the lower surface of the upper electrode 120. there is. In one embodiment, the thickness of the stress application pattern 118 may be thicker than the capping pattern 116 and thinner than the upper electrode 120. For example, the thickness of the stress application pattern 118 may be 4 nm to 60 nm. At this time, the thickness of the capping pattern 116 may be smaller than the thickness of the stress application pattern 118, and the thickness of the upper electrode 120 may be greater than the thickness of the stress application pattern 118.

The stress application pattern 118 may include a conductive material having tensile stress. For example, the stress application pattern 118 may include a metal nitride such as TiN, TaN, WN, or a combination thereof. In one embodiment, the stress application pattern 118 may be a TiN layer. The stress application pattern 118 may have a tensile stress of 1 GPa to 4 GPa. The stress application pattern 118 may provide tensile stress to the MTJ, thereby improving the magnetic and electrical properties of the MTJ.

The upper electrode 120 may be disposed on the stress application pattern 118 . For example, the upper electrode 120 may include Ti, TiN, Ta, TaN, W, WN, or a combination thereof. In one embodiment, the upper electrode 120 may include a TiN layer.

The sequentially stacked lower electrode 114, magnetic tunnel junction (MTJ), capping pattern 116, stress application pattern 118, and upper electrode 120 correspond to the variable resistance structure (VR) described with reference to FIG. 1. You can.

According to embodiments of the present invention, the width of the magnetic tunnel junction (MTJ) of the variable resistance structure (VR) may be smaller than the widths of other layers. For example, the width of the fixed layer pattern (PLc), tunnel barrier layer pattern (TBLc), and free layer pattern (FLc) of the magnetic tunnel junction (MTJ) may be smaller than the width of the capping pattern 116 and the stress application pattern 118. . In other words, one side of the capping pattern 116 and the stress application pattern 118 are coplanar, while one side of the magnetic tunnel junction (MTJ) adjacent to the one side is the capping pattern 116 and the stress application pattern. It may have a shape that is not aligned with the sides of (118) and is indented inward. In this way, as the stress application pattern 118 has a width larger than the magnetic tunnel junction (MTJ), the efficiency of applying tensile stress can be increased.

A protection pattern 132 may be provided on the sidewalls of the variable resistance structure VR. The protection pattern 132 covers the sidewalls of the variable resistance structure VR and extends onto the lower interlayer insulating film 110 to be connected to the protection pattern 132 covering the sidewalls of the adjacent variable resistance structure VR. The protection pattern 132 may expose the upper surface of the upper electrode 120. The protection pattern 132 may include silicon nitride. The protection pattern 132 may function to protect the surface of the variable resistance structure VR from oxidation or damage.

An upper interlayer insulating film 140 may be provided on the lower interlayer insulating film 110 . The upper interlayer insulating film 140 may fill the space between the variable resistance structures VR where the protection pattern 132 is formed. The upper interlayer insulating film 140 may include silicon oxide or silicon nitride. The upper surfaces of the upper interlayer insulating film 140, the protection pattern 132, and the upper electrode 120 may be coplanar with each other. That is, the upper surfaces of the upper interlayer insulating film 140, the protection pattern 132, and the upper electrode 120 may have the same height.

An upper conductive line 150 may be disposed on the upper electrode 120. The upper conductive line 150 may correspond to or be connected to a bit line. The upper conductive line 150 may include a metal (eg, tungsten, or copper) or a conductive metal nitride (eg, titanium nitride, tantalum nitride, or tungsten nitride).

Hereinafter, with reference to FIGS. 5 to 16, a method of manufacturing a variable resistance memory device according to an embodiment of the present invention will be described.

5 to 16 are cross-sectional views for explaining a method of manufacturing a variable resistance memory device according to an embodiment of the present invention.

Referring to FIG. 5 , a lower interlayer insulating film 110 may be formed on the substrate 100 to cover the selection transistors SE. The selection transistors SE may be formed to include, for example, an active region, source/drain regions, a gate dielectric layer, and a gate electrode.

Contact plugs 112 connected to the selection transistors SE may be formed in the lower interlayer insulating layer 110. For example, the contact plugs 112 may be formed by forming contact holes exposing one terminal of the selection transistors SE in the lower interlayer insulating film 110 and filling the contact holes with a conductive material. The conductive material may include a metal (eg, tungsten, or copper) or a conductive metal nitride (eg, titanium nitride, tantalum nitride, or tungsten nitride).

A lower electrode layer 113 may be formed on the lower interlayer insulating film 110 on which the contact plugs 112 are formed. The lower electrode layer 113 may include Ti, TiN, Ta, TaN, W, WN, or a combination thereof. In one embodiment, the lower electrode layer 113 may include a TiN layer.

Referring to FIG. 6, a magnetic tunnel junction thin film layer (MTJL) including a pinned layer (PLa), a tunnel barrier layer (TBLa), and a free layer (FLa) may be formed on the lower electrode layer 113. Each of the pinned layer (PLa), tunnel barrier layer (TBLa), and free layer (FLa) is made of the same material as the pinned layer (PL), tunnel barrier layer (TBL), and free layer (FL) described with reference to Figure 3a or 3b. Since it may be included, detailed description thereof is omitted. In this example, the fixed layer (PLa) is shown as being in contact with the lower electrode layer 113, but the present invention is not limited thereto. According to another embodiment, the free layer (FLa) may be in contact with the lower electrode layer 113, and the fixed layer (PLa) may be formed to be spaced apart from the free layer (FLa) with the tunnel barrier layer (TBLa) interposed therebetween.

A capping layer 115 may be formed on the magnetic tunnel junction thin film layer (MTJL). The capping layer 115 may include a metal oxide such as RuO, MgO, VO, WO, VdO, TaO, HfO, MoO, or a combination thereof. As an example, the capping layer 115 may include a dielectric layer such as a RuO layer.

A stress-inducing layer 117 may be formed on the capping layer 115. The stress-inducing layer 117 may directly contact the upper surface of the capping layer 115. The stress-inducing layer 117 may have tensile stress. In one embodiment, the thickness of the stress-inducing layer 117 may be thicker than the capping layer 115. For example, the thickness of the stress-inducing layer 117 may be 4 nm to 60 nm. The stress-inducing layer 117 is formed using a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a combination thereof. can be formed. As an example, the stress-inducing layer 117 may be formed using a PVD method. The stress-inducing layer 117 may include a metal nitride such as TiN, TaN, WN, or a combination thereof. In one embodiment, the stress-inducing layer 117 may be a TiN layer.

Referring to FIG. 7, a heat treatment process may be performed to crystallize the magnetic tunnel junction thin film layer (MTJL). The heat treatment process may be performed in a vacuum or low pressure atmosphere at a temperature of 350°C to 400°C for 50 to 70 minutes. For example, the heat treatment process for crystallizing the magnetic tunnel junction thin film layer (MTJL) is performed by treating the substrate 100 on which the stress-inducing layer 117 and the magnetic tunnel junction thin film layer (MTJL) are formed for about 1 hour at a temperature of about 375° C. in a vacuum or low pressure chamber. ) may include heat treatment.

Referring to FIG. 8, the upper electrode layer 119 may be formed on the stress-inducing layer 117 after performing the heat treatment process. For example, the upper electrode layer 119 may include Ti, TiN, Ta, TaN, W, WN, or a combination thereof. In one embodiment, the upper electrode layer 119 may include a TiN layer.

Next, mask patterns 125 may be formed on the upper electrode layer 119. The mask patterns 125 may include a photoresist pattern, a hardmask pattern, or a combination thereof.

Referring to FIG. 9, the upper electrode layer 119, the stress-inducing layer 117, the capping layer 115, and the free layer (FLa) are etched in a first etching process using the mask patterns 125 as an etch mask to form the upper electrode layer 119. An electrode 120, a stress application pattern 118, a capping pattern 116, and a preliminary free layer pattern (FLb) may be formed. The first etching process may include an anisotropic etching process. The upper electrode 120, the stress applying pattern 118, the capping pattern 116, and the preliminary free layer pattern (FLb) may have one side surfaces aligned, and the upper surface of the tunnel barrier layer (TBLa) may be exposed. .

Referring to FIG. 10 , the free layer pattern FLc may be formed by selectively etching the preliminary free layer pattern FLb through a second etching process. The second etching process may include an isotropic etching process. As a result of the second etching process, the side surfaces of the preliminary free layer pattern (FLb) are selectively etched to form a free layer pattern ( FLc) may be formed. That is, the side surface of the free layer pattern FLc may not be aligned with one side surface of the upper electrode 120, the stress application pattern 118, and the capping pattern 116, but may be offset (or indented) inward.

Referring to FIG. 11 , the tunnel barrier layer TBLa may be etched through a third etching process using the mask patterns 125 as an etch mask to form a preliminary tunnel barrier layer pattern TBLb. The third etching process may include an anisotropic etching process, and as a result of the third etching process, a preliminary tunnel barrier has a width substantially equal to the width of the upper electrode 120, the stress application pattern 118, and the capping pattern 116. The layer pattern TBLb may be formed, and the upper surface of the fixed layer PLa may be exposed.

Referring to FIG. 12 , the tunnel barrier layer pattern (TBLc) may be formed by selectively etching the preliminary tunnel barrier layer pattern (TBLb) in the fourth etching process. The fourth etching process may include an isotropic etching process. As a result of the fourth etching process, the side surfaces of the preliminary tunnel barrier layer pattern (TBLc) are selectively etched to form a tunnel barrier layer having a width smaller than the width of the upper electrode 120, the stress application pattern 118, and the capping pattern 116. A pattern (TBLc) may be formed.

Referring to FIG. 13 , the preliminary pinned layer pattern PLb may be formed by etching the pinned layer PLa through a sixth etching process using the mask patterns 125 as an etch mask. The sixth etching process may include an anisotropic etching process, and as a result of the sixth etching process, a preliminary pinned layer pattern having a width substantially equal to the width of the upper electrode 120, the stress application pattern 118, and the capping pattern 116 (PLb) may be formed, and the upper surface of the lower electrode layer 113 may be exposed.

Referring to FIG. 14 , the pinned layer pattern PLc may be formed by selectively etching the preliminary pinned layer pattern PLb through the seventh etching process. The seventh etching process may include an isotropic etching process. As a result of the seventh etching process, the side surfaces of the preliminary pinned layer pattern (PLb) are selectively etched to form a pinned layer pattern (PLc) having a width smaller than the width of the upper electrode 120, the stress application pattern 118, and the capping pattern 116. can be formed, and thus the formation of a magnetic tunnel junction (MTJ) can be completed.

Referring to FIG. 15 , the lower electrode 114 may be formed by etching the lower electrode layer 113 using the eighth etching process using the mask patterns 125 as an etch mask. The eighth etching process may include an anisotropic etching process, and as a result of the eighth etching process, a lower electrode ( 114) may be formed, and the upper surface of the lower interlayer insulating film 110 may be exposed.

As a result, the formation of the variable resistance structure (VR) including the sequentially stacked lower electrode 114, magnetic tunnel junction (MTJ), capping pattern 116, stress application pattern 118, and upper electrode 120 will be completed. You can.

Referring to FIG. 16 , the mask patterns 125 may be removed, and a protective film 130 may be formed to conformally cover the surface of the variable resistance structure VR. The protective film 130 may be formed through a chemical vapor deposition method using plasma. The protective film 130 may include, for example, silicon nitride. Preferably, the protective film 130 may be formed by a plasma enhanced-CVD method using plasma using a silicon source gas, a nitrogen source gas not containing hydrogen, and a dissociation gas. The protective film 130 may be formed to prevent the sides of the magnetic tunnel junction (MTJ) from being oxidized in a subsequent process.

Referring again to FIG. 4, the upper interlayer insulating film 140 is formed between the variable resistance structures VR on which the protective film 130 is formed, and a planarization process is performed to expose the upper surface of the upper electrode 120. You can. As a result, a protection pattern 132 exposing the upper electrode 120 may be formed on the sidewalls of the variable resistance structure VR. The planarization process may include, for example, a chemical mechanical polish (CMP) process. The upper surfaces of the upper interlayer insulating film 140, the protection pattern 132, and the upper electrode 120 may have the same height. The upper interlayer insulating film 140 may include silicon oxide or silicon nitride.

Subsequently, an upper conductive line 150 connected to the upper electrode 120 may be formed. The upper conductive line 150 may be formed by forming an upper conductive film on the substrate 100 on which the protection pattern 132 is formed and then patterning it. The upper conductive layer may include a metal (eg, tungsten, or copper) or a conductive metal nitride (eg, titanium nitride, tantalum nitride, or tungsten nitride).

A variable resistance memory device can be completed by performing the above-described processes.

According to embodiments of the present invention, as the stress applying pattern 118 having tensile stress is disposed on the magnetic tunnel junction (MTJ), the coercive force of the magnetic tunnel junction (MTJ) can be increased and the switching current can be improved. . In particular, as the stress application pattern 118 has a larger width than the layers of the magnetic tunnel junction (MTJ), the stress application efficiency is improved, the magnetic and electrical properties of the magnetic tunnel junction (MTJ) are further strengthened, and retention Retention Fail Bits can be reduced.

As a result, it may be possible to provide a variable resistance element with improved electrical characteristics and reliability.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will understand that you can. Therefore, the embodiments and application examples described above should be understood as illustrative in all respects and not restrictive.

Claims (3)

first conductive lines;
second conductive lines intersecting the first conductive lines; and
Comprising memory cells provided at intersections between the first conductive lines and the second conductive lines, respectively,
Each of the memory cells includes a selection element and a variable resistance structure,
The variable resistance structure includes a lower electrode, a magnetic tunnel junction, a capping pattern, a stress application pattern, and an upper electrode stacked in order,
The magnetic tunnel junction includes a fixed layer pattern, a free layer pattern, and a tunnel barrier layer pattern sandwiched between them,
The stress application pattern includes a conductive material having tensile stress,
A width of the fixed layer pattern, the free layer pattern, and the tunnel barrier layer pattern is smaller than the width of the capping pattern and the stress application pattern,
One side of the capping pattern and the stress application pattern are coplanar,
A variable resistance memory device wherein one side of the magnetic tunnel junction adjacent to the one side of the capping pattern and the stress application pattern is not aligned with the one side but is indented inward. delete According to claim 1,
It further includes a protection pattern that covers side walls of the variable resistance structure and exposes an upper surface of the upper electrode,
A variable resistance memory element wherein the upper electrode is connected to a corresponding second conductive line.