KR102654457B1 - Semiconductor device and method manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device containing silicon carbide and a method of manufacturing the same. The semiconductor device according to one embodiment includes a substrate; an n-type layer located on the first side of the substrate; a first trench and a second trench formed in the n-type layer; a gate located within the first trench; an n-type region and a first source electrode located within the second trench; a second source electrode positioned above the gate and the first source electrode; and a drain electrode located on a second side of the substrate, wherein the first source electrode contacts the n-type layer in the second trench to form a Schottky junction.

Description

Semiconductor device and method of manufacturing the same {SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING THE SAME}

The present invention relates to a semiconductor device containing silicon carbide (SiC) and a method of manufacturing the same.

Power semiconductor devices especially require low on-resistance or low saturation voltage in order to allow very large currents to flow while reducing power loss in a conductive state. In addition, characteristics that can withstand the high reverse voltage of the PN junction applied to both ends of the power semiconductor device in the off state or at the moment the switch is turned off, that is, high breakdown voltage characteristics, are basically required.

Multiple power semiconductor devices that satisfy basic electrical and physical conditions are modularized into one package, and the number and electrical specifications of power semiconductor devices inside the power semiconductor module can be changed depending on the conditions required by the system.

Generally, a three-phase power semiconductor module is used to generate Lorentz force to drive a motor. In other words, the driving state of the motor is determined by the three-phase power semiconductor module controlling the current and power injected into the motor.

Existing silicon insulated gate bipolar transistors (IGBTs) and silicon diodes were applied inside these three-phase power semiconductor modules, but recently, power consumption occurring in three-phase modules has been minimized and module switching has been minimized. The trend is to apply silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) and silicon carbide diodes with the goal of increasing speed.

When connecting a silicon IGBT or silicon carbide MOSFET with a separate diode, multiple wiring combinations are made, and the presence of parasitic capacitance and inductance due to these wiring reduces the switching speed of the module.

The embodiments are intended to provide a semiconductor device that can reduce the overall device area and module volume within a three-phase power semiconductor module and increase the switching speed of the module by reducing the number of wires inside the module.

A semiconductor device according to an embodiment includes a substrate; an n-type layer located on the first side of the substrate; a first trench and a second trench formed in the n-type layer; a gate located within the first trench; an n-type region and a first source electrode located within the second trench; a second source electrode positioned above the gate and the first source electrode; and a drain electrode located on a second side of the substrate, wherein the first source electrode contacts the n-type region in the second trench to form a Schottky junction.

The substrate may include an n+ type hydrocarbon.

The first source electrode may include Schottky metal, and the second source electrode may include ohmic metal.

a p-type region located above the n-type layer; an n+ type region located above the p type region and adjacent to a side of the first trench; a p+ type region located above the p type region and adjacent to a side of the second trench; And it may further include a p shield region located below the first trench.

The second source electrode may contact the n+ type region and the p+ type to form an ohmic junction.

The n- type layer, the n+ type region, the p+ type region, the p type region, the gate, the p shield region, the second source electrode, and the drain electrode may be driven by a MOSFET.

The n-type layer, the n-type region, the first source electrode, the second source electrode, and the drain electrode may be driven as diodes.

The second source electrode may be a cathode electrode, and the drain electrode may be an anode electrode.

a first insulating film located within the first trench; It may further include a second insulating layer located on the gate.

The n-type region may have a higher ion doping concentration than the n-type layer.

A method of manufacturing a semiconductor device according to an embodiment includes sequentially forming an n-type layer and a p-type region on a first surface of a substrate; forming a p+ type region and an n+ type region adjacent to each other on the p type region; forming a first trench by etching the n+ type region, the p type region and the n- type layer, and forming a second trench by etching the p+ type region, the p type region and the n- type region; forming a p-shield region below the lower surface of the first trench; forming a first insulating film inside the first trench, forming a gate on the first insulating film, and forming a second insulating film on the gate; forming an n-type region and a first source electrode inside the second trench; forming a second source electrode on the p+ type region, the n+ type region, the first source electrode, and the second insulating layer; and forming a drain electrode on a second side of the substrate, wherein the first source electrode contacts the n-type region in the second trench to form a Schottky junction.

The substrate may include an n+ type hydrocarbon.

The first source electrode may include Schottky metal, and the second source electrode may include ohmic metal.

The second source electrode may contact the n+ type region and the p+ type to form an ohmic junction.

The second source electrode may be a cathode electrode, and the drain electrode may be an anode electrode.

According to embodiments, by forming the MOSFET and the diode on one chip, the total chip area and module size within the module can be reduced, and the number of wires inside the module can be reduced to reduce switching loss. Accordingly, power consumption occurring inside the module can be reduced.

Additionally, since the diode can be formed on one chip in the MOSFET manufacturing process, a new process is not required, making the manufacturing process simple and economical.

FIG. 1 is a diagram briefly illustrating an example of a cross section of a semiconductor device according to an embodiment.
Figure 2 is a diagram showing an operating state when a semiconductor device operates as a MOSFET according to an embodiment.
Figure 3 is a diagram showing an operating state when a semiconductor device operates as a diode, according to an embodiment.
Figure 4 is a diagram showing an operating state when a semiconductor device is in an off state, according to an embodiment.
Figure 5 is a diagram showing simulation results of electron and current density when a semiconductor device operates as a MOSFET according to an embodiment.
Figure 6 is a diagram showing simulation results of electron and current density when a semiconductor device operates as a diode according to an embodiment.
7 to 14 are diagrams briefly illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.
FIG. 15 is a diagram briefly illustrating an example of a cross section of a semiconductor device according to another embodiment.
FIG. 16 is a diagram briefly illustrating an example of a cross section of a semiconductor device according to another embodiment.

Hereinafter, with reference to the attached drawings, various embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. The invention may be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts that are not relevant to the description are omitted, and identical or similar components are assigned the same reference numerals throughout the specification.

In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, so the present invention is not necessarily limited to what is shown.

In the drawing, the thickness is enlarged to clearly express various layers and regions. And in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated. When a part of a layer, membrane, region, plate, etc. is said to be “on” another part, this includes not only being “directly on” the other part, but also cases where there is another part in between.

In addition, throughout the specification, when a part is said to "include" a certain component, this means that it may further include other components rather than excluding other components, unless specifically stated to the contrary. In addition, throughout the specification, “on” means located above or below the object part, and does not necessarily mean located above the direction of gravity.

Below, a detailed structure of a semiconductor device according to an embodiment will be described.

FIG. 1 is a diagram briefly illustrating an example of a cross section of a semiconductor device according to an embodiment.

Referring to FIG. 1, a semiconductor device according to an embodiment includes a substrate 100, an n- type layer 200, a p-type region 300, a p shield region 310, a p+-type region 320, and an n+-type region. (400), n-type region 410, first insulating film 500, second insulating film 510, gate 600, first source electrode 800, second source electrode 850, and drain electrode 900 ) includes.

The substrate 100 may include n+ type hydrocarbon (SiC).

The n-type layer 200 is located on the top surface (first surface) of the substrate 100. A first trench 251 and a second trench 252 are formed in the n- type layer 200.

A p-type region 300 is located on the n-type layer 200, and the p-type region 300 is located adjacent to the side of the first trench 251 and the second trench 252. The p shield area 310 is located below the first trench 251. The p+ type region 320 is located above the p type region 300, and the p+ type region 320 is located adjacent to the side of the second trench 252. Here, the p-type refers to a semiconductor region in which an intrinsic semiconductor of a tetravalent element such as silicon (Si) is doped with a trivalent element (boron (B), aluminum (Al), etc.) as an impurity. The p shield region 310 is a region with a higher ion doping concentration than the p+ type region 320, and the p+ type region 320 is a region with a higher ion doping concentration than the p type region 300.

The n+ type region 400 is located on the p type region 300 and adjacent to the side of the first trench 251. The n+ type region 400 is located on the same layer as the p+ type region 320. The n-type region 410 is located within the second trench 252 and adjacent to the sides of the p-type region 300 and the p+-type region 320. Here, n-type refers to a semiconductor region in which an intrinsic semiconductor of a tetravalent element such as silicon (Si) is doped with a pentavalent element (phosphorus (P), arsenic (As), etc.) as an impurity. The n+ type region 400 is a region with a higher ion doping concentration than the n-type region 410, and the n-type region 410 is a region with a higher ion doping concentration than the n- type layer 200.

The first insulating film 500 is located within the first trench 251. The first insulating layer 500 may include silicon oxide (SiOx). The first insulating film 500 extends to a portion of the top surface of the n+ type region 400.

The gate 600 is formed in the first trench 251 and is located on the first insulating film 500. The gate 600 may include poly-crystalline silicon or a metal such as aluminum (Al), copper (Cu), or titanium (Ti). The gate 600 is located on the first insulating film 500 located on a portion of the top surface of the n+ type region 400. That is, the gate 600 partially overlaps the top surface of the n+ type region 400.

The second insulating film 510 covers the gate 600 . The second insulating film 510 may extend to the top and side surfaces of the gate 600, contact the first insulating film 500, and cover the gate 600.

The first source electrode 800 is formed in the second trench 252 and is located on the n-type region 410. The first source electrode 800 may include Schottky metal. The first source electrode 800 contacts the n-type region 410 to form a Schottky junction.

The second source electrode 850 is located on the p+ type region 320, the n+ type region 400, the first source electrode 800, and the second insulating film 510. The second source electrode 850 may include an ohmic metal. The second source electrode 850 contacts the p+ type region 320 and the n+ type region 400 to form an ohmic junction.

The first source electrode 800 and the second source electrode 850 are made of different metals, but since they are in direct contact, they can be driven by the same source electrode to which the same voltage is applied.

The drain electrode 900 is located on the lower surface (second surface) of the substrate 100. In this embodiment, the drain electrode 900 includes ohmic metal, but may include Schottky metal depending on the embodiment.

The semiconductor device according to this embodiment includes a metal oxide semiconductor field effect transistor (MOSFET) and a diode, and MOSFET operation and diode operation are performed. At this time, the MOSFET operation and the diode region operation are performed separately depending on the voltage application state.

The MOSFET includes a second source electrode 850, n+ type region 400, p+ type region 320, p type region 300, gate 600, p shield region 310, n- type layer 200, and It can be driven including the drain electrode 900. When the semiconductor device operates as a MOSFET, a channel is formed in the p-type region 300 adjacent to the first trench 251. Since the p-shield area 310 surrounds the corners of the first trench 251, concentration of electric fields in the first trench 251 can be alleviated. Accordingly, the breakdown voltage of the semiconductor device may increase and leakage current may decrease.

The diode may be driven by including a second source electrode 850, a first source electrode 800, an n-type region 410, an n-type layer 200, and a drain electrode 900. When the semiconductor device according to this embodiment is driven by a diode, the second source electrode 850 is implemented as an anode electrode, and the drain electrode 900 is implemented as a cathode electrode.

In this way, the semiconductor device according to this embodiment forms the MOSFET and diode on one chip, thereby reducing the total chip area and module size within the module, and reducing the number of wires inside the module, thereby reducing switching loss. . Additionally, power consumption occurring inside the module can be reduced.

Below, we will look at the operation of the semiconductor device according to this embodiment.

First, we will look at the operating conditions of semiconductor devices.

The semiconductor device operates in an off state under the following conditions.

VGS < VTH, VDS ≥ 0V

Under the following conditions, the semiconductor device operates as a diode.

VGS < VTH, VDS < 0V

Under the following conditions, the semiconductor device operates as a MOSFET.

VGS ≥ VTH, VDS > 0V

Here, VTH is the threshold voltage of the MOSFET, VGS is VG - VS, and VDS is VD - VS. VG is the voltage applied to the gate electrode, VD is the voltage applied to the drain electrode, and VS is the voltage applied to the source electrode.

FIG. 2 is a diagram showing an operating state when a semiconductor device operates as a MOSFET according to an embodiment, FIG. 3 is a diagram showing an operating state when a semiconductor device operates as a diode according to an embodiment, and FIG. 4 is a diagram showing an operating state when a semiconductor device according to an embodiment is in an off state. In addition, FIG. 5 is a diagram showing simulation results of electron and current density when the semiconductor device according to FIG. 1 operates as a MOSFET, and FIG. 6 shows the electron and current density when the semiconductor device according to FIG. 1 operates as a diode. This is a diagram showing the simulation results.

Referring to FIG. 2, when a semiconductor device operates as a MOSFET, electrons (e-) move from the second source electrode 850 to the drain electrode 900. Here, electrons (e-) emitted from the second source electrode 850 move to the drain electrode 900 through the n+ type region 400, p type region 300, and n- type layer 200. Accordingly, current flows from the drain electrode 900 to the second source electrode 850.

Referring to FIG. 3, when a semiconductor device operates as a diode, electrons (e-) move from the drain electrode 900 to the first source electrode 800. Here, electrons (e-) emitted from the drain electrode 900 move to the first source electrode 800 through the n- type layer 200 and the n-type region 410. Accordingly, current flows from the first source electrode 800 to the drain electrode 900.

Referring to FIG. 4, when the semiconductor device is in an off state, current does not flow, and the n-type layer 200 is formed as a depletion layer.

Referring to FIG. 5, it can be seen that when a semiconductor device operates as a MOSFET, electrons/current flow in the direction of the channel region of the MOSFET. Additionally, it can be seen that electrons/current do not flow through the Schottky junction surface.

Referring to FIG. 6, when a semiconductor device operates as a diode, it can be seen that electrons/current flow through the Schottky junction surface. Additionally, it can be seen that electrons/current do not flow into the channel area of the MOSFET.

Below, with reference to Table 1, we will look at the characteristics of the semiconductor device according to this embodiment and general semiconductor devices.

In Table 1, the current densities of the semiconductor devices according to Example, Comparative Example 1, and Comparative Example 2 were compared with almost the same breakdown voltage. In addition, the sum of the areas of the conductive parts of the semiconductor devices according to Comparative Examples 1 and 2 was equal to the area of the electric current conducting parts of the other semiconductors in the Examples. In this simulation, the areas of the conductive portions of the semiconductor devices according to Comparative Examples 1 and 2 were each set to 0.5 cm ² , and the areas of the conductive portions of the semiconductors used in the examples were set to 1 cm ² .

breakdown voltage
(V) current density
(A/ ^cm2 ) electrical department
area
@100A( ^mm2 ) Chips
Current-carrying area
( ^cm2 ) amount of current
(A) Comparative Example 1 1462 1022.5 9.78 0.5 511.3 Comparative Example 2 1408 1117.1 8.95 0.5 558.6 line
city
yes diode operation 1450 1704.8 9.88 One 1704.8 MOSFET operation 1012.0 1012.0

Referring to Table 1, the current of the diode device according to Comparative Example 1 was measured at 511.3 A, and the current of the MOSFET device according to Comparative Example 2 was measured at 558.6 A. When operating as a diode, the semiconductor device according to this embodiment was measured at 1704.8 A, and when operating as a MOSFET, it was measured at 1012.0 A. That is, when the semiconductor device according to this embodiment operates as a diode, it can be seen that the amount of current increases by about 233.4% compared to the diode device according to Comparative Example 1, and when the semiconductor device according to this embodiment operates as a MOSFET, , it can be seen that the current amount increases to about 81.2% compared to the MOSFET device according to Comparative Example 2.

Accordingly, it can be seen that the amount of current increases when the semiconductor device according to this embodiment operates as a diode or MOSFET compared to the semiconductor device according to Comparative Examples 1 and 2 in the same area of the conductive part.

In addition, referring to Table 1, looking at the area of the current carrying part for 100A to flow, it can be seen that the diode device according to Comparative Example 1 requires 9.78 mm ² and the MOSFET device according to Comparative Example 2 requires 8.95 mm ² . That is, in order to drive the diode device and the MOSFET device according to the comparative example, a total area of 18.73 mm ² is required. On the other hand, it can be seen that the semiconductor device according to this embodiment requires an area of 9.88 mm ² to drive the diode device and the MOSFET device.

Therefore, it can be seen that when the amount of current is designed to be the same, the area of the conductive part of the semiconductor device according to this embodiment is reduced compared to the semiconductor device according to Comparative Examples 1 and 2.

Below, with reference to FIGS. 1 and 7 to 14 , a method of manufacturing a semiconductor device according to an embodiment will be described.

7 to 14 are diagrams briefly illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

Referring to FIG. 7, a substrate 100 is prepared, and an n-type layer 200 is formed on the upper surface (first surface) of the substrate 100. The substrate 100 may include n+ type silicon carbide (SiC), and the n- type layer 200 may be formed on the first surface of the substrate 100 by epitaxial growth.

Referring to FIG. 8, a p-type region 300 is formed on the n-type layer 200. The p-type region 300 can be formed by implanting p-type ions such as boron (B), aluminum (Al), gallium (Ga), and indium (In) into the n- type layer 200. Additionally, it is not limited to this, and may be formed by epitaxial growth on the n- type layer 200.

Referring to FIG. 9, a p+ type region 320 and an n+ type region 400 are formed on the p type region 300. The p+ type region 320 can be formed by implanting p-type ions such as boron (B), aluminum (Al), gallium (Ga), and indium (In) into the p-type region 300. The n+ type region 400 can be formed by implanting n-type ions such as nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) into the p-type region 300. Here, the ion doping concentration of the p+ type region 320 is higher than that of the p type region 300.

Referring to FIG. 10, the n+ type region 400, p type region 300, and n- type layer 200 are etched to form a first trench 251 and a second trench 252. At this time, the first trench 251 penetrates the n+ type region 400 and the p type region 300 and is formed in the n- type layer 200. The second trench 252 penetrates the p+ type region 320 and the p type region 300 and is formed in the n- type layer 200.

Referring to FIG. 11, a p shield area 310 is formed under the lower surface of the first trench 251. The p shield area 310 uses the insulating material layer pattern as a mask and deposits materials such as boron (B), aluminum (Al), gallium (Ga), and indium (In) on a portion of the corner and bottom surface of the first trench 251. It can be formed by implanting p-type ions. The ion doping concentration of the p shield region 310 is higher than that of the p+ type region 320.

Referring to FIG. 12, a first insulating film 500 is formed inside the first trench 251 and on the n+ type region 400, a gate 600 is formed on the first insulating film 500, and the gate 600 ) is formed to cover the second insulating film 510. The gate 600 may include poly-crystalline silicon or metal. The gate 600 extends to a portion of the upper surface of the first trench 251 and overlaps a portion of the n+ type region 400.

Referring to FIG. 13, an n-type region 410 is formed inside the second trench 252. The n-type region 410 is formed by implanting n-type ions such as nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) into the second trench 252 and the n- type layer 200. You can. Here, the ion doping concentration of the n-type region 410 is higher than that of the n- type layer 200.

Referring to FIG. 14, a first source electrode 800 is formed on the n-type region 410 in the second trench 252, and a p+ type region 320, an n+ type region 400, and a first source electrode ( A second source electrode 850 is formed on the 800 and the second insulating film 510. The first source electrode 800 may include Schottky metal, and the second source electrode 850 may include ohmic metal. The first source electrode 800 and the second source electrode 850 are made of different metals, but since they are in direct contact, they can be driven by the same source electrode to which the same voltage is applied.

Additionally, a drain electrode 900 is formed on the lower surface (second surface) of the substrate 100. The drain electrode 900 may include ohmic metal.

Below, we will look at semiconductor devices according to other embodiments.

FIG. 15 is a diagram briefly showing an example of a cross section of a semiconductor device according to another embodiment, and FIG. 16 is a diagram briefly showing an example of a cross section of a semiconductor device according to another embodiment. Content that is the same as that of the semiconductor device according to the embodiment of FIG. 1 will be omitted, and the differences will be focused on.

Referring to FIG. 15, a semiconductor device according to another embodiment includes a substrate 100, an n- type layer 200, a p-type region 300, a p+-type region 320, an n+-type region 400, and an n-type region. 410, a first insulating film 500, a gate 600, a first source electrode 800, a second source electrode 850, and a drain electrode 900.

The n- type layer 200 is located on the upper surface (first surface) of the substrate 100, and a second trench 252 is formed.

The p-type region 300 is located inside the n-type layer 200 and adjacent to the side of the second trench 252. The p+ type region 320 is located inside the p type region 300 and adjacent to the side of the second trench 252.

The n+ type region 400 is located inside the p type region 300. The n+ type region 400 is located on the same layer as the p+ type region 320, and is located deeper inside the p type region 300 than the p+ type region 320.

The first insulating film 500 is located on a portion of the n- type layer 200, the p-type region 300, and the n+-type region 400. The first insulating layer 500 may include silicon oxide (SiOx).

The gate 600 is located on the first insulating film 500 and overlaps a portion of the n- type layer 200, the p-type region 300, and the n+-type region 400.

The second insulating film 510 covers the gate 600 . The second insulating film 510 may extend to the top and side surfaces of the gate 600, contact the first insulating film 500, and cover the gate 600.

The semiconductor device according to this embodiment includes a second source electrode 850, an n+ type region 400, a p+ type region 320, a p type region 300, a gate 600, an n- type layer 200, and a drain. It can be driven by a MOSFET including the electrode 900.

In addition, a diode including a first source electrode 800, a second source electrode 850, a first source electrode 800, an n-type region 410, an n-type layer 200, and a drain electrode 900. It can be driven.

In this way, the semiconductor device according to this embodiment forms the MOSFET and diode on one chip, thereby reducing the total chip area and module size within the module, and reducing the number of wires inside the module, thereby reducing switching loss. . Additionally, power consumption occurring inside the module can be reduced.

Referring to FIG. 16, a semiconductor device according to another embodiment includes a substrate 100, an n- type layer 200, a p-type region 300, a p shield region 310, a p+-type region 320, and an n+-type region. 400, includes an n-type region 410, a first insulating film 500, a gate 600, a first source electrode 800, a second source electrode 850, and a drain electrode 900.

The first source electrode 800 is located on the n-type region 410 and is located only in a partial area within the second trench 252. The first source electrode 800 may include Schottky metal. The first source electrode 800 contacts the n-type region 410 to form a Schottky junction.

The remaining area of the second trench 252 is filled with the second source electrode 850. The second source electrode 850 may include ohmic metal. Accordingly, the first source electrode 800 and the second source electrode 850 are made of different metals, but when the first source electrode 800 forms a Schottky junction, they are connected to the same source electrode to which the same voltage is applied. It can be driven.

In other words, the semiconductor device according to this embodiment includes a MOSFET and a diode in one chip, and individual MOSFET or diode operation is performed, thereby reducing the overall chip area and module size within the module and reducing the number of wires inside the module. Switching losses can be reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also possible. falls within the scope of rights.

100: substrate 200: n-type layer
300: p-type area 310: p shield area
320: p+ type region 400: n+ type region
410: n-type region 500: first insulating film
510: second insulating film 600: gate
800: first source electrode 850: second source electrode
900: drain electrode

Claims (15)

As a semiconductor device,
Board;
an n-type layer located on the first side of the substrate;
a first trench and a second trench formed in the n-type layer;
a p-type region located above the n-type layer;
an n+ type region located above the p type region and adjacent to a side of the first trench;
a p+ type region located above the p type region and adjacent to a side of the second trench;
a first insulating film located within the first trench;
a gate located within the first trench;
an n-type region and a first source electrode located within the second trench;
a second source electrode positioned above the gate and the first source electrode; and
It includes a drain electrode located on a second side of the substrate,
the first source electrode contacts the n-type region in the second trench to form a Schottky junction,
The n+ type region is located in the same layer as the p+ type region,
The n-type region is located adjacent to the side of the p-type region and the p+-type region,
The first insulating film extends to a portion of the upper surface of the n+ type region,
When the semiconductor device operates as a MOSFET, current flows from the drain electrode to the second source electrode through the n- type layer, the p-type region, and the n+-type region,
When the semiconductor device operates as a diode, current flows from the first source electrode made of a different metal from the second source electrode to the drain electrode through the n-type region and the n-type layer. According to paragraph 1,
The substrate is a semiconductor device containing n+ type hydrocarbon. According to paragraph 1,
The first source electrode includes Schottky metal,
The second source electrode is a semiconductor device including an ohmic metal. According to paragraph 1,
A semiconductor device further comprising a p shield region located below the first trench. According to clause 4,
The second source electrode is in contact with the n+ type region and the p+ type to form an ohmic junction. According to clause 5,
The n- type layer, the n+ type region, the p+ type region, the p type region, the gate, the p shield region, the second source electrode, and the drain electrode are driven by a MOSFET. According to clause 4,
A semiconductor device wherein the n-type layer, the n-type region, the first source electrode, the second source electrode, and the drain electrode are driven by diodes. In clause 7,
The second source electrode is a cathode electrode,
A semiconductor device in which the drain electrode is an anode electrode. According to paragraph 1,
A semiconductor device further comprising a second insulating film positioned on the gate. According to paragraph 1,
A semiconductor device in which the n-type region has a higher ion doping concentration than the n-type layer. As a method of manufacturing a semiconductor device,
sequentially forming an n-type layer and a p-type region on the first side of the substrate;
forming a p+ type region and an n+ type region adjacent to each other on the p type region;
forming a first trench by etching the n+ type region, the p type region and the n- type layer, and forming a second trench by etching the p+ type region, the p type region and the n- type region;
forming a p-shield region below the lower surface of the first trench;
forming a first insulating film inside the first trench, forming a gate on the first insulating film, and forming a second insulating film on the gate;
forming an n-type region and a first source electrode inside the second trench;
forming a second source electrode on the p+ type region, the n+ type region, the first source electrode, and the second insulating layer; and
Forming a drain electrode on the second side of the substrate,
the first source electrode contacts the n-type region in the second trench to form a Schottky junction,
The n+ type region is located in the same layer as the p+ type region,
The n-type region is located adjacent to the side of the p-type region and the p+-type region,
The first insulating film extends to a portion of the upper surface of the n+ type region,
When the semiconductor device operates as a MOSFET, current flows from the drain electrode to the second source electrode through the n- type layer, the p-type region, and the n+-type region,
When the semiconductor device operates as a diode, current flows from the first source electrode made of a different metal from the second source electrode to the drain electrode through the n-type region and the n-type layer. method. According to clause 11,
A method of manufacturing a semiconductor device wherein the substrate contains an n+ type hydrocarbon. According to clause 11,
The first source electrode includes Schottky metal,
A method of manufacturing a semiconductor device wherein the second source electrode includes an ohmic metal. According to clause 13,
The second source electrode is in contact with the n+ type region and the p+ type to form an ohmic junction. According to clause 13,
A method of manufacturing a semiconductor device wherein the second source electrode is a cathode electrode and the drain electrode is an anode electrode.

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