KR102613898B1 - Display device - Google Patents

Abstract

The display device includes a first region including a plurality of first region pixel rows having the same number of pixels and a plurality of second region pixel rows each having a smaller number of pixels than the number of pixels included in each of the first region pixel rows. a display panel divided into a second region, including a plurality of stages each connected to a plurality of scan lines respectively connected to pixel rows of the first region and pixel rows of the second region, and corresponding to the pulse width of a clock signal. A scan driver that provides a plurality of scan signals with the same activation level width to the first region pixel rows and the second region pixel rows through stages, respectively, and a plurality of data signals to the display panel through a plurality of data lines. It includes a data driver that provides signals, and a timing controller that changes the pulse width of the clock signal based on the positions of the first area and the second area within one frame period.

Description

Display device {DISPLAY DEVICE}

The present invention relates to electronic devices, and more specifically, to display devices having various display panel shapes.

The display device includes a plurality of pixels that emit light in response to a data signal and a scan driver that outputs a scan signal to write the data signal to the pixels. A difference in the rise time (and fall time) of an output signal (eg, the scan signal) for each scan line occurs due to a load difference for each scan line inside the display panel. In particular, if an opening pattern exists inside the display panel or if the display panel is not square, the load difference becomes severe. Accordingly, the width of the activation level of the scan signals varies for each scan line, and the time at which data is written to each pixel row by the scan signals varies. For example, in the area where the opening pattern exists, the panel load is relatively small compared to other areas, so the rise and fall times of the scan signal are relatively short and the data writing time is short. As a result, the luminance of the area where the opening pattern exists becomes darker than other areas, resulting in luminance non-uniformity.

One object of the present invention is to provide a display device that changes clock pulses based on the load of a pixel row.

Another object of the present invention is to provide a display device that changes clock pulses based on the length of a pixel row.

However, the purpose of the present invention is not limited to the above-mentioned purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention.

In order to achieve an object of the present invention, a display device according to embodiments of the present invention includes a first region including a plurality of first region pixel rows having the same number of pixels, and each of the first region pixel rows. A display panel divided into a second region including a plurality of second region pixel rows, each having a number of pixels less than the number of pixels, a plurality of pixel rows connected to the first region pixel rows and the second region pixel rows, respectively. It includes a plurality of stages each connected to scan lines, and transmits a plurality of scan signals having the same activation level width based on the pulse width of the clock signal through the stages, respectively, to the first region pixel rows and the first region pixel rows. A scan driver that provides two-region pixel rows, a data driver that provides a plurality of data signals to the display panel through a plurality of data lines, and a device based on the positions of the first region and the second region within one frame period. It may include a timing controller that changes the pulse width of the clock signal.

According to one embodiment, the timing controller provides the scan signals to the pixel rows of the first region based on the width of the activation level of the clock signal output during the period in which the scan signals are provided to the pixel rows of the second region. It can be set to be smaller than the width of the activation level of the clock signal output during the interval.

According to one embodiment, the timing controller adjusts and outputs the width of the activation level of the clock signal, so that the width of the activation level of the scan signals can be the same.

According to one embodiment, the number of pixels in at least one of the pixel rows in the second area may be different from the number of pixels in other pixel rows in the second area.

According to one embodiment, the timing controller may change the width of the activation level of the clock signal based on the number of pixels in each of the pixel rows in the second region.

According to one embodiment, as the number of pixels in the second area pixel rows decreases, the width of the activation level of the clock signal may decrease.

According to one embodiment, the number of pixels in each of the pixel rows in the second area may be the same.

According to one embodiment, the width of the activation level of the clock signal output during a period in which the scan signals are provided to the pixel rows of the second area may be the same.

According to one embodiment, the display panel may include an opening pattern in which the pixels do not exist in the second area.

According to one embodiment, the length of the opening pattern in a first direction parallel to the pixel rows in the second region may be uniform.

According to one embodiment, the number of pixels in each of the pixel rows in the second area may be the same.

According to one embodiment, the width of the activation level of the clock signal output during a period in which the scan signals are provided to the pixel rows of the second area may be the same.

According to one embodiment, when the length of the opening pattern in the first direction parallel to the pixel rows of the second area is not uniform, the timing controller is operated during a period in which the scan signals are provided to the pixel rows of the second area. The width of the activation level of the output clock signal may be changed based on the length of the opening pattern in the first direction.

According to one embodiment, the longer the length of the opening pattern in the first direction, the narrower the width of the activation level of the clock signal may be set.

According to one embodiment, as the length of the opening pattern in the first direction increases, the number of pixels in each of the pixel rows in the second area may decrease.

In order to achieve an object of the present invention, a display device according to embodiments of the present invention includes a display panel including a plurality of pixel rows each having a plurality of pixels, a plurality of scan lines connected to the pixel rows, and A scan driver that includes a plurality of stages connected to each other and provides a plurality of scan signals with the same activation level width based on the pulse width of the clock signal to the pixel rows through the stages, respectively, and a plurality of data lines. It may include a data driver that provides a plurality of data signals to the display panel and a timing controller that changes the pulse width of the clock signal based on the length of the pixel rows within one frame period.

According to one embodiment, the length of each pixel row may be determined depending on the shape of the display panel.

According to one embodiment, the timing controller may reduce the width of the activation level of the clock signal as the length of the pixel row becomes shorter.

According to one embodiment, the timing controller may change the width of the activation level of the clock signal based on the number of pixels in each pixel row.

According to one embodiment, the display panel may further include an opening pattern in which the pixels do not exist.

A display device according to embodiments of the present invention includes a display panel including various types of opening areas and pixel rows of various lengths, and a scan driver according to the length of the pixel rows (i.e., the number of pixels in each pixel row). The width of the activation level of the clock signal provided to can be adjusted. Accordingly, the plurality of scan signals having the same activation level width can be output to the display panel regardless of the shape and number of the opening area and the length of the pixel rows. Accordingly, the data writing time of the pixels can be substantially uniform, and the unevenness of the data writing time and luminance unevenness due to the load difference between the first area and the second area can be improved.

Additionally, display devices according to embodiments of the present invention include various types of display panels including pixel rows of various lengths, and operate a scan driver according to the length of the pixel rows (i.e., the number of pixels in each pixel row). The width of the activation level of the provided clock signal can be adjusted. Accordingly, luminance unevenness due to load differences within the display panel can be improved.

However, the effects of the present invention are not limited to the effects described above, and may be expanded in various ways without departing from the spirit and scope of the present invention.

1 is a block diagram showing a display device according to embodiments of the present invention.
FIG. 2 is a diagram illustrating an example of a display panel included in the display device of FIG. 1 .
FIG. 3 is a block diagram illustrating an example of a scan driver included in the display device of FIG. 1 .
FIG. 4 is a circuit diagram showing an example of a stage included in the scan driver of FIG. 3.
FIG. 5 is a timing diagram illustrating an example of the operation of the scan driver of FIG. 3.
FIG. 6 is an enlarged view of a portion of the timing diagram of FIG. 5.
FIG. 7A is a diagram illustrating another example of a display panel included in the display device of FIG. 1.
FIG. 7B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 7A within one frame period.
FIG. 8A is a diagram illustrating another example of a display panel included in the display device of FIG. 1.
FIG. 8B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 8A within one frame period.
Figure 9 is a block diagram showing a display device according to embodiments of the present invention.
FIG. 10A is a diagram illustrating an example of a display panel included in the display device of FIG. 9 .
FIG. 10B is a diagram illustrating another example of a display panel included in the display device of FIG. 9 .
FIG. 10C is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 10A or FIG. 10B within one frame period.
FIG. 11A is a waveform diagram showing an example of the clock signal of FIG. 10C.
FIG. 11B is a waveform diagram showing an example of implementing the clock signal of FIG. 11A.
FIG. 12A is a diagram illustrating another example of a display panel included in the display device of FIG. 9 .
FIG. 12B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 12A within one frame period.
FIG. 13A is a diagram illustrating another example of a display panel included in the display device of FIG. 9 .
FIG. 13B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 13A within one frame period.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

FIG. 1 is a block diagram illustrating a display device according to embodiments of the present invention, and FIG. 2 is a diagram illustrating an example of a display panel included in the display device of FIG. 1 .

Referring to FIGS. 1 and 2 , the display device 1000 may include a display panel 100, a scan driver 200, a data driver 300, and a timing controller 400. In one embodiment, the display device 1000 may further include an emission control driver that generates an emission control signal that controls whether the pixels P emit light.

In one embodiment, the display device 1000 may be an organic light emitting display device.

The display panel 100 can display images. The display panel 100 includes a plurality of scan lines (SL1 to SLn) and a plurality of data lines (DL1 to DLm), and each of the scan lines (SL1 to SLn) and the data lines (DL1 to DLm) It may include a plurality of connected pixels (P). For example, the pixels P may be arranged in a matrix form. In one embodiment, the number of scan lines SL1 to SLn may be n. The number of data lines DL1 to DLm may be m. n and m are natural numbers. In one embodiment, the number of pixels PX may be n m. The spacing of each of the pixels P in the first direction DR1 may be substantially the same. Here, the first direction DR1 refers to a direction parallel to the pixel row.

The pixels P may be divided into a plurality of pixel rows PR1 to PRn corresponding to the scan lines SL1 to SLn. In one embodiment, the number of pixels P in some of the pixel rows PR1 to PRn may be less than the number of pixel rows included in the remaining pixel rows. For example, as shown in FIG. 2, the first area pixel rows MPR included in the first area DA1 may all have the same number of pixels, and the first area pixel rows MPR included in the second area DA2 may have the same number of pixels. The second region pixel rows SPR may have a smaller number of pixels than the number of pixels included in each of the first region pixel rows MPR.

In one embodiment, the display panel 100 may include an opening pattern OP in which no pixel P is present in the second area DA2. Therefore, the number of pixels P included in each of the second region pixel rows SPR overlapping with the opening pattern OP (or adjacent to the left and right of the opening pattern OP) is the number of pixels P included in each of the first region pixel rows ( MPR) may be less. That is, the length of the second region pixel rows SPR may be shorter than the length of the first region pixel rows MPR. Accordingly, the load (or resistance component) of the scan lines connected to the second region pixel rows SPR may be smaller than the load of the scan lines connected to the first region pixel rows MPR.

In one embodiment, the pixel P, data line, scan line, and other wiring may not be located in the opening pattern OP. In another embodiment, wires excluding the pixel P may be disposed in the opening pattern OP. In one embodiment, other components of an electronic device including the display device 1000 may be disposed in the opening pattern OP. For example, a camera, lens, various sensors, etc. may be placed in the opening pattern OP. Alternatively, input/output devices such as a speaker, microphone, joystick, or track ball may be disposed in the opening pattern OP.

The opening pattern (OP) may have various forms. For example, the opening pattern OP has a shape such as a square, a circle, an oval, a ring, an S-shape, or a U-shape, and may be located at an arbitrary location on the display panel 100 . Additionally, the display panel 100 may include a plurality of opening patterns OP.

The display panel 100 may also have various shapes. For example, the display panel may have a shape such as a square, a shape with one corner cut off, a circle, or a hexagon, and the length of the pixel rows PR1 to PRn may be determined depending on the shape of the display panel.

The scan driver 200 may include a plurality of stages respectively connected to scan lines SL1 to SLn respectively connected to the first region pixel rows MPR and second region pixel rows SPR. The stages may be connected to each other in a dependent manner. The scan driver 200 sends a plurality of scan signals having the same activation level width through the stages, respectively, based on the pulse width of the clock signal CLK and the first control signal CON1 received from the timing controller 400. It can be provided to the first region pixel rows (MPR) and the second region pixel rows (SPR). In one embodiment, the scan signals may be provided sequentially to pixel rows. The length or load of pixel rows connected to the scan lines SL1 to SLn may be different in the first area DA1 and the second area DA2. Accordingly, a difference may occur between the rise/fall times of the scan signal output from each of the stages, and the turn-on time of the switching transistors included in the stages may vary. The scan driver 200 may receive a clock signal CLK with a variable pulse width from the timing controller 400 based on the length of the pixel row (or the number of pixels in each pixel row, load). The scan driver 200 may adjust the turn-on time of the switching transistors included in each of the stages based on the clock signal CLK.

In one embodiment, the scan driver 200 may be disposed on both sides of the display panel 100. In this case, the scan lines are not arranged while passing through the aperture pattern OP. That is, the scan line may not be disposed in the opening pattern OP. In one embodiment, the scan driver 200 may be placed on one side of the display panel 100. In this case, some scan lines may be connected to the pixels (P) while passing through the opening pattern (OP).

The data driver 300 converts the data signal into an analog data voltage based on the second control signal CON2 received from the timing controller 400 and applies the data voltage to the plurality of data lines DL1 to DLm. It can be approved.

The timing controller 400 may control the operation of the scan driver 200 and the data driver 300. The timing controller 400 may receive an input control signal and an input image signal from an image source such as an external graphics device. The timing controller 400 provides a first control signal (CON1) for controlling the driving timing of the scan driver 200 and a second control signal (CON1) for controlling the driving timing of the data driver 300 based on the input control signal ( CON2) can be created and provided to the scan driver 200 and data driver 300, respectively.

The timing controller 400 may change the pulse width of the clock signal CLK based on the positions of the first area DA1 and the second area DA2 within one frame period. The width of the activation level of the scan signals may be determined according to the width of the activation level of the clock signal CLK. In one embodiment, the timing controller 400 determines the width of the activation level of the clock signal CLK provided to the second region stages connected to the second region pixel rows SPR among the stages. The width of the activation level of the clock signal CLK provided to the first region stages connected to the first region pixel rows MPR may be set to be smaller than the width. Since the second area pixel rows SPR have a small load, the rise/fall time of the output signal of the second area stages is shorter than the rise/fall time of the output signal of the first area stage. That is, by reducing the width of the activation level of the clock signal CLK provided to the second region stages, all pixels P included in the first pixel rows MPR and the second pixel rows SPR. ) (i.e., the activation level sections of the scan signals for all pixel rows) can be made substantially the same.

In one embodiment, the timing controller 400 may change the width of the activation level of the clock signal CLK based on the number of pixels in each of the second region pixel rows SPR. As the number of pixels in the second area pixel rows SPR decreases, the width of the activation level of the clock signal CLK may decrease.

As described above, the display device 1000 according to embodiments of the present invention includes display panels 100 and 100A including various shapes of opening areas OP and pixel rows PR1 to PRn of various lengths. and the width of the activation level of the clock signal CLK provided to the scan driver 200 according to the length of the pixel rows PR1 to PRn (i.e., the number of pixels in each of the pixel rows PR1 to PRn). can be adjusted. Accordingly, the plurality of scan signals having the same activation level width can be output to the display panel 100 regardless of the shape of the display panel 100 and the lengths of the pixel rows PR1 to PRn. Accordingly, the data writing time of the pixels P can be substantially uniform, and the unevenness of the data writing time and luminance unevenness due to the load difference between the first area DA1 and the second area DA2 can be improved. there is.

FIG. 3 is a block diagram illustrating an example of a scan driver included in the display device of FIG. 1 .

Referring to FIG. 3, the scan driver 200 may include a plurality of stages 201, 202, 203, 204, ... that are dependently connected to each other.

Each stage (201, 202, 203, 204, ...) receives scan signals (S[1], S[2], S[3]) provided to each of the plurality of scan lines (SL1 to SLn). , S[4], ...) can be created. However, this is an example, and the signals output by the stages 201, 202, 203, 204, ... are scan signals (S[1], S[2], S[3], S[4], ...) is not limited to this. For example, the signals provided by the stages 201, 202, 203, 204, ... to the display panel include an emission control signal, a sensing signal, an initialization signal, etc. applied to the pixel, depending on the configuration of the transistors included in the pixel. It can correspond.

Each of the plurality of stages (201, 202, 203, 204, ...) includes a first clock signal input terminal (CLK1), a second clock signal input terminal (CLK2), an input signal input terminal (IN), and an output terminal (OUT). can do. A first clock signal (SCLK1) is input to the first clock signal input terminal (CLK1) of the odd-numbered stages (201, 203, ...), and a second clock signal (SCLK2) is input to the second clock signal input terminal (CLK2). can be entered. The second clock signal (SCLK2) is input to the first clock signal input terminal (CLK1) of the even-numbered scan driving blocks (202, 204, ...), and the first clock signal (SCLK1) is input to the second clock signal input terminal (CLK2). ) can be entered.

[Stages 201, 202, 203, 204, ...) are connected to the first clock signal (SCLK1), the second clock signal (SCLK2), the signal input to the input signal input terminal (IN), and the power supply voltage (VGH). Scan signals (S[1], S[2], S[3], S[4], ...) can be output sequentially.

The first stage 201 receives the scan start signal (SSP) and sends the generated first scan signal (S[1]) to the first scan line (SL1) and the input signal input terminal (IN) of the second stage 202. It can be delivered to . The kth stage may receive the scan signal output from the k-1th stage and output the generated kth scan signal. Here, k is a natural number between 2 and n.

Each of the stages 201, 202, 203, 204, ... clock signals (CLK1, CLK2) having an activation level width determined according to the length (or load of the pixel rows) of each of the corresponding pixel rows. can be provided.

FIG. 4 is a circuit diagram showing an example of a stage included in the scan driver of FIG. 3.

Referring to FIG. 4, the stage may include first to sixth transistors (M1, M2, M3, M4, M5, M6) and first and second capacitors (C1, C2).

Hereinafter, the structure and operation of the display device and scan driver 200 will be described in terms of a structure using a P-channel oxide metal semiconductor (PMOS) transistor. However, this is an example, and the structure is not limited to this. For example, an N-channel oxide metal semiconductor (NMOS) transistor may be applied to the scan driver 200 and the pixels.

The first transistor M1 may include a gate electrode connected to the first node QB, a first electrode connected to the power supply voltage VGH, and a second electrode connected to the output terminal OUT. The second transistor M2 may include a gate electrode connected to the second node Q, a second electrode connected to the second clock signal input terminal CLK2, and a second electrode connected to the output terminal OUT. The third transistor M3 may include a gate electrode connected to the first node QB, a first electrode connected to the input signal input terminal IN, and a second electrode connected to the second node Q. The fourth transistor M4 may include a gate electrode connected to the first clock signal input terminal CLK1, a first electrode connected to the input signal input terminal IN, and a second electrode connected to the second node Q. there is. The fifth transistor M5 includes a gate electrode connected to the first clock signal input terminal CLK1, a first electrode connected to the first clock signal input terminal CLK1, and a second electrode connected to the first node QB. can do. The sixth transistor T6 may include a gate electrode connected to the second node Q, a first electrode connected to the first clock signal input terminal CLK1, and a second electrode connected to the first node QB. there is. The first capacitor C1 includes a first electrode connected to the second node Q and a second electrode connected to the output terminal OUT, and the second capacitor C2 is connected to the first node QB. It may include a first electrode and a second electrode connected to the power voltage (VGH). Here, the power voltage VGH may have a logic high level voltage (i.e., turn-off voltage, deactivation voltage).

The stage may output a scan signal based on the output (or scan start signal) of the previous stage and the first and second clock signals CLK1 and CLK2. In one embodiment, the activation level (i.e., the turn-on voltage, logic low level) of the scan signal output from the output terminal (OUT) is applied to the second clock signal input terminal (CLK) by the second transistor (M2). It can be output in synchronization with the activation level of the clock signal. Accordingly, the width of the activation level of the scan signal may be determined by the width of the activation level of the clock signal.

FIG. 5 is a timing diagram illustrating an example of the operation of the scan driver of FIG. 3.

Referring to FIGS. 1 to 5, the scan driver 200 may sequentially output a plurality of scan signals (S[1], S[2], ...) during one frame period (1FRAME). . The first section P1 and the third section P3 are sections in which scan signals are sequentially provided to the first area DA1 of the display panel 100A, and the third section P2 is a section in which the scan signal is sequentially provided to the first area DA1 of the display panel 100A. This is a section in which scan signals are sequentially provided to the second area DA2.

When the scan start signal (SSP) and the first clock signal (SCLK1) having an activation level (L) are applied, the fourth and fifth transistors (T4 and T5) of the first stage 201 are turned on and activated. The first clock signal SCLK1 of level L may be transmitted to the first node QB. The first and third transistors (T1, T3) are turned on by the activation level (L) of the first node (QB), and the scan start signal (SSP) of the activation level (L) is turned on by the second node (Q) can be provided. The second transistor T2 is turned on by the activation level (L) of the second node (Q), and the second clock signal (SCLK2) of the deactivation level (H) can be transmitted to the output terminal. At this time, the first capacitor C1 may be charged by the voltage of the deactivation level (H) of the output terminal (OUT) and the voltage of the activation level (L) of the second node (Q).

Afterwards, the scan start signal (SSP) and the first clock signal (SCLK1) change to the deactivation level (H), and the second clock signal (SCLK2) at the activation level (L) may be applied. The fourth transistor M4 and the fifth transistor M15 may be turned off by the first clock signal SCLK1. As the second clock signal (SCLK2) changes from the deactivation level (H) to the activation level (L), the voltage of the second node (Q) is bootstrapped by the first capacitor (C1), and the second transistor (M2) can be fully turned on. The second clock signal (SCLK2) of the Hwasehwa level (L) is transmitted to the output terminal (OUT) through the turned-on second transistor (M2), and the first scan signal (S[1]) of the activation level (L) is output. It can be. The first scan signal S[1] may be provided to the input terminal IN of the second stage 202 and may be provided to the first pixel row PR1 through the first scan line SL1.

Afterwards, the second clock signal SCLK2 may change to the deactivation level (H), and the first clock signal (SCLK1) may change back to the activation level (L). Through the above-described operation, the first scan signal (S[1]) changes to the deactivation level (H), and the second scan signal (S[2]) at the activation level (L) may be output. Accordingly, all scan signals can be sequentially output during one frame period (FRAME1).

In one embodiment, the widths W1 of the first and second clock signals SCLK1 and SCLK2 in the first and third sections P1 and P3 that output scan signals for the first area DA1 ( Hereinafter, the first widths (W1) may be the same. This is because the first area DA1 includes the first area pixel rows MPR having the same number of pixels, so the load of the output line (or scan line) is substantially the same. For example, the first width W1 may be substantially equal to one horizontal period 1H.

During the second period P2, scan signals may be provided to the second area pixel rows SPR of the second area DA2. The activation levels L of the first and second clock signals SCLK1 and SCLK2 output during the second period P2 may have a second width W2. As shown in FIG. 2, since the number of pixels in each of the second area pixel rows (SPR) (or the length of each of the second area pixel rows (SPR)) is the same, the second widths W2 are the same. can do.

Since the load of the second area pixel rows (SPR) is smaller than the load of the first area pixel rows (MPR), the first and second clock signals (SCLK1, SCLK2) are activated in the second period (P2) By making the width W2 of the levels L shorter than the first width W1, the gate driver 200 can output the widths of the activation levels L of all scan signals to be substantially the same.

Accordingly, the data writing time of all pixels P may be substantially the same, and the overall luminance of the display panel 100A including the opening area OP may become uniform.

Since the scan signal is provided to the first area pixel rows MPR of the first area DA1 below the second area DA2 during the third period P3, the first and second clock signals SCLK1 and SCLK2 The activation levels (L) of ) may again have a first width (W1).

As described above, the first and second clock signals SCLK1 and SCLK2 are input to the scan driver 200 based on the length of the pixel rows (i.e., the number of pixels included in the pixel rows, the load of the pixel rows). By adjusting the width of the activation level (L), the width of the activation level (L) of the entire scan signal can be made substantially the same. Accordingly, the data writing time for all pixels P of the display panel 100A may be substantially the same.

FIG. 6 is an enlarged view of a portion of the timing diagram of FIG. 5.

5 and 6, the first width W1 is the width W1 of the clock signal SCLK_P1 in the first section P1 and the width W1 of the clock signal SCLK_P2 in the second section P2 is The second width W2 may be set differently.

Since the second region pixel rows (SPR) have a smaller load than the first region pixel rows (MPR), the rise/fall time of the output signal of the second region stages is the rise/fall time of the output signal of the first region stages. It is shorter than the descent time.

In one embodiment, the second width W2 may be shorter than the first width W1. Since the load of the second region pixel rows (SPR) corresponding to the second section (P2) is smaller than the load of the first region pixel rows (MPR) corresponding to the first section (P1), the second section (P2) ) by making the width (W2) of the activation levels (L) of the first and second clock signals (SCLK1, SCLK2) shorter than the first width (W1), the gate driver 200 activates all scan signals. The widths W3 and W4 of the level L can be output as substantially the same. That is, as shown in FIG. 6, the width W3 of the scan signal S[DA1] in the first area DA1 is the width W3 of the scan signal S[DA2] in the second area DA2. It may be substantially the same as (W4).

Accordingly, the data writing time for all pixels P of the display panel 100A including the opening pattern OP is substantially the same, and luminance uniformity of the entire display panel 100A can be improved.

FIG. 7A is a diagram showing another example of a display panel included in the display device of FIG. 1, and FIG. 7B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 7A within one frame period. .

Referring to FIGS. 7A and 7B , the display panel 100B may be divided into first areas DA11 and DA12 and second areas DA2.

In one embodiment, as shown in FIG. 7A , the second area DA2 may include a circular opening pattern OP. Accordingly, the lengths L11 and L21 of the opening pattern in the second area DA2 in the first direction DR1 are not uniform, and the lengths L12 and L22 of the pixel rows in the second area are also not uniform. Since the lengths (L12, L22) of the pixel rows in the second area are shorter than the length (L) of the pixel rows in the first area, the load of the second area (DA2) is smaller than the load of the first area (DA1). In one embodiment, as the lengths (L11, L21) of the opening pattern (OP) become longer, the lengths (L12, L22) of the second area pixel rows become shorter, and the number of pixels included in the second area pixel rows increases. may decrease.

As shown in FIG. 7B, the timing controller 400 can change the width of the activation level of the clock signal SCLK1 according to the length of the pixel row (i.e., the load of the pixel row) within one frame period.

The width W1 of the activation level of the clock signal SCLK1 may be the same during a period corresponding to the scan signal output to the first areas DA11 and DA12. The widths (W21, W22, W23) of the activation level of the clock signal (SCLK1) during the period corresponding to the scan signal output to the second area (DA2) are the widths (W21, W22, W23) corresponding to the scan signal output to the first area (DA11, DA12). It is shorter than the width (W1) of the activation level of the clock signal (SCLK1) during the section.

In one embodiment, the timing controller 400 adjusts the widths (W21, W22, W23) of the activation level of the clock signal (SCLK1) output during the period in which the scan signals are provided to the pixel rows of the second area to the second area pixel rows. It can be changed based on the length of the pixel row (L12, L22). In one embodiment, as shown in FIG. 7B, the longer the length (L12, L22) of the second area pixel rows (L12, L22) or the smaller the number of pixels in the second area pixel rows (L12, L22), the lower the clock signal (SCLK1). ) The width (W21, W22, W23) of the activation level can be set narrow. Therefore, when scan output to the second area DA2 is performed, the widths (W21, W22, W23) of the activation level of the clock signal (SCLK1) change depending on the lengths (L12, L22) of the pixel rows in the second area. You can.

In one embodiment, a camera, a lens, various sensors, etc. may be disposed in the opening pattern OP. Alternatively, input/output devices such as a speaker, microphone, joystick, or trackball may be disposed in the opening pattern OP.

FIG. 8A is a diagram showing another example of a display panel included in the display device of FIG. 1, and FIG. 8B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 8A within one frame period. am.

Referring to FIGS. 8A and 8B , the display panel 100C may be divided into first areas DA11, DA12, and DS13 and second areas DA21 and DA22.

In one embodiment, as shown in FIG. 8A , the display panel 100C may include a plurality of opening patterns OP1 and OP2. For example, it may include first and second opening patterns OP1 and OP2 having different lengths L11 and L21. Accordingly, the length L12 of the pixel rows in the second area DA21 where the first opening pattern OP1 is located is the length L22 of the pixel rows in the second area DA22 where the second opening pattern OP2 is located. ) can be shorter than

As shown in FIG. 8B, the timing controller 400 can change the width of the activation level of the clock signal SCLK1 according to the length of the pixel row (i.e., the load of the pixel row) within one frame period.

The width W1 of the activation level of the clock signal SCLK1 may be the same during a period corresponding to the scan signal output to the first area DA11, DA12, and DA13.

The width W2 of the activation level of the clock signal SCLK1 may be the same during a period corresponding to the scan signal output for the second area DA21 where the first opening pattern OP1 is located.

The width W3 of the activation level of the clock signal SCLK1 may be the same during a period corresponding to the scan signal output for the second area DA22 where the second opening pattern OP2 is located.

However, since the length L11 of the first opening pattern OP1 is longer than the length L21 of the second opening pattern OP2, the width W2 of the activation level of the clock signal SCLK1 is greater than the length L21 of the second opening pattern OP2. It may be shorter than the width (W3) of the activation level.

In one embodiment, a camera, a lens, various sensors, etc. may be disposed in the opening pattern OP. Alternatively, input/output devices such as a speaker, microphone, joystick, or trackball may be disposed in the opening pattern OP.

Figure 9 is a block diagram showing a display device according to embodiments of the present invention.

In FIG. 9, the same reference numerals are used for components described with reference to FIGS. 1 and 2, and overlapping descriptions of these components will be omitted. Additionally, the display device 2000 of FIG. 9 may have a substantially same or similar configuration as the display device 1000 of FIG. 1 except for the display panel 110.

Referring to FIG. 9 , the display device 2000 may include a display panel 110, a scan driver 200, a data driver 300, and a timing controller 400. In one embodiment, the display device 1000 may further include an emission control driver that generates an emission control signal that controls whether the pixels P emit light.

The display panel 110 can display images. The display panel 110 includes a plurality of scan lines (SL1 to SLn) and a plurality of data lines (DL1 to DLm), and each of the scan lines (SL1 to SLn) and the data lines (DL1 to DLm) It may include a plurality of connected pixels (P). The display panel 110 may have various shapes (notch shapes). For example, the display panel 110 may have a shape such as a shape with one corner cut off, a circle, a hexagon, or a triangle.

The pixels P may be divided into a plurality of pixel rows SPR and MPR corresponding to the scan lines SL1 to SLn. The length of the pixel rows (SPR, MPR) may be determined depending on the shape of the display panel 110. For example, as shown in FIG. 9 , the display panel 110 may have a shape in which part of an edge is cut off. At this time, the length of the pixel rows (SPR) located in the second area (DA2) including the portion with the corner cut off is the length of the pixel rows (SPR) located in the first area (DA1) corresponding to the remaining portion of the display panel 110. It may be shorter than the length of the MPR. In one embodiment, the number of pixels in each pixel row SPR of the second area DA2 may be less than the number of pixels in each pixel row MPR of the first area DA1.

In one embodiment, the display panel 110 may further include an opening pattern in which no pixels exist. The opening pattern may have various shapes. For example, the opening pattern has a shape such as a square, circle, oval, ring, S-shape, or U-shape, and may be located at any position on the display panel 110. Other components of an electronic device, including the display device 2000, may be disposed in the opening pattern. For example, cameras, lenses, various sensors, etc. may be placed in the opening pattern. Alternatively, input/output devices such as speakers, microphones, joysticks, and trackballs may be disposed in the opening pattern.

The scan driver 200 may include a plurality of stages each connected to scan lines SL1 to SLn respectively connected to the pixel rows SPR and MPR. The stages may be connected to each other in a dependent manner. The scan driver 200 sends a plurality of scan signals having the same activation level width through the stages, respectively, based on the pulse width of the clock signal CLK and the first control signal CON1 received from the timing controller 400. It can be provided to pixel rows (SPR, MPR). In one embodiment, the scan signals may be provided sequentially to pixel rows.

The data driver 300 converts the data signal into an analog data voltage based on the second control signal CON2 received from the timing controller 400 and applies the data voltage to the plurality of data lines DL1 to DLm. It can be approved.

The timing controller 400 may control the operation of the scan driver 200 and the data driver 300. The timing controller 400 may change the pulse width of the clock signal CLK based on the positions of the first area DA1 and the second area DA2 within one frame period. The width of the activation level of the scan signals may be determined according to the width of the activation level of the clock signal CLK. In one embodiment, the timing controller 400 may reduce the width of the activation level of the clock signal CLK as the length of the pixel rows SPR and MPR becomes shorter. Alternatively, in one embodiment, the timing controller 400 may change the width of the activation level of the clock signal CLK based on the number of pixels in each pixel row. For example, as the number of pixels decreases, the width of the activation level of the clock signal CLK for the corresponding scan signal may decrease.

As described above, the display device 2000 according to embodiments of the present invention includes various types of display panels 110 including pixel rows (SPR, MPR) of various lengths, and pixel rows (SPR) , MPR) (i.e., the number of pixels in each of the pixel rows (SPR, MPR)) can be adjusted to adjust the width of the activation level of the clock signal (CLK) provided to the scan driver 200. Accordingly, the plurality of scan signals having the same activation level width can be output to the display panel 110 regardless of the shape of the display panel 110 and the lengths of the pixel rows (SPR, MPR). Accordingly, the data writing time of the pixels P can be substantially uniform, and the unevenness of the data writing time and luminance unevenness due to the load difference inside the display panel 110 can be improved.

FIG. 10A is a diagram showing an example of a display panel included in the display device of FIG. 9, FIG. 10B is a diagram showing another example of a display panel included in the display device of FIG. 9, and FIG. 10C is a diagram showing an example of a display panel included in the display device of FIG. 9. FIG. This is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 10A or FIG. 10B.

Referring to FIGS. 10A to 10C , the display panel 110A may be divided into a first area DA1 and a second area DA2.

In one embodiment, as shown in FIG. 10A, the length L12 of the second area DA2 in the first direction DR1 is longer than the length of the first area DA1 in the first direction DR1. short. Accordingly, the length of the pixel rows in the second area DA2 may be shorter than the length of the pixel rows in the first area DA1. The load of the second area DA2 may be smaller than the load of the first area DA1.

As shown in FIG. 10B, a portion where pixels are not disposed may be located in the middle of the second area DA2 of the display panel 110B. However, since the configuration and operation of the display panel 110B of FIG. 10B and the operation of the clock signal SCLK1 are similar or substantially the same as the configuration and operation of the display panel 110A of FIG. 10A, overlapping descriptions will be omitted.

As shown in FIG. 10C, the timing controller 400 can change the width of the activation level of the clock signal SCLK1 according to the length of the pixel row (i.e., the load of the pixel row) within one frame period.

The width W1 of the activation level of the clock signal SCLK1 may be the same during the period corresponding to the scan signal output to the first area DA1.

The width W2 of the activation level of the clock signal SCLK1 may be the same during the period corresponding to the scan signal output to the second area DA2. However, since the length L12 of the second area DA2 is shorter than the length L of the first area DA1, the width W2 of the activation level of the clock signal SCLK1 corresponding to the second area DA2 ) may be shorter than the width W1 of the activation level of the clock signal SCLK1 corresponding to the first area DA1.

FIG. 11A is a waveform diagram showing an example of the clock signal of FIG. 10C, and FIG. 11B is a waveform diagram showing an example of implementing the clock signal of FIG. 11A.

Referring to FIGS. 10C to 11B, the timing controller 400 can change the width of the activation level of the clock signal SCLK1 according to the length of the pixel row (i.e., the load of the pixel row) within one frame period. .

FIGS. 11A and 11B show examples of enlarged portions of the clock signal SCLK1 of FIG. 10C. In one embodiment, the transition time of the clock signal SCLK1 in the section for outputting the scan signals for the second area DA2 is the clock signal for the section for outputting the scan signals for the first area DA1. It can be set longer than the transition time of the signal (SCLK2). That is, the second falling period FT2 of the clock signal SCLK1 corresponding to the second area DA2 is longer than the first falling period FT1 of the clock signal SCLK1 corresponding to the first area DA1. can be set. In addition, the second rising period RT2 of the clock signal SCLK1 corresponding to the second area DA2 is longer than the first rising period RT1 of the clock signal SCLK1 corresponding to the first area DA1. It can also be set. Control of the rising and falling sections of the clock signal SCLK1 may be performed by a timing controller. For example, the length of the rising and falling sections of the clock signal SCLK1 may be controlled based on a change in the frequency of a dot clock provided to the timing controller. Alternatively, the length of the rising and falling sections of the clock signal SCLK1 may be controlled by controlling the rising and/or falling timing of the first clock signal SCLK1 in response to a predetermined clock number of the dot clock.

As a result, the width W2 of the activation level L of the clock signal SCLK1 corresponding to the second area DA2 is greater than the width W2 of the activation level L of the clock signal SCLK1 corresponding to the first area DA1. It has the effect of becoming longer than the width (W1). Accordingly, the data writing time for all pixels can be substantially the same, and the overall luminance of the display panel including the opening area (or notch) can be made uniform. Furthermore, the luminance deviation in the low luminance area can be more precisely corrected by controlling the length of the second falling section FT2 and/or the second rising section RT2 of the clock signal SCLK1.

Figure 11b shows an example of increasing the rising and falling sections of the clock signal (SCLK1). In one embodiment, a step is placed in the second rising section RT2 and the second falling section FT2 corresponding to the second area DA2 to form two rising sections RT2 and the second falling section FT2. The length can be increased. A predetermined intermediate voltage level (M) is set between the logic high level (H, e.g., deactivation level) and the logic low level (L, e.g., enable level), and the transition of the clock signal (SCLK1) is at the intermediate level. It can go through voltage level (M). For example, if the logic high level (H) is about 7V and the logic low level (L) is about -8V, the intermediate voltage level (M) can be determined as the ground voltage. In one embodiment, the transition of the clock signal SCLK1 may be generated by a charge sharing method. In addition, the rising and falling periods of the clock signal (SCLK1) are controlled by controlling the frequency of the dot clock or controlling the rising and/or falling timing of the clock signal (SCLK1) in response to a predetermined clock number of the dot clock. The length of can be controlled.

Accordingly, the data writing time for all pixels can be substantially the same, and the overall luminance of the display panel including the opening area (or notch) can be made uniform. Furthermore, the luminance deviation in the low luminance area can be more precisely corrected by controlling the length of the second falling section FT2 and/or the second rising section RT2 of the clock signal SCLK1.

FIG. 12A is a diagram showing another example of a display panel included in the display device of FIG. 9, and FIG. 12B is a waveform diagram showing an example of signals output to drive the display panel of FIG. 12A within one frame period. .

Referring to FIGS. 12A and 12B , the display panel 110C may have a trapezoidal shape. That is, the lengths L1 and L2 of the display panel 110C (and the pixel row) in the first direction DR1 may become shorter as the second direction DR2 increases. Accordingly, the load on the display panel 110C may decrease in the second direction DR2.

As shown in FIG. 12B, the timing controller 400 can change the width of the activation level of the clock signal SCLK1 according to the length of the pixel row (i.e., the load of the pixel row) within one frame period. That is, as the scan operation progresses, the width (W) of the activation level of the clock signal (SCLK1) applied to the scan driver may gradually decrease. Accordingly, regardless of the shape of the display panel 110C, the length of the pixel rows, and the deviation of the panel load, the effective time of the scan operation (or data writing operation) for all pixel rows can be substantially the same.

FIG. 13A is a diagram showing another example of a display panel included in the display device of FIG. 9, and FIG. 13B is a waveform diagram showing an example of a clock signal output to drive the display panel of FIG. 13A within one frame period. am.

Referring to FIGS. 13A and 13B , the display panel 110D may be implemented in a circular shape. That is, the lengths L1 and L2 of the display panel 110D in the first direction DR1 are not uniform. As shown in FIG. 12B, the timing controller 400 can change the width of the activation level of the clock signal SCLK1 according to the length of the pixel row (i.e., the load of the pixel row) within one frame period. That is, as the scan operation progresses, the width (W) of the activation level of the clock signal (SCLK1) applied to the scan driver may gradually increase and then decrease again. Accordingly, regardless of the shape of the display panel 110C, the length of the pixel rows, and the deviation of the panel load, the effective time of the scan operation (or data writing operation) for all pixel rows can be substantially the same.

The present invention can be applied to various electronic devices equipped with a display device. For example, the present invention can be applied to computers, laptops, mobile phones, smartphones, smart pads, PMPs, PDAs, MP3 players, digital cameras, video camcorders, etc.

Although the present invention has been described above with reference to embodiments, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it is possible.

100, 110: Display panel 200: Scan driver
300: data driver 400: timing controller
1000, 2000: display device SCLK1: first clock signal
SCLK2: second clock signal

Claims (20)

A first region including a plurality of first region pixel rows having the same number of pixels, and a plurality of second region pixel rows each having a smaller number of pixels than the number of pixels included in each of the first region pixel rows. a display panel divided into a second area;
and a plurality of stages each connected to a plurality of scan lines respectively connected to the first region pixel rows and the second region pixel rows, and having the same activation level width based on the pulse width of the clock signal. a scan driver that provides a plurality of scan signals to the first region pixel rows and the second region pixel rows through the stages, respectively;
a data driver providing a plurality of data signals to the display panel through a plurality of data lines; and
A timing controller that changes the pulse width of the clock signal based on the positions of the first area and the second area within one frame period,
The timing controller changes the width of the activation level of the clock signal based on the number of pixels in the pixel row. The method of claim 1, wherein the timing controller determines the width of the activation level of the clock signal output during a period in which the scan signals are provided to the pixel rows of the second region by allowing the scan signals to be applied to the pixel rows of the first region. A display device characterized in that the width of the activation level of the clock signal output during the provided period is set to be smaller than the width. The display device of claim 2, wherein the timing controller adjusts and outputs the width of the activation level of the clock signal, so that the widths of the activation levels of the scan signals are the same. The display device of claim 2, wherein the number of pixels in at least one of the pixel rows in the second area is different from the number of pixels in other pixel rows in the second area. The display device of claim 4, wherein the timing controller changes the width of the activation level of the clock signal based on the number of pixels in each of the pixel rows in the second area. The display device of claim 4, wherein as the number of pixels in the pixel rows of the second area decreases, the width of the activation level of the clock signal decreases. The display device of claim 2, wherein the number of pixels in each of the pixel rows in the second area is the same. The display device of claim 7, wherein the widths of the activation levels of the clock signals output during a period in which the scan signals are provided to the pixel rows of the second area are equal to each other. The display device of claim 2, wherein the display panel includes an opening pattern in which no pixels exist in the second area. The display device of claim 9, wherein the length of the opening pattern in a first direction parallel to the pixel rows of the second region is uniform. The display device of claim 10, wherein the number of pixels in each of the pixel rows in the second area is the same. The display device of claim 10, wherein the widths of the activation levels of the clock signals output during a period in which the scan signals are provided to the pixel rows of the second area are the same. The method of claim 9, wherein when the length of the opening pattern in the first direction parallel to the pixel rows of the second area is not uniform, the timing controller performs a period in which the scan signals are provided to the pixel rows of the second area. A display device characterized in that the width of the activation level of the output clock signal is changed based on the length of the opening pattern in the first direction. The display device of claim 13, wherein the width of the activation level of the clock signal is set to be narrower as the length of the opening pattern in the first direction becomes longer. The display device of claim 13, wherein as the length of the opening pattern in the first direction increases, the number of pixels in each of the pixel rows in the second area decreases. a display panel including a plurality of pixel rows each having a plurality of pixels;
A plurality of stages are each connected to a plurality of scan lines connected to the pixel rows, and a plurality of scan signals having the same activation level width are transmitted through the stages, respectively, based on the pulse width of the clock signal. A scan driver that provides for doing things;
a data driver providing a plurality of data signals to the display panel through a plurality of data lines; and
A display device comprising a timing controller that changes the pulse width of the clock signal based on the length of the pixel rows within one frame period. The display device of claim 16, wherein the length of each pixel row is determined depending on the shape of the display panel. The display device of claim 17, wherein the timing controller reduces the width of the activation level of the clock signal as the length of the pixel row becomes shorter. The display device of claim 16, wherein the timing controller changes the width of the activation level of the clock signal based on the number of pixels in each of the pixel rows. The display device of claim 16, wherein the display panel further includes an opening pattern in which the pixels do not exist.

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